- Email: [email protected]
Enhanced electrical characteristics of FinFET by rapid-thermal-and-laser annealing with suitable power
Microelectronic Engineering 178 (2017) 56–60
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Research paper
Enhanced electrical characteristics of FinFET by rapid-thermal-and-laser annealing with suitable power Dun-Bao Ruan, Kuei-Shu Chang-Liao ⁎, Yan-Lin Li, Hao-Ting Feng, Yi-Wen Hsu, Chin-Hsiu Huang, Shang-Fu Tsai, Meng-Ying Yang Department of Engineering and System Science, National Tsing Hua University, Hsinchu 30013, Taiwan ROC
a r t i c l e
i n f o
Article history: Received 20 February 2017 Received in revised form 7 April 2017 Accepted 27 April 2017 Available online 03 May 2017 Keywords: FinFET Microwave annealing Rapid thermal annealing Laser annealing
a b s t r a c t In order to improve electrical characteristics of FinFETs, various annealing treatments for dopant activation were studied in this work. The treatments including rapid thermal annealing (RTA), microwave annealing, and RTAand-laser annealing with different powers were investigated. The on-current and carrier mobility of FinFET are significantly improved by a RTA-and-laser annealing with suitable power; meanwhile, the leakage current, interface characteristics and device reliability can be simultaneously maintained. The improvement can be attributed to the high thermal activation energy, less dopant diffusion, and enhanced quality of interfacial layer during the gate first processes. Therefore, a RTA-and-laser annealing with suitable power is promising for manufacturing high performance FinFET. © 2017 Elsevier B.V. All rights reserved.
1. Introduction With continuously scaling down the dimension of CMOS devices, the random dopant fluctuation effects that may induce a higher off-state leakage current, uniformity variation, and reliability degradation, are becoming important issues for manufacturing advanced FinFETs [1–6]. To suppress these effects, many annealing treatments for dopant activation were reported recently [7]. A rapid thermal annealing (RTA) was widely used in the industry, but the dopant fluctuation of device with 20-nm gate length and annealed by RTA is not small enough [8]. A microwave annealing process at low temperature, which can restrain the dopant diffusion by a lower thermal activation energy, was implemented to replace the traditional method in recent reports [9–13]. However, the unexpected degradation on electrical performance was observed, which is caused by its insufficient dopant activation. In addition, laser annealing treatments were proposed to achieve better dopant activation, and a shallow junction can also be obtained with some optimal conditions [14–19]. It was reported that a laser annealing with fast ramp down of temperature can significantly reduce the gate leakage current, enhance the dielectric constant (k value), and improve the quality of interfacial layer (IL) in gate first CMOS processes [20]. In this work, FinFET devices were fabricated on silicon-on-insulator (SOI) wafer by gate first processes to investigate the effects of different annealing treatments. RTA, microwave, RTA-and-laser annealing treatments were performed after the conventional ion implantation for the ⁎ Corresponding author. E-mail address: [email protected] (K.-S. Chang-Liao).
http://dx.doi.org/10.1016/j.mee.2017.04.037 0167-9317/© 2017 Elsevier B.V. All rights reserved.
activation of source and drain (S/D). The on/off-current, carrier mobility, gate leakage current, interface traps density (Dit), equivalent oxide thickness at inversion (Tinv), and reliability characteristics of FinFETs were investigated and compared. 2. Experiment The FinFET devices were fabricated on 6-inch p-type SOI (100) wafers by gate first processes. The patterns of dummy fins were defined by I-line lithography. Reactive ion etching (RIE) process was performed to form four parallel fins with a fin height of 40 nm. Then, a 3-nm thick HfO2 was deposited by atomic layer deposition (ALD). Afterward, a 100-nm thick TiN film was deposited by a sputtering to serve as metal gate. After patterning gate stack, phosphorous implantation (at 40 keV with a dose of 5 × 1015 cm−2) was performed. Subsequently, annealing treatments with microwave, RTA, and RTA + laser were applied on different samples. A microwave process was performed at a peak temperature of 400 °C with a power of 300 W for 300 s. The peak temperature was detected by a light pipe and the frequency of the microwave annealing is 5.8 GHz. Control sample was treated with a RTA at 750 °C for 30 s. Some of control samples were treated with additional laser annealing at powers of 2.5 W and 1.5 W, respectively, namely, RTA-and-laser samples. The wavelength, pulse width, and scanning speed of laser source with HIPPO 532QW Nd:YAG are 532 nm, 13 ns, and 25 cm/s, respectively. The sample splits in this work are shown in Table 1. Passivation and metallization processes were performed, followed by a sintering at 400 °C for 30 min to complete device fabrication. The cross-sectional view and detailed process flow of SOI FinFET are shown in Fig. 1.
D.-B. Ruan et al. / Microelectronic Engineering 178 (2017) 56–60
57
Table 1 Sample splits of SOI FinFET in this work.
Sample
Control
2.5 W
Activation
RTA 750 30 s
Laser 2.5 W Laser 1.5 W RTA 750 RTA 750 TiN 100 nm
Metal gate
Microwave MW = 400 300W 300 s
HfO2 3 nm
High-k Channel material Substrate
1.5 W Al-Si-Cu
Contact
Singlec-Si
Hfin = 40 nm Wfin = 20 nm SOI
3. Results and discussion Fig. 2 shows cross-sectional transmission electron microscope (TEM) image of FinFET with TiN/HfO2/Si gate stack. A fin structure is clearly observed, and it is covered with partially crystallized high-k dielectric. The height and width of Si fin are 40 nm and 20 nm, respectively. An IL formed by a H2O2 solution exists between high-k dielectric and Si fin structure, and its thickness is below 0.5 nm. This IL would play an important role on EOT scaling and suppress the influence of interface traps on electrical characteristics of FinFETs. Fig. 3 shows drain current versus gate voltage (ID-VG) of FinFETs with various annealing treatments. The on-currents of samples with RTA-and-laser treatments are about 8 × 10− 5 A/μm, and are much higher than that with other treatments. It can be attributed to the higher dopant activation energy received by the S/D regions. Specially, sample with a RTA-and-laser at a power of 1.5 W shows a lower off-current, which achieves an on/off current ratio of 8 × 106 and a sub-threshold swing (S.S.) of 67 mV/dec. Sample with a RTA-and-laser at a power of 2.5 W shows a larger off-current, which may be due to more dopant diffusion or damage in gate dielectric caused by a laser treatment with a higher power. Sample with a microwave annealing shows a lower offcurrent, but its on-current is clearly degraded, suggesting that the dopant activation in S/D region by using a microwave annealing is not enough. Fig. 4 shows current-voltage (J-V) curves of P/N junctions in FinFETs with various annealing treatments. The junction characteristics of sample with a RTA-and-laser treatment at a power of 1.5 W are better than those of control one. The dopant activation in S/D regions by using a microwave annealing is not enough although a lower reverse current is obtained. The reverse current of sample with a RTA-and-laser treatment at
Fig. 2. Cross-sectional transmission electron microscope (TEM) image of FinFET with TiN/ HfO2/Si gate stack.
a higher power is larger, which may be due to more dopant diffusion during its thermal process. Fig. 5 shows trans-conductance (GM) versus gate voltage (GM-VG) of FinFETs with various annealing treatments. The peak GM value of sample with a RTA-and-laser treatment is much higher than that of control one. The VG values of peak GM for all samples are different, which may be attributed to the changes of physical thickness and k-value of ILs during the gate first processes. Fig. 6 shows electron mobility versus inversion charge density (μ eff -Ninv) of FinFETs with various annealing treatments. Inset figure shows the schematic mechanisms of carrier mobility degradation. The peak electron mobility of FinFET with RTA-and-laser at a power of 1.5 W is about 210 cm2/V-s, which can be due to better activation of S/ D dopant. Besides, with increasing the inversion charge density, the electron mobility values of samples with RTA-and-laser treatments decrease much more slightly than those with other treatments, suggesting that the surface roughness can be reduced with RTA-and-laser treatments. Fig. 7 shows gate leakage current versus gate voltage (JG-VG) curves for FinFETs with various annealing treatments. The leakage current of
Fig. 1. Cross-sectional view and schematic process flow of SOI FinFET in this work.
58
D.-B. Ruan et al. / Microelectronic Engineering 178 (2017) 56–60
Fig. 3. Drain current versus Gate voltage (ID-VG) of FinFETs with various annealing treatments.
Fig. 6. Electron mobility versus inversion charge density (μeff-Ninv) of FinFETs with various annealing treatments. Inset figure shows the schematic mechanisms of carrier mobility degradation.
values, which may be due to its less thermal treatment during the S/D dopant activation in the gate first processes. The sample with RTA-and-laser at a power of 1.5 W shows clear reduction in the gate leakage and slightly smaller Tinv value as compared to control one. The results are consistent with those presented in Fig. 3. Fig. 9 shows interface trap density (Dit) for FinFETs with various annealing treatments. The Dit values were extracted by conductance method using MOS capacitors with the same gate stacks and annealing treatments as FinFETs. With the conductance model, the Dit value can be approximately extracted from (1): [21] Dit ≈
2:5 Gp q ω max
ð1Þ
sample with a microwave annealing is the lowest owing to the fewer traps in its gate dielectric treated by less thermal energy. In comparison with the control one, the gate leakage current can be suppressed by RTA-and-laser treatments. Results indicate that the quality of IL can be improved and dopant diffusion is limited by an annealing with fast ramp down of temperature. Hence, an optimal power condition for a laser annealing is required in the gate first processes. Fig. 8 shows gate leakage current density versus EOT at inversion (JG-Tinv) for FinFETs with various annealing treatments. Sample with a microwave annealing shows the lowest leakage current and Tinv
The GP and ω are equivalent parallel conductance density and angular frequency, respectively. The Dit value of sample with a microwave annealing is the smallest due to fewer damages caused by less thermal energy. Samples with RTA-and-laser treatments show similar Dit values as compared to the control one. Fig. 10 shows threshold voltage shift (Vth-shift) versus F-N stress time (E = 9 MV/cm) for FinFETs with various annealing treatments. The Vth-shift values after 1000 s for sample with a microwave annealing are the smallest owing to fewer oxide traps in high-k dielectric. The V th-shift of sample with RTA-and-laser at a power of 1.5 W is smaller than that of control one, while reliability degradation is serious for sample with RTA-and-laser at a power of 2.5 W. It suggests that the oxide traps are increased after a laser annealing with a higher power. In other words, an optimal power condition of laser annealing is very important for the gate first processes.
Fig. 5. Trans-conductance (GM) versus Gate voltage (GM-VG) of FinFETs with various annealing treatments.
Fig. 7. Gate leakage current versus Gate voltage (JG-VG) curve for FinFETs with various annealing treatments.
Fig. 4. Current-voltage (J-V) curves of P/N junctions in FinFETs with various annealing treatments.
D.-B. Ruan et al. / Microelectronic Engineering 178 (2017) 56–60
Fig. 8. Gate leakage current density versus equivalent oxide thickness at inversion (JG-Tinv) for FinFETs with various annealing treatments.
59
Fig. 11. The degradation of maximum trans-conductance (Gm, max) versus F-N stress time (E = 9 MV/cm) for FinFETs with various annealing treatments.
4. Conclusions Electrical characteristics of FinFETs with various annealing treatments were investigated in this work. FinFET with a RTA-and-laser treatment at suitable conditions shows significant improvement on electrical characteristics, such as on/off current ratio of 8 × 106, S.S. of 67 mV/dec, higher electron mobility, lower gate leakage current, and good reliability, which may be attributed to the better dopant activation and less damage on high-k gate dielectrics. Since a microwave annealing is helpful to obtain low Dit and Tinv, its combination with a laser annealing may provide another way to achieve high performance FinFETs.
Acknowledgment Fig. 9. Interface trap density (Dit) for FinFETs with various annealing treatments.
Fig. 11 shows degradation of maximum trans-conductance (Gm, max) versus F-N stress time (E = 9 MV/cm) for FinFETs with various annealing treatments. The Gm, max degradation values of sample with a microwave annealing are the smallest due to fewer interface traps at gate dielectric/channel. The Gm, max degradation for sample with RTA-andlaser at a power of 1.5 W is only 6%. However, the Gm, max degradation of sample with RTA-and-laser at a power of 2.5 W is 16%, which may be attributed to more interface traps generated by higher thermal energy.
Fig. 10. The threshold voltage shift (Vth shift) versus F-N stress time (E = 9 MV/cm) for FinFETs with various annealing treatments.
The authors would like to thank the Ministry of Science and Technology of Taiwan (MOST 105-2221-E-007 -108 -MY3), the Republic of China (R.O.C.) for financial support. The technical supports from National Nano Device Laboratories (NDL), Taiwan, R.O.C. are also acknowledged. References [1] Changho Shin, Jeong-Kyu Kim, Gwang-Sik Kim, Hyunjae Lee, Changhwan Shin, Jong-Kook Kim, Byung Jin Cho, Hyun-Yong Yu, IEEE Trans. Electron Devices 63 (2016) 4167–4172. [2] Yiming Li, Han-Tung Chang, Chun-Ning Lai, Pei-Jung Chao, Chieh-Yang Chen, IEDM Tech. (2015) 34.4.1–34.4.4. [3] Nauman Z. Butt, Jeffrey B. Johnson, IEEE Electron Device Lett. 33 (2012) 1099–1101. [4] Greg Leung, Chi On Chui, IEEE Electron Device Lett. 33 (2012) 767–769. [5] Nobuyuki Sugii, Ryuta Tsuchiya, Takashi Ishigaki, Yusuke Morita, Hiroyuki Yoshimoto, Shin'ichiro Kimura, IEEE Trans. Electron Devices 57 (2010) 835–845. [6] Yiming Li, Chih-Hong Hwang, Tien-Yeh Li, Ming-Hung Han, IEEE Trans. Electron Devices 57 (2010) 437–447. [7] Shinichi Kato, Takayuki Aoyama, Takashi Onizawa, Kazuto Ikeda, Yuzuru Ohji, VLSI Symp. Tech. (2010) 71–72. [8] S. Shimizu, T. Kuroi, Y. Kawasaki, T. Tsutsumi, H. Oda, M. Inuishi, H. Miyoshi, VLSI Symp. Tech. (1996) 64–65. [9] Rui Zhang, Junkang Li, Feng Chen, Yi Zhao, IEEE Trans. Electron Devices 7 (2016) 2665–2670. [10] Hsin-Hui Hu, Kai-Min Wang, IEEE Trans. Electron Devices 62 (2015) 2883–2887. [11] Fu-Kuo Hsueh, Yao-Jen Lee, Kun-Lin Lin, Michael I. Current, Ching-Yi Wu, TienSheng Chao, IEEE Trans. Electron Devices 58 (2011) 2088–2093. [12] Yao-Jen Lee, Ta-Chun Cho, Shang-Shiun Chuang, Fu-Kuo Hsueh, Yu-Lun Lu, Po-Jung Sung, Hsiu-Chih Chen, Michael I. Current, Tseung-Yuen Tseng, Tien-Sheng Chao, Chenming Hu, Fu-Liang Yang, IEEE Trans. Electron Devices 61 (2014) 651–665. [13] Yao-Jen Lee, Shang-Shiun Chuang, Fu-Kuo Hsueh, Ho-Ming Lin, Shich-Chuang Wu, Ching-Yi Wu, Tseung-Yuen Tseng, IEEE Electron Device Lett. 32 (2011) 194–196. [14] I-Hsieh Wong, Fang-Liang Lu, Shih-Hsien Huang, Hung-Yu Ye, Chun-Ti Lu, Jhih-Yang Yan, Yu-Cheng Shen, Yu-Jiun Peng, Huang-Siang Lan, C.W. Liu, IEDM Tech. (2016) 33.6.1–33.6.4. [15] Q. Zhang, J. Huang, N. Wu, G. Chen, M. Hong, L.K. Bera, C. Zhu, IEEE Electron Device Lett. 27 (2006) 728–730. [16] C. Fenouillet-Beranger, B. Mathieu, B. Previtali, M.-P. Samson, N. Rambal, V. Benevent, S. Kerdiles, J.-P. Barnes, D. Barge, P. Besson, R. Kachtouli, M. Cassé, X. Garros, A. Laurent, F. Nemouchi, K. Huet, I. Toqué-Trésonne, D. Lafond, H. Dansas, F. Aussenac, G. Druais, P. Perreau, E. Richard, S. Chhun, E. Petitprez, N. Guillot, F.
60
D.-B. Ruan et al. / Microelectronic Engineering 178 (2017) 56–60
Deprat, L. Pasini, L. Brunet, V. Lu, C. Reita, P. Batude, M. Vinet, IEDM Tech. (2014) 27.5.1–27.5.4. [17] William Hsu, Feng Wen, Xiaoru Wang, Yun Wang, Andrei Dolocan, Anupam Roy, Taegon Kim, Emanuel Tutuc, Sanjay K. Banerjee, IEEE Trans. Electron Devices 64 (2017) 346–352. [18] William Hsu, Taegon Kim, Alfredo Benítez-Lara, Harry Chou, Andrei Dolocan, Amritesh Rai, M. Josefina, Arellano-Jiménez, Marylene Palard, Miguel JoséYacamán, Sanjay K. Banerjee, J. Appl. Phys. 120 (2016), 015701.
[19] William Hsu, Xiaoru Wang, Feng Wen, Yun Wang, Andrei Dolocan, Taegon Kim, Emanuel Tutuc, Sanjay K. Banerjee, IEEE Electron Device Lett. 37 (2016) 1088–1091. [20] Dina H. Triyoso, Greg Spencer, Rama I. Hegde, Rich Gregory, Xiang-Dong Wang, Appl. Phys. Lett. 92 (2008) 113501. [21] Roman Engel-Herbert, Yoontae Hwang, Susanne Stemmer, J. Appl. Phys. 108 (2010) 124101.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Research paper
Enhanced electrical characteristics of FinFET by rapid-thermal-and-laser annealing with suitable power Dun-Bao Ruan, Kuei-Shu Chang-Liao ⁎, Yan-Lin Li, Hao-Ting Feng, Yi-Wen Hsu, Chin-Hsiu Huang, Shang-Fu Tsai, Meng-Ying Yang Department of Engineering and System Science, National Tsing Hua University, Hsinchu 30013, Taiwan ROC
a r t i c l e
i n f o
Article history: Received 20 February 2017 Received in revised form 7 April 2017 Accepted 27 April 2017 Available online 03 May 2017 Keywords: FinFET Microwave annealing Rapid thermal annealing Laser annealing
a b s t r a c t In order to improve electrical characteristics of FinFETs, various annealing treatments for dopant activation were studied in this work. The treatments including rapid thermal annealing (RTA), microwave annealing, and RTAand-laser annealing with different powers were investigated. The on-current and carrier mobility of FinFET are significantly improved by a RTA-and-laser annealing with suitable power; meanwhile, the leakage current, interface characteristics and device reliability can be simultaneously maintained. The improvement can be attributed to the high thermal activation energy, less dopant diffusion, and enhanced quality of interfacial layer during the gate first processes. Therefore, a RTA-and-laser annealing with suitable power is promising for manufacturing high performance FinFET. © 2017 Elsevier B.V. All rights reserved.
1. Introduction With continuously scaling down the dimension of CMOS devices, the random dopant fluctuation effects that may induce a higher off-state leakage current, uniformity variation, and reliability degradation, are becoming important issues for manufacturing advanced FinFETs [1–6]. To suppress these effects, many annealing treatments for dopant activation were reported recently [7]. A rapid thermal annealing (RTA) was widely used in the industry, but the dopant fluctuation of device with 20-nm gate length and annealed by RTA is not small enough [8]. A microwave annealing process at low temperature, which can restrain the dopant diffusion by a lower thermal activation energy, was implemented to replace the traditional method in recent reports [9–13]. However, the unexpected degradation on electrical performance was observed, which is caused by its insufficient dopant activation. In addition, laser annealing treatments were proposed to achieve better dopant activation, and a shallow junction can also be obtained with some optimal conditions [14–19]. It was reported that a laser annealing with fast ramp down of temperature can significantly reduce the gate leakage current, enhance the dielectric constant (k value), and improve the quality of interfacial layer (IL) in gate first CMOS processes [20]. In this work, FinFET devices were fabricated on silicon-on-insulator (SOI) wafer by gate first processes to investigate the effects of different annealing treatments. RTA, microwave, RTA-and-laser annealing treatments were performed after the conventional ion implantation for the ⁎ Corresponding author. E-mail address: [email protected] (K.-S. Chang-Liao).
http://dx.doi.org/10.1016/j.mee.2017.04.037 0167-9317/© 2017 Elsevier B.V. All rights reserved.
activation of source and drain (S/D). The on/off-current, carrier mobility, gate leakage current, interface traps density (Dit), equivalent oxide thickness at inversion (Tinv), and reliability characteristics of FinFETs were investigated and compared. 2. Experiment The FinFET devices were fabricated on 6-inch p-type SOI (100) wafers by gate first processes. The patterns of dummy fins were defined by I-line lithography. Reactive ion etching (RIE) process was performed to form four parallel fins with a fin height of 40 nm. Then, a 3-nm thick HfO2 was deposited by atomic layer deposition (ALD). Afterward, a 100-nm thick TiN film was deposited by a sputtering to serve as metal gate. After patterning gate stack, phosphorous implantation (at 40 keV with a dose of 5 × 1015 cm−2) was performed. Subsequently, annealing treatments with microwave, RTA, and RTA + laser were applied on different samples. A microwave process was performed at a peak temperature of 400 °C with a power of 300 W for 300 s. The peak temperature was detected by a light pipe and the frequency of the microwave annealing is 5.8 GHz. Control sample was treated with a RTA at 750 °C for 30 s. Some of control samples were treated with additional laser annealing at powers of 2.5 W and 1.5 W, respectively, namely, RTA-and-laser samples. The wavelength, pulse width, and scanning speed of laser source with HIPPO 532QW Nd:YAG are 532 nm, 13 ns, and 25 cm/s, respectively. The sample splits in this work are shown in Table 1. Passivation and metallization processes were performed, followed by a sintering at 400 °C for 30 min to complete device fabrication. The cross-sectional view and detailed process flow of SOI FinFET are shown in Fig. 1.
D.-B. Ruan et al. / Microelectronic Engineering 178 (2017) 56–60
57
Table 1 Sample splits of SOI FinFET in this work.
Sample
Control
2.5 W
Activation
RTA 750 30 s
Laser 2.5 W Laser 1.5 W RTA 750 RTA 750 TiN 100 nm
Metal gate
Microwave MW = 400 300W 300 s
HfO2 3 nm
High-k Channel material Substrate
1.5 W Al-Si-Cu
Contact
Singlec-Si
Hfin = 40 nm Wfin = 20 nm SOI
3. Results and discussion Fig. 2 shows cross-sectional transmission electron microscope (TEM) image of FinFET with TiN/HfO2/Si gate stack. A fin structure is clearly observed, and it is covered with partially crystallized high-k dielectric. The height and width of Si fin are 40 nm and 20 nm, respectively. An IL formed by a H2O2 solution exists between high-k dielectric and Si fin structure, and its thickness is below 0.5 nm. This IL would play an important role on EOT scaling and suppress the influence of interface traps on electrical characteristics of FinFETs. Fig. 3 shows drain current versus gate voltage (ID-VG) of FinFETs with various annealing treatments. The on-currents of samples with RTA-and-laser treatments are about 8 × 10− 5 A/μm, and are much higher than that with other treatments. It can be attributed to the higher dopant activation energy received by the S/D regions. Specially, sample with a RTA-and-laser at a power of 1.5 W shows a lower off-current, which achieves an on/off current ratio of 8 × 106 and a sub-threshold swing (S.S.) of 67 mV/dec. Sample with a RTA-and-laser at a power of 2.5 W shows a larger off-current, which may be due to more dopant diffusion or damage in gate dielectric caused by a laser treatment with a higher power. Sample with a microwave annealing shows a lower offcurrent, but its on-current is clearly degraded, suggesting that the dopant activation in S/D region by using a microwave annealing is not enough. Fig. 4 shows current-voltage (J-V) curves of P/N junctions in FinFETs with various annealing treatments. The junction characteristics of sample with a RTA-and-laser treatment at a power of 1.5 W are better than those of control one. The dopant activation in S/D regions by using a microwave annealing is not enough although a lower reverse current is obtained. The reverse current of sample with a RTA-and-laser treatment at
Fig. 2. Cross-sectional transmission electron microscope (TEM) image of FinFET with TiN/ HfO2/Si gate stack.
a higher power is larger, which may be due to more dopant diffusion during its thermal process. Fig. 5 shows trans-conductance (GM) versus gate voltage (GM-VG) of FinFETs with various annealing treatments. The peak GM value of sample with a RTA-and-laser treatment is much higher than that of control one. The VG values of peak GM for all samples are different, which may be attributed to the changes of physical thickness and k-value of ILs during the gate first processes. Fig. 6 shows electron mobility versus inversion charge density (μ eff -Ninv) of FinFETs with various annealing treatments. Inset figure shows the schematic mechanisms of carrier mobility degradation. The peak electron mobility of FinFET with RTA-and-laser at a power of 1.5 W is about 210 cm2/V-s, which can be due to better activation of S/ D dopant. Besides, with increasing the inversion charge density, the electron mobility values of samples with RTA-and-laser treatments decrease much more slightly than those with other treatments, suggesting that the surface roughness can be reduced with RTA-and-laser treatments. Fig. 7 shows gate leakage current versus gate voltage (JG-VG) curves for FinFETs with various annealing treatments. The leakage current of
Fig. 1. Cross-sectional view and schematic process flow of SOI FinFET in this work.
58
D.-B. Ruan et al. / Microelectronic Engineering 178 (2017) 56–60
Fig. 3. Drain current versus Gate voltage (ID-VG) of FinFETs with various annealing treatments.
Fig. 6. Electron mobility versus inversion charge density (μeff-Ninv) of FinFETs with various annealing treatments. Inset figure shows the schematic mechanisms of carrier mobility degradation.
values, which may be due to its less thermal treatment during the S/D dopant activation in the gate first processes. The sample with RTA-and-laser at a power of 1.5 W shows clear reduction in the gate leakage and slightly smaller Tinv value as compared to control one. The results are consistent with those presented in Fig. 3. Fig. 9 shows interface trap density (Dit) for FinFETs with various annealing treatments. The Dit values were extracted by conductance method using MOS capacitors with the same gate stacks and annealing treatments as FinFETs. With the conductance model, the Dit value can be approximately extracted from (1): [21] Dit ≈
2:5 Gp q ω max
ð1Þ
sample with a microwave annealing is the lowest owing to the fewer traps in its gate dielectric treated by less thermal energy. In comparison with the control one, the gate leakage current can be suppressed by RTA-and-laser treatments. Results indicate that the quality of IL can be improved and dopant diffusion is limited by an annealing with fast ramp down of temperature. Hence, an optimal power condition for a laser annealing is required in the gate first processes. Fig. 8 shows gate leakage current density versus EOT at inversion (JG-Tinv) for FinFETs with various annealing treatments. Sample with a microwave annealing shows the lowest leakage current and Tinv
The GP and ω are equivalent parallel conductance density and angular frequency, respectively. The Dit value of sample with a microwave annealing is the smallest due to fewer damages caused by less thermal energy. Samples with RTA-and-laser treatments show similar Dit values as compared to the control one. Fig. 10 shows threshold voltage shift (Vth-shift) versus F-N stress time (E = 9 MV/cm) for FinFETs with various annealing treatments. The Vth-shift values after 1000 s for sample with a microwave annealing are the smallest owing to fewer oxide traps in high-k dielectric. The V th-shift of sample with RTA-and-laser at a power of 1.5 W is smaller than that of control one, while reliability degradation is serious for sample with RTA-and-laser at a power of 2.5 W. It suggests that the oxide traps are increased after a laser annealing with a higher power. In other words, an optimal power condition of laser annealing is very important for the gate first processes.
Fig. 5. Trans-conductance (GM) versus Gate voltage (GM-VG) of FinFETs with various annealing treatments.
Fig. 7. Gate leakage current versus Gate voltage (JG-VG) curve for FinFETs with various annealing treatments.
Fig. 4. Current-voltage (J-V) curves of P/N junctions in FinFETs with various annealing treatments.
D.-B. Ruan et al. / Microelectronic Engineering 178 (2017) 56–60
Fig. 8. Gate leakage current density versus equivalent oxide thickness at inversion (JG-Tinv) for FinFETs with various annealing treatments.
59
Fig. 11. The degradation of maximum trans-conductance (Gm, max) versus F-N stress time (E = 9 MV/cm) for FinFETs with various annealing treatments.
4. Conclusions Electrical characteristics of FinFETs with various annealing treatments were investigated in this work. FinFET with a RTA-and-laser treatment at suitable conditions shows significant improvement on electrical characteristics, such as on/off current ratio of 8 × 106, S.S. of 67 mV/dec, higher electron mobility, lower gate leakage current, and good reliability, which may be attributed to the better dopant activation and less damage on high-k gate dielectrics. Since a microwave annealing is helpful to obtain low Dit and Tinv, its combination with a laser annealing may provide another way to achieve high performance FinFETs.
Acknowledgment Fig. 9. Interface trap density (Dit) for FinFETs with various annealing treatments.
Fig. 11 shows degradation of maximum trans-conductance (Gm, max) versus F-N stress time (E = 9 MV/cm) for FinFETs with various annealing treatments. The Gm, max degradation values of sample with a microwave annealing are the smallest due to fewer interface traps at gate dielectric/channel. The Gm, max degradation for sample with RTA-andlaser at a power of 1.5 W is only 6%. However, the Gm, max degradation of sample with RTA-and-laser at a power of 2.5 W is 16%, which may be attributed to more interface traps generated by higher thermal energy.
Fig. 10. The threshold voltage shift (Vth shift) versus F-N stress time (E = 9 MV/cm) for FinFETs with various annealing treatments.
The authors would like to thank the Ministry of Science and Technology of Taiwan (MOST 105-2221-E-007 -108 -MY3), the Republic of China (R.O.C.) for financial support. The technical supports from National Nano Device Laboratories (NDL), Taiwan, R.O.C. are also acknowledged. References [1] Changho Shin, Jeong-Kyu Kim, Gwang-Sik Kim, Hyunjae Lee, Changhwan Shin, Jong-Kook Kim, Byung Jin Cho, Hyun-Yong Yu, IEEE Trans. Electron Devices 63 (2016) 4167–4172. [2] Yiming Li, Han-Tung Chang, Chun-Ning Lai, Pei-Jung Chao, Chieh-Yang Chen, IEDM Tech. (2015) 34.4.1–34.4.4. [3] Nauman Z. Butt, Jeffrey B. Johnson, IEEE Electron Device Lett. 33 (2012) 1099–1101. [4] Greg Leung, Chi On Chui, IEEE Electron Device Lett. 33 (2012) 767–769. [5] Nobuyuki Sugii, Ryuta Tsuchiya, Takashi Ishigaki, Yusuke Morita, Hiroyuki Yoshimoto, Shin'ichiro Kimura, IEEE Trans. Electron Devices 57 (2010) 835–845. [6] Yiming Li, Chih-Hong Hwang, Tien-Yeh Li, Ming-Hung Han, IEEE Trans. Electron Devices 57 (2010) 437–447. [7] Shinichi Kato, Takayuki Aoyama, Takashi Onizawa, Kazuto Ikeda, Yuzuru Ohji, VLSI Symp. Tech. (2010) 71–72. [8] S. Shimizu, T. Kuroi, Y. Kawasaki, T. Tsutsumi, H. Oda, M. Inuishi, H. Miyoshi, VLSI Symp. Tech. (1996) 64–65. [9] Rui Zhang, Junkang Li, Feng Chen, Yi Zhao, IEEE Trans. Electron Devices 7 (2016) 2665–2670. [10] Hsin-Hui Hu, Kai-Min Wang, IEEE Trans. Electron Devices 62 (2015) 2883–2887. [11] Fu-Kuo Hsueh, Yao-Jen Lee, Kun-Lin Lin, Michael I. Current, Ching-Yi Wu, TienSheng Chao, IEEE Trans. Electron Devices 58 (2011) 2088–2093. [12] Yao-Jen Lee, Ta-Chun Cho, Shang-Shiun Chuang, Fu-Kuo Hsueh, Yu-Lun Lu, Po-Jung Sung, Hsiu-Chih Chen, Michael I. Current, Tseung-Yuen Tseng, Tien-Sheng Chao, Chenming Hu, Fu-Liang Yang, IEEE Trans. Electron Devices 61 (2014) 651–665. [13] Yao-Jen Lee, Shang-Shiun Chuang, Fu-Kuo Hsueh, Ho-Ming Lin, Shich-Chuang Wu, Ching-Yi Wu, Tseung-Yuen Tseng, IEEE Electron Device Lett. 32 (2011) 194–196. [14] I-Hsieh Wong, Fang-Liang Lu, Shih-Hsien Huang, Hung-Yu Ye, Chun-Ti Lu, Jhih-Yang Yan, Yu-Cheng Shen, Yu-Jiun Peng, Huang-Siang Lan, C.W. Liu, IEDM Tech. (2016) 33.6.1–33.6.4. [15] Q. Zhang, J. Huang, N. Wu, G. Chen, M. Hong, L.K. Bera, C. Zhu, IEEE Electron Device Lett. 27 (2006) 728–730. [16] C. Fenouillet-Beranger, B. Mathieu, B. Previtali, M.-P. Samson, N. Rambal, V. Benevent, S. Kerdiles, J.-P. Barnes, D. Barge, P. Besson, R. Kachtouli, M. Cassé, X. Garros, A. Laurent, F. Nemouchi, K. Huet, I. Toqué-Trésonne, D. Lafond, H. Dansas, F. Aussenac, G. Druais, P. Perreau, E. Richard, S. Chhun, E. Petitprez, N. Guillot, F.
60
D.-B. Ruan et al. / Microelectronic Engineering 178 (2017) 56–60
Deprat, L. Pasini, L. Brunet, V. Lu, C. Reita, P. Batude, M. Vinet, IEDM Tech. (2014) 27.5.1–27.5.4. [17] William Hsu, Feng Wen, Xiaoru Wang, Yun Wang, Andrei Dolocan, Anupam Roy, Taegon Kim, Emanuel Tutuc, Sanjay K. Banerjee, IEEE Trans. Electron Devices 64 (2017) 346–352. [18] William Hsu, Taegon Kim, Alfredo Benítez-Lara, Harry Chou, Andrei Dolocan, Amritesh Rai, M. Josefina, Arellano-Jiménez, Marylene Palard, Miguel JoséYacamán, Sanjay K. Banerjee, J. Appl. Phys. 120 (2016), 015701.
[19] William Hsu, Xiaoru Wang, Feng Wen, Yun Wang, Andrei Dolocan, Taegon Kim, Emanuel Tutuc, Sanjay K. Banerjee, IEEE Electron Device Lett. 37 (2016) 1088–1091. [20] Dina H. Triyoso, Greg Spencer, Rama I. Hegde, Rich Gregory, Xiang-Dong Wang, Appl. Phys. Lett. 92 (2008) 113501. [21] Roman Engel-Herbert, Yoontae Hwang, Susanne Stemmer, J. Appl. Phys. 108 (2010) 124101.