Epi Wafers

6

Chapter Six

Epi Wafers: Preparation and Properties Douglas J. Meyer AZonic Solar, Mesa, AZ, USA

The epitaxial deposition of Si, often referred to as epi, is an essential step in the formation of many MEMS structures. Epi is used as etch stops for forming BESOI (bonded etch-back silicon on insulator) structures, on SIMOX SOI structures to increase the Si thickness above the buried oxide (BOX) and as a means for build­ ing a combination monocrystalline/polycrystalline struc­ ture referred to as epi-poly. Epi layers of up to 100 μm, or even more, are used in MEMS structures, although most applications require only 2–20 μm of epi. This brief treatise on epitaxy touches on the funda­ mentals of epitaxial deposition as well as some specific examples relevant to MEMS. A comprehensive discus­ sion of Si epitaxy can be found in the tome edited by Crippa et al. [1].

Load wafer(s) into the process chamber

Purge process chamber

Heat to H2 bake temperature

Perform H2 bake

Heat or cool to deposition temperature

Deposit the epi layer

Cool to wafer unload temperature

6.1 Silicon Epitaxy—The Basics Unload wafer(s)

Epitaxy was invented at AT&T Bell Labs [2] circa 1960 in order to improve doping profile abruptness and increase the operating frequencies of bipolar transis­ tors. Since then, the use of epitaxy has spread through­ out the semiconductor industry and can be found in nearly all fabrication disciplines. Although the details of epitaxial deposition recipes are often highly specific to the precise goals of the process, with respect to MEMS applications, the process can often be represented by Figure 6.1. Silicon substrates (wafers) are loaded into the proc­ ess chamber and the chamber is then purged with N2, if loading required exposure to air. Hydrogen is intro­ duced and the process chamber then remains in an H2 ambient throughout the entire process. The chamber is

Etch the process chamber

Fig 6.1 ● The basic epitaxy process recipe.

heated to a temperature sufficient for removing native oxide from the wafer surface as described in Section 6.1.1. Following native oxide removal, the chamber is then cooled, if necessary, to the desired temperature for deposition of the epitaxial layer. The choice of deposi­ tion temperature, pressure, silicon precursor and doping species are discussed in Sections 6.1.2, 6.1.3 and 6.1.4. After depositing the epi layer, the system is briefly purged in H2 to remove any residual Si and doping gas 89

Silicon as MEMS Material

species and then cooled to the appropriate tempera­ ture for unloading the processed substrates. After the substrates have been unloaded the chamber may be heated to 1200°C and etched with HCl (gas phase concentration of 50% HCl in H2 in the chamber) or the process chamber is loaded with a new set of wafers and another epi process run is begun. The frequency of process chamber etching is determined by the type of epi reactor (single wafer or batch), the build-up of dopant background in the chamber and the amount of Si accumulated in the process chamber.

6.1.1 Surface Preparation The growth of epitaxial Si fundamentally requires that the deposition occur over a surface that has an atomic spacing very nearly equal to that of Si. The most com­ mon case of Si epitaxy is that of homoepitaxial growth, where Si epi is deposited on a Si substrate. Si sub­ strates are normally covered with a native oxide consist­ ing of 1–3 nm of SiO2 and this amorphous layer must first be removed to expose the Si surface. Removal is commonly accomplished by reduction in H2 at an ele­ vated temperature of 1100°C or more through the reactions: SiO2(s) H2 (v)  SiO(v) H2O(v)

(6.1)

SiO2(s) Si(s)  2SiO(v)

(6.2)

and

Equation 6.1 is the dominant process for native oxide removal at low temperatures with Eq. 6.2 becoming important at higher temperatures. This process step is referred to as the hydrogen bake. The presence of H2O in Eq. 6.1 suggests that the H2 bake step is sensitive to the water vapor content of the H2 used in the proc­ ess. This is indeed highly significant and H2O contents of 1 ppm, and preferably 100 ppb, are essential for high quality, stacking fault-free epitaxial processing. Figure 6.2 demonstrates the impact of temperature on the SiO2 reduction rate with a H2 source containing 10 ppb of H2O. Some epitaxial processes have severe thermal budget limitations due to the presence of other structures on the wafer prior to epi. In these cases the native oxide can be removed by liquid phase etching with a dilute HF solution, typically 100:1 deionized water to reagent HF by volume, for a duration of 2–5 minutes at room temperature. Native oxide removal proceeds via the reaction: SiO2(s) 6HF(l)  H2(v) + SiF6 (l) 2H2O(l) 90

(6.3)

10

SiO2 etch rate (nm/min)

PA R T I

1

0.1

1200°C 1100°C 1000°C

0.01 0.6

0.7

900°C

0.8

0.9

1000/T (K–1)

Fig 6.2 ● SiO2 etch rate in H2 at 100 kPa.

Rinsing the wafers in ultrapure deionized water (total ionized C content 5 ppb, dissolved O content 50 ppb) after the etch will result in a hydrogen ter­ minated surface that resists oxidation for several hours in ambient conditions. This allows transportation of the etched wafers to an inert gas purged or vacuum loadlock for staging prior to epitaxial processing. The ex-situ removal of the native oxide enables the hydrogen bake to be performed at a temperature of 850°C or so for 5 minutes and yields an O-free epi/substrate interface. Failure to remove the native oxide prior to deposition will result in amorphous or polycrystalline film growth, depending on the temperature of deposition. If a chlorosi­ lane is used as the Si precursor, the film deposited over the native oxide will most likely be discontinuous, or at sufficiently low temperatures, no growth will occur at all.

6.1.2 Silicon Precursors and Deposition Temperature The choice of a Si precursor and the deposition temper­ ature are strongly related to the dopants and structure present on the wafer prior to epitaxy. An Arrhenius plot of the commercially available Si precursors most often used for Si epitaxy is shown in Figure 6.3. The deposition of Si from chlorosilanes can be described by the overall reaction as in SiH(4n )C l n ( v ) (n  2)H2(v)  Si(s) nHCl(v) n  2, 3 or 4

(6.4)

Epi Wafers: Preparation and Properties

and for non-chlorinated silanes as Si m H2(m 1)(v)  Si(s) (m 1)H2 (v) m  1, 2 or 3 (6.5)

Precursors such as Si2H6 and Si3H8 are extremely expensive compared to SiH4 and the chlorosilanes. Thus, their application is reserved for processes requir­ ing very thin epitaxy at low deposition temperatures, for example, T600°C. Fortunately, MEMS applications do not normally require such low epi process temper­ atures, thereby enabling the use of less expensive pre­ cursors which have higher deposition rates and higher productivity. Further, the use of SiCl4, which was quite common in the 1970s and 1980s, has been curtailed sig­ nificantly in recent times since it provides no deposition rate advantage over SiHCl3 [3]. In general, it is desirable to choose the Si precursor which provides the highest deposition rate, at the cho­ sen deposition temperature, in order to maximize pro­ ductivity. If there are no temperature restrictions on the

10 Deposition rate (μm/min)

SiHCl3 SiH2Cl2

1 SiCl4 0.1

SiH4 Si2H6

0.01

Si3H8

0.001 1200°C1000°C 800°C 700°C 0.0001 0.65 0.85 1.05

600°C 1.25

1000/K (K–1)

Fig 6.3 ● Arrhenius plot for inorganic Si precursors.

CHAPTER 6

process, SiHCl3 is the obvious choice. Coincidentally, it is also the lowest cost Si precursor for epi. There is, however, a practical limitation to this rule. All commer­ cial epi reactors rotate the wafer support, referred to as a susceptor, in order to achieve acceptable film uni­ formities by a superposition of the deposition profiles at various locations within the process chamber. Although there is no hard and fast rule, it is usually desirable to allow the susceptor to make at least 10 revolutions dur­ ing the deposition step. Thus a single wafer epi reac­ tor, with a rotation rate of 30 rpm, would suggest a minimum deposition time of around 20 seconds. At a growth rate of 4 μm/min a minimum epi thickness of about 1.5 μm is needed to achieve good film uniformity with this precursor. The special case of epi-poly, where both monocrys­ talline and polycrystalline Si are to be deposited on a wafer, is discussed in greater detail in Section 6.2. Briefly, SiH4 must be used, at least initially, in order to achieve a continuous film over the dielectric regions. Epi layers having a thickness  1 μm often use a chlo­ rosilane (SiHCl3 or SiH2Cl2) following an initial growth with SiH4. The use of SiH2Cl2 as a precursor is usually limited to films 2 μm in thickness. Such films are common in bipolar and BiCMOS structures where reduced pressure (RP) processing is often required to control As autodop­ ing, or for selective epitaxy as described in Section 6.5. A comparison of the applicability of the various Si pre­ cursors is provided in Table 6.1. The choice of deposition temperature is usually imposed upon the epi process by structures (physical and/or doping) which are on the wafer prior to epi. The diffusion of dopants, particularly B and P, in the substrate may place a constraint on the upper temperature of the process. The choice of deposition temperature must then be made with respect to the overall process integra­ tion strategy. The presence of SiO2 on the wafer surface,

Table 6.1 Comparison of common precursors for Si epitaxy

Thickness range (μm)

Deposition temp. (°C)

Dep. rate range (mm/min)

Reduced press?

Selective epi?

SiGe epi?

Chamber coating

SiCl4

2–100

1150–1250

0.5–2

No

Rare

No

Lowest

SiHCl3

2–100

1050–1200

0.5–5

Rare

No

Rare

Low

SiH2Cl2

0.001–5

650–1100

0.001–2

Yes

Yes

Yes

Moderate

SiH4

0.001–2

500–1000

0.001–1

Yes

Yes

Yes

Significant

Si2H6

0.001–0.5

400–800

0.001–0.2

Yes

Yes

Yes

Significant

Si3H8

0.001–0.5

400–600

0.001–0.2

Yes

Yes

Yes

Significant

91

PA R T I

Silicon as MEMS Material

typically found in selective epi processes or the epi-poly process, may put a constraint on the maximum H2 bake temperature, as discussed in Sections 6.2 and 6.5.

6.1.3 Choice of Doping Species

deposition. Finally, the substrate surface crystal orienta­ tion may also motivate the pressure of deposition. The growth of epitaxy over a substrate contain­ ing only B as the dopant species is best performed at atmospheric pressure (AP). Figure 6.4 shows the transi­ tion region for p-type epi deposited on a p (heavily B doped) substrate. The impact of temperature on the transition region for p epi on a p substrate is demonstrated in Figure 6.5. As the temperature increases, the vapor pressure of B, due to out-gassing from the substrate, also increases

B concentration (atoms/cm3)

Epitaxial layers are doped in-situ during the growth of the layer. The dopants used for epi are usually As or P, for n-type epi layers, and B for p-type epi. The gas phase species for these dopants are AsH3, PH3, B2H6 or, much less commonly, BCl3. The hydride doping spe­ cies are typically purchased in high pressure gas cylin­ ders containing 10–100 ppm of the hydride in H2. If 1020 T = 1100C exceptionally high concentrations of doping are neces­ P = 760 torr 19 sary in the epi layer these dopants can be purchased 10 SiHCl3= 12 g/min as pure components. However, concentrations in the Dep. rate = 4 μm/min range of 1–10% diluted with H2 or an inert gas are more 1018 common. The use of Sb as an n-type dopant in Si epi is excep­ 1017 tionally rare due to the poor stability (shelf life) of SbH3 and low vapor pressure of SbCl5. If BCl3 or 1016 SbCl5 is used as the doping source, a liquid-vapor deliv­ ery system (often referred to as a bubbler) is required 1015 Transition width ~ 0.35 μm where H2 or an inert carrier gas is passed through the pure component liquid and the resulting mixture of the 1014 dopant in H2 is delivered to the process chamber. The incorporation of n-type and p-type dopants as 1013 a function of temperature can be summarized as fol­ 0 1 2 3 lows: Under the conditions of fixed deposition rate,

Depth (μm) fixed pressure and fixed doping species partial pres­ Fig 6.4 ● Transition region for p-epi on a p substrate.

sure, n-type doping incorporation decreases (resistivity increases) with increasing temperature while p-type

doping incorporation increases (resistivity decreases)

6 0.5 with increasing temperature. Increasing the deposition

Overall rate, at fixed temperature and pressure, will result in a

Trans. Width decrease of n-type or p-type doping incorporation at a

5 fixed partial pressure of the doping species. 0.4 The choice of doping species is almost always deter­ mined by the type of epi layer (p-type epi requires B)

4 and diffusion caused by subsequent processing of the

0.3 wafer (P diffuses faster than As). Thus, the epi engineer

rarely has any freedom of choice with regard to doping

3 species selection.

The choice of process pressure is most often based on structures present on or in the substrate. Control of autodoping, where dopants in the substrate impact the doping of the epi layer during the initial growth stages, is the primary motivator for process pressure choice. There are, however, two situations in MEMS where the nature of the epi deposition process motivates the choice of process pressure: selective epitaxy and epi-poly 92

3

Cl

2

Deposition rate (μm/min)

dep osi ti

on ra

te

T.W .a

0.2

SiH

6.1.4 Choosing an Operating Pressure

Transition width (μm)

t ra

te =

1μ

m/

mi

n

4

0.1

0 900

1

1000

1100

0 1200

Temperature (°C)

Fig 6.5 Transition width temperature dependence for p-epi on a p substrate. ●

Epi Wafers: Preparation and Properties

providing more available B for incorporation into the growing epitaxial layer and thereby increasing the transition width. As the deposition rate increases, the transition width is reduced due to the surface of the substrate rapidly becoming covered by the epi layer. Based on Figures 6.3 and 6.5, it can be seen that the deposition rate decreases, in the surface reaction rate limited region of the Arrhenius plot as the tempera­ ture decreases. The combination of B out-gassing and the change of deposition rate yields the resulting graph of transition width vs. temperature, as shown in Figure 6.5. The issue of B autodoping is critical to the success­ ful growth of high resistivity p-type epi layers over heav­ ily doped p-type regions such as etch stops discussed in Section 6.3.1. The issue with n-type dopants is more complex. Figure 6.6 compares AP processing with RP (reduced pressure) processing for n-epi deposited over a substrate with n As buried layers. The impact on vertical transition region and lat­ eral autodoping is clearly demonstrated. This effect is explained by the fact that the gas phase diffusion coef­ ficient of the As, which out-gasses from the substrate, increases with decreasing pressure, thus providing a means for the As to diffuse away from the wafer sur­ face, thereby reducing the opportunity for incorpora­ tion into the epi layer. Thus, operating at RP (P 100 torr) during epi growth over substrates heavily doped with As, either as a buried layer or as the dopant in the substrate itself, is extremely valuable in controlling As autodoping.

1021 Epi

Substrate

1019 AP

1018

When P or B is used as a dopant in the substrate or buried layer, pressure has very little impact on autodop­ ing. This is due to the rapid solid phase diffusion coef­ ficients of P and B, compared to that of As, which allow the surface to be replenished with P or B as they out­ gas from the substrate. In theory, Sb should behave similarly to As with respect to autodoping. However, due to the very low vapor pressure of Sb, the effect of pressure on transi­ tion region and lateral autodoping cannot be observed by spreading resistance analysis. The use of SIMS (sec­ ondary ion mass spectrometry) on very thin layers of undoped Si deposited over Sb buried layers does indeed confirm that Sb and As behave similarly [3]. However, the impact of RP on Sb autodoping is only significant for layers having thicknesses of 100 nm or so and is, therefore, not of interest for most MEMS applications. There exists a phenomenon known as pattern shift [1], which will cause a buried layer structure to appear at a different position on top of the epi layer than its actual location in the substrate. A diagram of this phe­ nomenon is provided in Figure 6.7 along with a graph depicting the impact of pressure on pattern shift for a substrate having a (111) surface orientation. This effect is caused by anisotropic etching and growth when a chlorosilane is used as the Si precursor. Substrates which have a surface orientation of (100) do not suffer from pattern shift due to the symmetry of the atomic structure. It should be noted that (100)-oriented sub­ strates may be cut off-orientation, usually in the direction of the (110) crystal plane. A small off-orientation of 1° or so will not result in a significant amount of pattern shift. Larger amounts of off-orientation, say 10° or more, will result in a very observable pattern shift and may motivate the use of RP processing. Selective epitaxy is usually processed at RP (10–100

torr) in order to mitigate loading effects. Selective epi­ taxy is discussed in greater detail in Section 6.5. The epi-poly process, which is often used in MEMS structures, may need to operate at RP in order to adjust the relative thickness of the monocrystalline and

2

1017 RP

Pattern shift ratio

Doping concentration (atoms/cm3)

1020

1016 1015

1014

0

1

2 Depth (μm)

Fig 6.6 ● Vertical and lateral autodoping over an n As buried layer.

3

CHAPTER 6

1.5 1

Buried layer

Apparent position of b.l. after epi epi

SiHCl3

Si substrate

SiH2Cl2

0.5 0 –0.5 10

100

1000

Pressure (torr)

Fig 6.7 ● Pattern shift on a (111)-oriented substrate using chlorosilane Si precursors for epi.

93

Silicon as MEMS Material

The epi-poly process is used to deposit both mono­ crystalline and polycrystalline Si films on the wafer. Epi (monocrystalline Si) will grow over the exposed Si regions while polysilicon will grow over a dielectric region (either SiO2 or Si3N4), as shown in Figure 6.8. In this application a chlorosilane cannot be used for deposition since the Cl atoms in the gas phase will result in discontinuous growth over the dielectric regions [4]. Thus, SiH4 is most often used as the Si precursor for thin (e.g., 2 μm) films. The use of SiH4 for depositing thicker films will often result in unacceptable coating of the fused silica process chamber enclosure. In order to deposit films 2 μm in total thickness, an initial thin layer of Si (e.g., 0.5 μm or so) is grown from SiH4. The growth is then interrupted and the precursor is switched to chlorosilanes such as SiHCl3. This strategy allows much thicker layers of Si to be deposited with­ out excessive chamber coating and greatly improves the overall productivity of the process. The switch from one Si precursor to another occurs within the process recipe requiring less than one minute to affect this change. It is also possible to deposit a thin poly-Si or α­ Si layer over the dielectric in a low pressure chemical vapor deposition (LPCVD) furnace prior to depositing the epi-poly layer. A photolithography step and etch step to expose the monocrystalline Si region which will receive epitaxial growth must then follow this LPCVD process prior to epi. Using this strategy enables a chlo­ rosilane to be used throughout the entire epi-poly depo­ sition process, since exposed dielectric regions will not be present on the substrate surface. The presence of dielectric structures on the substrate surface may impose a constraint on H2 bake tempera­ ture, as discussed for selective epitaxy in Section 6.5. Further, if a certain grain size is required for the depos­ ited polysilicon region, a specific temperature will be necessary to achieve that grain size [4]. The impact of deposition temperature on as-deposited, undoped polysilicon grain size, is shown in Figure 6.9 for a total film thickness of 200–300 nm.

250

200

150

100

Amorphous

6.2 The Epi-Poly Process

Due to the different crystalline structures of epi­ taxy and polysilicon, these two layers will often grow at different rates. At low temperatures (T800°C) it has been observed during Si and SiGe epitaxy that epi grows faster than polysilicon at AP [5]. As shown in Figure 6.10, pressure can be used to control this dif­ ference in order to achieve a polysilicon region thicker than the epi region or vice versa.

Poly-Si grain size (nm)

polycrystalline regions. The epi-poly process is discussed in greater detail in Section 6.2.

50

0 500

700

900

1100

Temperature (°C)

Fig 6.9 ● As deposited poly-Si grain size from SiH4 at AP.

1.5 Si Deposited from SiH4 at 700°C

Si Poly:Epi growth rate ratio

PA R T I

1.0

0.5 0

20

40

60

80

100

Pressure (torr)

Fig 6.8 Deposition of Si on a substrate with oxidized regions resulting in the epi-poly structure. ●

94

Fig 6.10 The impact of process pressure on the poly-Si:epi-Si growth rate ratio. ●

Epi Wafers: Preparation and Properties

6.3 Etch Stop Layers

There are two epi layer structures that are used as etch stops in MEMS applications. The most common method is the use of a very heavily B doped epi layer, as described in Section 6.3.1. A second method using pseudomorphic SiGe is described in Section 6.3.2. The choice of etch stop is dictated by the liquid phase chemistry to be used in the etch process.

6.3.1 Heavily Boron Doped Epitaxial Etch Stop Layers Extremely heavily B doped epitaxy, referred to as p

epi, is often used as an etch stop layer when KOH is used in a liquid phase etching solution [6]. An etch selectivity of 1000:1 is observed for Si doped with B at 1019 cm3 compared to a doping concentration of 1020 cm3, with the higher etch rate observed for the lower doped material [6]. Achieving such high doping concentrations is no small task. Although the solid solubility of B is approximately 1  1020 cm3 at 900°C increasing to 4  1020 cm3 at 1200°C [7] there are several issues which compli­ cate the process. Very high partial pressures of B2H6 are necessary in the process chamber in order to dope the epi layer to such high levels. Thus, a gas phase doping source of 1–10% B2H6 in H2 is commonly used. Safety concerns are paramount when using such a high concen­ tration source, since the TLV for B2H6 is 0.1ppm and the LC50 is 80°ppm/h [8] (cf. the TLV of BCl3 is 1ppm while the LC50 is 2541ppm/h, [9]. The decomposition of high concentration doping sources often results in B being deposited on the fused silica process chamber walls and is observed as black lines. These deposits do not etch significantly in HCl, but will sublime if heated to very high temperatures (T  1200°C). Even so, it is not possible to clean the chamber adequately with an HCl etch or by sublima­ tion to allow high resistivity epi layers (ρ  50 Ω-cm) to be deposited with adequate control. Thus, the proc­ ess chamber used for p

etch stops is often dedicated to this heavily doped process and subsequent higher resistivity epi layers must be grown in a separate process chamber. Cleaning of the fused silica process chamber walls must be accomplished by an ex-situ liquid phase etch in an HF:HNO3 solution. The behavior of dopant incorporation with tempera­ ture, discussed in Section 6.1.3, suggests that a high deposition temperature and low deposition rate is ben­ eficial for incorporating high concentrations of B in Si. This is indeed the case for p

epitaxy etch stop dep­ osition. Thus, deposition temperatures of 1150°C or

CHAPTER 6

more with reduced flow rates of SiHCl3, to reduce the deposition rate, are used in these processes. Further, since incorporation of the dopant is roughly propor­ tional to the partial pressure in the gas phase, high total pressures of operation are desirable and, therefore, the process is carried out at AP. The B atom is very small compared to Si and, there­ fore, the large concentration of B in Si causes the p

epitaxial Si layer to have a smaller lattice constant than that of undoped or lightly B doped Si. As a result, a misfit dislocation matrix between the p

epi layer and the substrate beneath it will often be observed as shown in Figure 6.11 (Private comm. 2007, M. Tilli and V. M. Airaksinen). These line defects are present at the epi/substrate interface and may cause a corresponding surface rough­ ness on the top of the epi layer. The smaller lattice con­ stant of the epi layer on top of the substrate can also lead to bowing of the wafer. The misfit dislocation matrix and wafer bowing issues can be solved by counter doping the p

epi layer with Ge, which is a larger atom than that of Si. In theory, 5.6 atoms of Ge per atom of B are required in order to per­ fectly compensate for the effects of B [10]. Thus, a Ge atomic concentration of 2.2% is needed to compen­ sate for a B doping level of 2  1020 cm3.

6.3.2 Pseudomorphic Epitaxial SiGe Etch Stop Layers The use of pseudomorphic SiGe as an etch stop is typically driven by the need for very thin layers (e.g., 100 nm) after etching [11]. The KOH etch associated with p

etch stops is not sufficiently selective to allow etching to stop in time to achieve the desired

Fig 6.11 ● Misfit dislocation matrix with 10 μm of 1 mΩ-cm B doped Si Epi over a p- substrate [9].

95

Silicon as MEMS Material

PA R T I

the BOX of the as-implanted and annealed sub­ strate of 2 μm. Increasing this thickness to a total of 10 μm via epitaxial growth is a common requirement. Since the formation of a SIMOX substrate includes a 1250°C anneal, there are no fundamental temperature limitations to the epi process. Therefore, the SiHCl3 process outlined in Figure 6.1 is commonly used for this application.

layer thickness. Thus, other etch chemistries such as ethylene diamine pyrolcatechol can be used to achieve the desired post-etch layer thickness for BESOI struc­ tures [12]. Ge contents of 25–30% are required in order to achieve the needed etch selectivity for such structures. Strain in the SiGe layer is used to achieve etch selec­ tivity. The layer must be pseudomorphic and, therefore, very thin for high Ge content SiGe layers deposited on Si. Further, the deposition and all subsequent processes must be carried out at very low temperatures (e.g., T  700°C). The critical thickness for SiGe, calculated using the Matthews-Blakeslee methodology [13], is pre­ sented in Figure 6.12. The deposition of SiGe is usually performed at RP (100 torr). However, for substrates without dielectric features, it can be carried out at AP. Figure 6.13 demon­ strates the impact of Ge content of the film on deposi­ tion rate and activation energy. Figure 6.14 shows the incorporation behavior of Ge as functions of Ge partial pressure and temperature. A detailed discussion of SiGe deposition is provided in Chapter 10 of reference [1].

100

Deposition rate (nm/min)

Si from SiH4 Ea = 1.6 eV

Ge from GeH4 Ea= 0.2 eV 10

SiGe, Ea = 1.0 eV PSiH4:PGeH4= 20

6.4 Epi on SOI Substrates Epi is commonly used to increase the thickness of Si above a BOX in SOI wafers used for MEMS. SIMOX substrates, often used in sensor applications such as accelerometers [14], have a Si layer thickness over







800°C 700°C 600°C 1 0.9 1.0 1.1 1.2 1000/T

500°C 1.3

1.4

(K–1)

Fig 6.13 Arrhenius plot of Si and SiGe deposition. ●

200

30 625°C

Ge content of SiGe alloy (%)

Critical thickness (nm)

150

100

50

20

700°C

10

SiGe layer thickness limit

0

0 0

20

40

60

80

100

Ge content (%)

Fig 6.12 SiGe layer critical thickness for pseudomorphic structure. ●

96

0

2

4

6

GeH4 partial pressure (mtorr)

Fig 6.14 ● Ge content of SiGe alloy as functions of the deposition temperature and PGeH4.

Epi Wafers: Preparation and Properties

6.5 Selective Epitaxy and Epitaxial Layer Overgrowth Selective epitaxial growth (SEG), where deposition occurs only on exposed Si regions and not on dielectric materials, is achieved by creating a competition between etching and deposition. This is accomplished by using SiH2Cl2 and HCl together during the deposition proc­ ess. The ratio of HCl:SiH2Cl2 required to achieve selectivity is a function of the deposition temperature and the dielectric material present on the substrate. Figure 6.15 presents the HCl:SiH2Cl2 ratio for selec­ tive growth in the presence of SiO2. If Si3N4 is present on the substrate higher HCl:SiH2Cl2 ratios are required and the net deposition rate is reduced. Selective epitaxy is processed at RP to reduce the impact of micro-loading effects. Figure 6.16 demon­ strates the impact of pressure on the SEG deposition rate on features with sizes varying from 1 μm  1 μm to 500 μm  500 μm. The mechanism behind the micro-loading effect is simply one of mass transport via gas phase diffusion. Large exposed Si areas consume more Si precursor than small areas to achieve a given thickness. At high pres­ sure, the Si precursor becomes depleted while the HCl and Cl etching species are enhanced due to decompo­ sition of the chlorinated Si precursor. This happens to a greater extent over the larger exposed Si areas than smaller areas. Further, at high pressure, the additional etching species generated by decomposition of the Si precursor cannot diffuse away from the surface as quickly as at lower pressures. There is also an impact on SEG deposition rate due to macro-loading effects. The macro-loading effect is

2 Cl 2

50

1

rat io

De po sit

ion rat e

75

0.5

HC

25

HCl:SiH2Cl2 ratio

1.5

l:S iH

Deposition rate (nm/min)

100

0 700

750

800

850

0 900

Temperature (°C)

Fig 6.15 ● Deposition rate and HCl:SiH2Cl2 gas phase ratio for SEG in the presence of SiO2 dielectric.

Selective epi thickness (nm)

Other more complex epi processes, such as epi over Al2O3, which was itself hetero-epitaxially deposited over a Si substrate, can be used to build unique struc­ tures [15]. The growth of Si on Al2O3 requires the use of a non-chlorinated Si precursor, since the presence

of Cl will remove Al from the material matrix. Thus, SiH4, processed at AP and a deposition temperature of 900–1000°C, would be the recommended methodology for films 2 μm in thickness. If a substantially thicker Si epi layer is required, a chlorosilane can be used follow­ ing an initial deposition of 0.5 μm of Si from SiH4, as described in the epi-poly process in Section 6.2. It is convenient at this point to note that silicon on sapphire (SOS) is processed in the same manner, using r-plane Al2O3 substrates. Thus, the development of unique RF MEMS structures, which require high Q inductors in the device circuitry, are enabled through epitaxial technology on a sapphire substrate.

CHAPTER 6

100 90 80

760 torr

200 torr

70 100 torr 60

25 torr

50 1×1

5×5

10×10

100×100 500×500

Feature size (μm× μm)

Fig 6.16 ● Micro-loading effects during selective Si epitaxy 50.

caused by the amount of bare Si exposed on the sub­ strate surface relative to the fraction of the surface cov­ ered by dielectric. As an example, a substrate with 99% exposed Si will have a much lower overall SEG deposi­ tion rate than a substrate with only 1% exposed Si. Epitaxial layer overgrowth is a technique which exploits the characteristics of selective epitaxy and is shown diagrammatically in Figure 6.17. SEG Si grows only in the vertical direction until the first atomic layer appears above the dielectric. Once this occurs, Si grows both vertically and horizontally. As a result, the region at the center of the dielectric will be thinner than the regions adjacent to the exposed Si regions. The presence of SiO2 regions among single crys­ tal regions, essential for selective epitaxial structures, may place a constraint on the maximum H2 bake tem­ perature used for surface preparation. This is due to undercutting of the oxide, as described by Eqs 6.1 and 6.2, in Section 6.1.1 at temperatures 900°C. A dia­ gram of oxide undercutting is shown in Figure 6.18. 97

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Silicon as MEMS Material

Epi after growth

SiO2

Epi during growth

Si substrate

Fig 6.17 ● Epitaxial layer overgrowth during and after deposition.

Oxide undercutting from excessive H2 bake SiO2

Si substrate

Fig 6.18 ● Oxide undercutting of an SiO2 feature due to excessive hydrogen bake temperature.

It is important to recognize that even when Si3N4 regions are used as the dielectric on the substrate sur­ face, a “pad-oxide” of SiO2 lies beneath the Si3N4 and, therefore, undercutting may still occur.

6.6 Metrology A brief overview of metrology as it applies to epitaxial layers for measurements of thickness, resistivity and defect densities is provided in this section. For greater detail, please refer to Chapter 7 of reference [1] as well as Chapter 16 in Part III of this handbook.

6.6.1 Measurement of Si Epi Layer Thickness Epitaxial thickness measurements are most often per­ formed using the FTIR (Fourier Transform Infrared spectrometry) technique [16]. This method requires a structure where the epi layer has a relatively low doping concentration (Ndope  1018 cm3) and the region underlying the epi layer has a high doping concentration (Ndope  5  1018 cm3). The refractive index change of Si at high doping concentrations provides the reflec­ tion from the epi/substrate interface necessary for form­ ing the interferogram essential to this measurement. 98

Most epi layers grown over heavily n-type or p-type substrates meet the doping structural requirements for FTIR measurements of epi layer thickness. It is not necessary, however, that the entire substrate be heavily doped. Indeed, it is often possible to measure epi thick­ ness over a substrate which has discrete buried layer regions present, if the doping level and surface density of the buried layers is sufficient to appear like a con­ tinuous region to the beam of incident IR radiation, which is typically 1 mm in diameter for commercial applications. The FTIR technique is capable of measuring epi film thickness from 0.5 to over 100 μm. Exceptionally thin epi layers are often measured by spectroscopic ellip­ sometry [17] or SIMS [18]. Such techniques are rarely needed for MEMS applications, with the notable excep­ tion of SiGe, as discussed in Sections 6.3.2 and 6.6.3.

6.6.2 Measurement of Epi Layer Resistivity The measurement of resistivity, or doping concentra­ tion, in epitaxial layers is commonly performed using 4-point probe [19], capacitance-voltage (CV) [20], sur­ face potential [21] and spreading resistance profiling (SRP) [22]. In the extreme case of very thin films, SIMS [18] can be used. The 4-point probe measurement does not determine resistivity directly but instead measures the sheet resist­ ance of the layer with which it is in contact. In order to extract the resistivity of the epi layer, knowledge of the layer thickness is required. The resistivity is then calcu­ lated by ρ(Ω  cm)  104 × t epi × R s

(6.6)

where tepi is the epi layer thickness (μm) and Rs is the measured sheet resistance (Ω or Ω/square). Measurement of the epi layer sheet resistance requires that the underlying substrate be an insulator (e.g., SOI) or of the opposite resistivity type of that of the epi layer (p-type epi requires an n-type substrate and vice versa), where the p-n junction between the epi layer and the substrate electrically isolates the epi layer from the substrate. Often, a single epi layer thickness is used for calcu­ lating the on-wafer epi resistivity profile. However, in order to accurately determine the epi resistivity profile, the epi thickness at each point where the sheet resist­ ance is measured must be known. This creates a metrol­ ogy dilemma since epi thickness, measured by FTIR, must be measured over a heavily doped substrate, as discussed in Section 6.6.1. Further, the use of a heavily doped substrate of opposite type can result in grossly

Epi Wafers: Preparation and Properties

1. The epitaxial layer thickness required to achieve

a doping concentration change from 50% of the heavily doped substrate region to 2 times that of the epi layer. This method yields a 5 μm transition width in Figure 6.19. 2. The epitaxial layer thickness required to achieve

a doping concentration change of 3 orders of magnitude from the heavily doped substrate into the epi layer. This method results in a 2 μm transition width in Figure 6.19. 3. The epitaxial layer thickness required to achieve a

resistivity change from 2 times that of the heavily doped substrate region to 50% that of the epi layer. Note that this is not the same as technique 1 due to degenerate doping effects at high doping concentrations which lead to non-linearity in the doping concentration to resistivity relationship. This technique will result in a value slightly larger than that of method 1. SRP measurements are extremely useful since they can be performed directly on the product substrate. Precision of measurement is /–10% or so, and calibra­ tion to known standards is essential. The CV technique often uses a mercury (Hg) dot for formation of a Schottkey contact. This technique can be performed on either p or n-type epi layers, however the surface preparation technique for each is different.

1019

1018 Concentration (atoms/cm–3)

erroneous sheet resistance values if the epi layer is thin. This is due to autodoping from the substrate which will compensate the dopant in the epi layer. Thus, a lightly doped test wafer is commonly used for sheet resistance measurement by 4-point probe while epi thickness is measured over a heavily doped substrate. The 4-point probe technique is extremely precise com­ pared to other techniques discussed below. It is capable of providing repeatable measurements approaching /–0.1% over an extremely wide range of sheet resistances. Depth profile resistivity information for the epi layer is often determined by SRP [22]. The SRP tech­ nique requires that a small sample be beveled, with the spreading resistance measured by two probes at differ­ ent positions along the bevel. The extraction of resis­ tivity from spreading resistance is dependent upon the structure. Thus, if a heavily doped region is immediately beneath the epi layer the algorithm is different from a lightly doped region, which is in-turn different from a region of different doping type [22]. Figure 6.19 shows the SRP of an n-type epi layer on an n substrate. Regrettably, there is no formal definition for the tran­ sition region from low to high resistivity (or from high to low doping concentration). However, three tech­ niques are commonly used.

CHAPTER 6

1017

1016

2 μm

1015 5 μm 1014 0

5

10

15

Depth (μm)

Fig 6.19 ● 20 Ω-cm n-epi layer on n Sb substrate.

P-type epi surface preparation can be achieved by simply allowing the substrate to oxidize in air for 1 hour after epitaxial deposition. Alternatively, the sub­ strate can be prepared by a wash in SC-1 [23] solution to motivate oxide formation. N-type epi layers often require that the substrate surface be exposed to a hot HNO3 solution for 1 hour and then rinsed prior to making the CV measurement. The CV measurement is limited by doping concen­ tration and thickness by avalanche breakdown and the requirement of a minimum of 3 Debye lengths of sepa­ ration from the surface. A plot of the accessible resistiv­ ity vs. thickness is shown in Figure 6.20. The CV measurement can often be applied to prod­ uct wafers. Epitaxial p-type on p substrates, or n-type on n substrates can be measured with a single frontside contact in conjunction with a contact on the back­ side of the substrate (all dielectric materials must be removed from the back of the substrate in order to achieve a low resistance backside contact). The meas­ urement of opposite types (i.e., p epi on an n substrate or vice versa) require a double front-side contact, since the p-n junction will electrically isolate the backside of the wafer from the region under measurement. Although the CV measurement is not strictly destructive, wafers exposed to the Hg probe are not likely to be returned to the production line out of fear of contamination. Measurement of epi layer resistivity by surface potential provides a noncontact technique applicable 99

Silicon as MEMS Material

PA R T I

imu ma cce ssib le d epth Max

10

Minim um a cc

Resistivity (Ω-cm)

essib le

depth

100

1 0.1

1

10

100

1000

Depth (μm)

Fig 6.20 ● Limits of depth accessible to CV analysis.

to product wafers [21]. A beam of photons is chopped to provide an alternating source of exciting radiation on the wafer surface. The measured surface photo-voltage is then related to the doping level of the Si near the surface. Details of the method are discussed in Refs [21] and [24]. The noncontact nature of this method makes the use of SPV, also referred to as AC-SPV or SCP, truly a unique, nondestructive method for resistiv­ ity measurement. The use of SIMS [18] for doping concentra­ tion determination is relegated to very thin layers, typically  100 nm. SIMS is an expensive technique, often costing  US $ 1000 per measurement on an out­ source basis. Accuracy and precision of the measurement are in the order of / 10% at best, assuming a nearly religious adherence to calibration methodologies. The use of SIMS in MEMS applications is extremely rare.

6.6.3 Measurement of Ge in Si and SiGe Epi Layer Thickness The determination of Ge content in Si and SiGe epi­ taxial layer thickness can be accomplished by a number of different techniques. Rutherford Backscattering (RBS) [25], SIMS [18], spectroscopic ellipsometry [26], photoluminescence (PL) spectroscopy [27], scan­ ning Auger [28] and X-ray diffraction (XRD) [29] are commonly used. Of these techniques, RBS requires no standards or calibration and is, therefore, often used for

100

generating standards for the others. RBS is capable of providing both SiGe layer thickness and Ge composi­ tion information. The use of SIMS requires careful calibration to standards and, as previously noted, is an expensive tech­ nique. It does, however, provide the capability to deter­ mine depth profile information for Ge content as well as B, P, As, C and O down to a limit of detection in the 1  1016 cm3 concentration range. Regrettably, not all of this information can be obtained in a single meas­ urement scan, since an O sputtering beam must be used for accurate B measurements and a Cs sputtering beam must be used for O determination. Spectroscopic ellipsometry has demonstrated a capa­ bility for measuring Ge content in Si and also SiGe layer thicknesses. The use of multi-angle multi-wavelength spectroscopic ellipsometry has been the most successful approach. Fixed-angle, single wavelength ellipsometry has shown some similar capability but does not appear to have a sufficient number of degrees of freedom to yield unique solutions to the mathematical models needed for the independent determination of Ge con­ tent and SiGe thickness. The ellipsometry technique is considered to be nondestructive. Photoluminescence spectrometry is often carried out at low temperatures (e.g., 77 K or even 4 K) in order to achieve narrow well-defined spectral peaks of high inten­ sity due to the small energy distribution of electrons at low temperature [30]. More recently, room tem­ perature PL has been demonstrated in order to make this technique applicable as an in-line analysis tool for semiconductor fabrication [31]. In general, the tech­ nique involves the optical excitation of carriers in the crystal lattice which are then allowed to recombine in the absence of photons. The resulting location of the spectral peaks, as well as the peak width is used to determine degree of strain, Ge composition and layer thickness. Scanning Auger is useful for the determination of Ge in Si over a concentration range of 5–100% Ge. It is primarily useful for high concentration Ge measure­ ments where RBS, SIMS, PL and scanning ellipsometry have difficulties. Double crystal XRD is a technique which measures the crystal lattice and can, therefore, be applied to Ge content in pseudomorphic SiGe films. This technique is relatively fast, allowing a wafer to be profiled in less than 1 hour. Commercial tools are available for full wafer inspection and the technique is considered to be nondestructive. The reader is referred to Chapter 10 of reference [1], in addition to Refs [18] and [25] through [31], for further details regarding the measurement of Ge in Si and SiGe layer thickness.

Epi Wafers: Preparation and Properties

6.6.4

Defectivity Measurements

The most distinguishing characteristic of epitaxy over all other semiconductor manufacturing processes is that epi, like substrate manufacturing, is a single crys­ tal process. Thus, many defects which may occur during epi processing require inspection techniques outside the norm for other processes. Slip is the result of crystal plane movement caused by thermally induced mechanical stresses in a substrate during high-temperature processing. Figure 6.21 dem­ onstrates the geometric patterns of slip on (100) and (111)-oriented substrates. In extreme cases, slip can be observed by simply looking at a wafer with unaided eyesight. More com­ monly, wafers are inspected using phase contrast micro­ scopy (sometimes referred to as dark field or Nomarski microscopy) [32], automated optical laser-based surface scanning tools [33] or x-ray analysis [34]. Stacking faults occur when a contaminant on the wafer surface interrupts the growth of a contiguous sin­ gle crystal layer and polysilicon islands, surrounded by single crystal silicon, are established. Figure 6.22 shows the types of geometries observed for stacking faults on (100) and (111) silicon. Stacking faults can be observed using phase contrast microscopy [32]. In the case where slip is very difficult to observe, or stacking faults are very small (due to a thin epi layer) it can be desirable to decorate these defects with chemical etching prior to observation in a microscope. For (100)-oriented substrates the Secco [35], Schimmel [36] or Wright [37] etch chemistries may be used. Substrates having a (111) surface orientation require

(100) Si

(111) Si

Fig 6.21 ● Slip line geometries on (100) and (111) Si.

CHAPTER 6

the use of Sirtl [38] etch chemistry. Decorative etching is always a destructive technique. The reader is referred to an atlas of crystal defect micrographs [39] for a visual depiction of many macroscopic crystal defects. The measurement of metal contamination on the substrate surface may be accomplished through sev­ eral methods. For Fe, surface photovoltage [40], is a very sensitive technique which exploits the Fe-B bond energy in p-type Si. Other metals can be detected using a vapor phase decomposition (VPD) technique where the native oxide on the surface of the wafer is captured with a small amount of HF liquid, and the resulting liquid is then analyzed spectroscopically by TXRF or ICP-MS [41]. The measurement of particulate contamination on the substrate surface is accomplished using automated optical laser-based surface scanning tools [33]. Edge crown, shown diagrammatically in Figure 6.23, occurs when mass transport effects at the wafer edge in the epi deposition system cause increased epi growth rate at this area, compared to the rest of the wafer. Surface profilometry, using either a stylus which contacts the wafer surface [42], or a non-contact opti­ cal profilometer, are the most common methods for measuring edge crown [43]. Edge crown becomes a sig­ nificant issue as the epi layer thickness increases and is usually only important for layers 10 μm in thickness.

6.7 Commercially Available Epitaxy Systems The choice of a single wafer or batch processing approach for epitaxy is a compromise between film properties, productivity and cost. At first blush one might expect that productivity and cost are nearly syn­ onymous. However, the yield to specifications for sin­ gle wafer process tools is often higher than batch tools, particularly when exceptionally unforgiving film prop­ erties are specified. Further, some epi process tools can be purchased on a pre-owned basis for a much

Edge Crown Epi Layer

Si substrate

(100)

(111)

Fig 6. 22 ● Stacking fault geometries on (100) and (111) Si.

Fig 6.23 ● Edge crown formation often associated with thick (tepi  10 μm) epitaxial layers.

101

PA R T I

Silicon as MEMS Material

lower capital cost than a new tool, thus greatly reduc­ ing the cost-of-ownership (CoO) for processing due to a lower depreciation contribution compared to a new process tool. The reader is referred to the standard SEMATECH model for CoO [44] in order to compare the economics of various process tools. A comparison of process throughput between a sin­ gle wafer and batch process chamber is provided in Figure 6.24. As the epi layer thickness increases, the batch proc­ ess tool provides a higher productivity than single wafer processing. The crossover point is a very strong function of substrate diameter, as well as the details and require­ ments of the process. Thus, it is impossible to quantify this graph without a direct reference to a specific proc­ ess requirement and application. The following 2 exam­ ples illustrate the challenge between batch and single wafer process tool choices. A high-temperature process, for example, growing 20 μm of Si epi from SiHCl3 at 1100°C, would be car­ ried out at a deposition rate of 4 μm/min on a single wafer process tool, while a batch process tool would only be able to achieve 2 μm/min of deposition rate, due to mass transport limitations in the large batch process chamber. Further, the much larger thermal mass of the batch process tool would require substantially longer heat-up and cool-down times compared to sin­ gle wafer processing, as well as longer times for loading and unloading a batch of wafers, compared to only one wafer. On the other hand, the single wafer process tool would, by necessity, need to have the chamber etched

Throughput (wafers/hour)

Single wafer epi system

Batch epi system 150 mm substrates

Batch epi system 200 mm substrates

Epitaxial layer thickness (μm)

Fig 6.24 Comparison between batch and single wafer process tool productivities. ●

102

between each run, where the batch system may only need to be etched once every 100 μm or so (every 5 runs in this example). Obviously, the batch process tool has many more wafers present during the proc­ ess, but the precise number depends upon the design of the batch tool and the wafer diameter. Clearly, a final answer cannot be found without at least specifying the details of the batch tool and the wafer diameter. Low temperature processes have both similar and different issues. A selective epi deposition at, say 800°C or less, would likely have similar deposition rates for both the batch and single wafer tools since the deposi­ tion would be reaction rate limited, not mass transport limited. However, this deposition rate will be quite low. Therefore even a  1 μm film may require tens of min­ utes of deposition, providing an advantage for the batch tool. But the film thickness is so thin that the single wafer tool would not require etching between each run. The issues of wafer diameter and batch load/unload time compared to single wafer processing still remain, as do heat-up and cool-down time. Based on these two abstract examples, neither thin­ epi low-temperature processes nor thick-epi hightemperature processes can be simply assigned to a single wafer or batch process tool. The details of the process specifications, wafer diameter and specific process tools available must be considered carefully in order to make the best choice.

6.7.1 Single Wafer Systems Commercial single wafer process tools for Si epitaxy first became available in 1988 with the introduction of the Epsilon One from ASM Epitaxy [45], followed by the introduction of the Centura HT by Applied Materials in 1993 [46]. The development of an epi proc­ ess chamber around the requirements of a single wafer enabled unprecedented control of many issues suffered by batch process tools, most notably the control of slip as well as film thickness and resistivity uniformities. On-wafer film thickness and resistivity uniformities of 1 and 2%, respectively, are commonly achievable on 200 mm substrates. The basic design concept of the sin­ gle wafer epi process tool is shown in Figure 6.25. Single wafer process tools use a wafer holder, or sus­ ceptor, of very low thermal mass compared to batch processing systems. This allows much faster heating and cooling of the process chamber, which in turn greatly reduces the thermal budget of the process. The use of rapid thermal chemical vapor deposition (RTCVD) is essential for high productivity in such architectures. The process chambers used in RTCVD single wafer epi systems are very small in volume, which provide for a much higher mass transport capability compared to

Epi Wafers: Preparation and Properties

batch epi tools. Thus, substantially higher growth rates can be achieved in the mass transport limited regime, as much as 5 μm/min at 1150°C in a single wafer system compared to 2 μm/min in a batch process tool using SiHCl3. Further, autodoping from the substrate is less in single wafer systems due to the increased mass trans­ port allowing dopant species emanating from the sub­ strate to escape from the region adjacent to the growing epi layer. The use of a load-lock in conjunction with the proc­ ess chamber enables loading and unloading of the sub­ strate at high temperatures, typically in the range of 700°C to as much as 1000°C. The use of such high load/unload temperatures is critical to productivity as it reduces the heat-up time and, far more importantly, greatly reduces the cool-down time to unloading. Due to these high temperatures, and the environment in which the substrates are handled, all substrate load­ ing and unloading is automated. A very significant sec­ ond benefit of load-locked loading/unloading is that such a configuration enables low-temperature epitaxy, by eliminating exposure of the process chamber to air. This allows the process chamber to maintain a very low background partial pressure of oxygen and water vapor, essential to the successful low-temperature processing of Si and SiGe. Finally, the low background water vapor partial pressure essentially eliminates stacking fault formation (other than oxygen induced related stack­ ing faults or OSF) since oxide free surfaces are easily achieved by hydrogen bake prior to epitaxy. The single wafer approach to epitaxy has become the work-horse of the Si and SiGe epi industries since the

CHAPTER 6

mid-1990s. However, as previously mentioned, it may not be the optimum choice for some epi processes due to economic and productivity concerns.

6.7.2 Batch Systems Epitaxial deposition systems using batch technology were the dominate methodology for substrate diame­ ters of 150 mm and less. To a first order approximation, a batch epi reactor processes a fixed area of Si (m2) per run, whereas a single wafer tool processes one wafer per run, regardless of substrate diameter. On a throughput basis, the batch process tool has an obvious advantage at smaller substrate diameters. The inductively heated pancake reactor, shown in Figure 6.26 [47], uses RF energy to heat the SiC coated susceptor via eddy currents. This design was hampered by the backside of the wafer being at a higher temper­ ature than the front-side, which resulted in bowing of the wafer and slip. Cutting a spherical profile into the pockets where the wafers reside greatly reduced this problem. The radiantly heated barrel reactor in Figure 6.27 [48] further reduced the occurrence of slip by heating the substrates from the front using tungsten-halogen lamps. The inductively heated barrel reactor in Figure 6.28 [49] uses RF energy to heat the susceptor. In this design, the induced current flows around the susceptor, unlike the RF pancake where the susceptor is heated by eddy currents.

N2 purged load-locks Fused silica bell jar N2 purged wafer xfr chamber

Wafer xfr robot

Process module

Process module

SiC coated graphite susceptor

Process module

Fig 6.25 Single wafer epi system architecture showing up to 3 process modules on an integrated tool. ●

Gas exit

Gas inlet

RF coils

Fig 6.26 ● The inductively heated “pancake.”

103

Silicon as MEMS Material

PA R T I Fused silica bell jar

Gas inlet

Wafer Waf er φ

Batch

100 mm 125 mm 150 mm 200 mm

>30 32 21 5

Fig 6.29 ● The PE2061S inductively heated barrel epi system from LPE Epitaxy. Used by permission. (Courtesy LPE) Lamps SiC coated graphite susceptor Gas exit

Fig 6.27 ● The radiantly heated “barrel.”

Gas inlet Fused silica bell jar

RF coils

Wafer φ 125 mm 150 mm 200 mm

Batch 10

8

5

Fig 6.30 ● The PE3061D inductively heated pancake epi system From LPE Epitaxy. Used by permission. (Courtesy LPE)

The PE2061S, shown in Figure 6.29 and PE3061D, shown in Figure 6.30, have claimed process capability approaching that of single wafer process tools [49, 50]. The CSD EpiPro-5000, shown in Figure 6.31, claims on-wafer thickness and resistivity uniformity capability of, nominally 1% and 2%, respectively, for processing on 150 mm substrates [51]. As noted previously, the best choice of epi process tool requires consideration of the technical require­ ments, as well as productivity and economic perform­ ance. A detailed assessment of what is required and what is desired is essential to realizing the optimal choice.

6.8 Summary Gas exit

SiC coated graphite susceptor

Fig 6.28 ● The inductively heated “barrel.”

104

Si epitaxy processing for MEMS applications is most

often performed at AP and high temperature using

Epi Wafers: Preparation and Properties

Fig 6.31 ● The EpiPro-5000 inductively heated pancake epi system from CSD Epitaxy. Used by permission. (Courtesy CSD)

SiHCl3 as the silicon precursor. Doping of the epi layer is accomplished in-situ using B from B2H6 for p-type

CHAPTER 6

epi and As or P from AsH3 or PH3, respectively, for n-type epi. Epi layers used for etch stops may be either heavily p-type doped, where NA  1020cm3, or pseudomor­ phic SiGe, with Ge contents of 30%. The choice of epi structure used for the etch stop is based on etch chemistry and the layer thickness required. The epi-poly process, where epi is deposited over single crystal Si and polysilicon is deposited over a die­ lectric region, is often used in MEMS structures. If the dielectric region is not covered with Si prior to deposi­ tion, the use of a non-chlorinated Si precursor, usually SiH4, is essential to successful processing. Selective epi can be used to grow Si only on exposed Si regions without deposition on adjacent dielectric areas. Epitaxial layer overgrowth is based on the selec­ tive epi process methodology and can be used to grow lateral monocrystalline silicon regions over dielectrics. Although single wafer epi systems dominate the Si semiconductor industry as a whole, batch epi systems still play an important role for MEMS. Thick epi lay­ ers require long deposition times and the CoO for sin­ gle wafer processing, compared with batch processing for thick epi layers, can far out-weigh the performance advantages of single wafer systems for cost sensitive, high volume commodity MEMS products. Hard, honest cost and technical performance evaluations are essential to choosing the correct epi system architecture.

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