Evaluation of symmetric flying capacitor multilevel inverter for grid-connected application

Electrical Power and Energy Systems 115 (2020) 105430

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Evaluation of symmetric flying capacitor multilevel inverter for gridconnected application

T

Muhammad Humayuna, Muhammad Mansoor Khanb, Muhammad Alib, Xu Jianmingc, ⁎ Weidong Zhanga, a

Department of Automation, SEIEE, Shanghai Jiao Tong University, Shanghai 200240, PR China Department of Electrical Engineering, SEIEE, Shanghai Jiao Tong University, Shanghai 200240, PR China c State Grid Changzhou Power Supply Company, Changzhou, Jiangsu, PR China b

A R T I C LE I N FO

A B S T R A C T

Keywords: Symmetric flying capacitor (SFC) Multilevel inverter (MLI) Level shifted (LS) PWM Static compensator (STATCOM) DC voltage balancing

Grid voltage regulation and reactive power control have been revolutionized by high-voltage high-power multilevel inverters (MLIs) topologies. The implementation of such inverters in STATCOM application make it more feasible due to its multilevel output voltage, low harmonics, high modularity, and high-power quality. However, these topologies require more number of devices which adversely affect the overall system’s size, cost, and increase the control complexity. Recently, a packed U-cell (asymmetric flying capacitor) topology has been reported in literature with more output voltage levels using minimum number of components count. The conventional packed U-cell MLI utilizes DC-sources to fed AC loads. In this paper, a symmetric flying capacitor (SFC) MLI is introduced for grid-connected application. The proposed topology is suitable for medium voltage high-power grid-connected applications due to low voltage rating of switches. The SFC-MLI utilizes DC-capacitors instead of DCsources, therefore the inverter suffers from voltage imbalance problem. The voltage imbalance is due to nonideal devices, asymmetric switching losses, and/or non-linear loads. Hence the capacitor balancing is relatively challenging task due to availability of limited number of redundant switching states. A multi-stage feedback control method is proposed with level-shifted (LS) PWM technique to address this issue. Furthermore, a comprehensive comparison in terms of redundant switching states and voltage rating of switches, has been carried out to highlight the superiority of the proposed topology over the existing packed U-cell topologies. In addition, the devices count, and components losses are studied. Finally, simulated and experimental results for different scenario are presented to validate the proposed topology and its control technique.

1. Introduction Multilevel inverters (MLIs) have attracted significant attention because of their suitability for medium- and high power applications, such as flexible alternating current transmission system (FACTs) [1]. Applications of FACTs controllers including static synchronous compensator (STATCOM) and static synchronous series compensator (SSSC) are increasing in power systems. This is due to their ability to stabilize the transmission systems and to improve power quality in distribution systems. STATCOM is very popular as a reliable reactive power controller replacing conventional var compensators. It also provides active power oscillation damping, flicker attenuation, voltage regulation, etc. Generally, in high-power applications, var compensation is achieved using conventional multilevel inverters. The basic concept of

MLI is to develop high power by using multiple low DC voltage levels and low power rating switches to achieve power conversion by producing a staircase voltage waveform. MLIs have better efficiency in generating the high voltage (HV) with low harmonic profile compared to two-level traditional inverters. Due to low distortion at the output voltage, it can also reduce the dv / dt stresses, thereby reducing electromagnetic interference issues and improve the output voltage quality [2]. In the last few decades, different MLI topologies were extensively studied for STATCOM applications: (1) natural point clamped (NPC) MLI; (2) flying capacitor (FC) MLI; and (3) cascaded H-bridge (CHB) MLI. The diode clamped based STATCOM is presented in [3]. The NPC-MLI is mostly restricted to a three-level configuration because of the complex layout of the diodes (which grows as the square of the number of levels). Sanghun et al. presented FC-MLI with space vector switching scheme. Flying

⁎

Corresponding author. E-mail addresses: [email protected] (M. Humayun), [email protected] (M.M. Khan), [email protected] (A. Muhammad), [email protected] (J. Xu), [email protected] (W. Zhang). https://doi.org/10.1016/j.ijepes.2019.105430 Received 30 May 2018; Received in revised form 16 July 2019; Accepted 22 July 2019 0142-0615/ © 2019 Published by Elsevier Ltd.

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the SFC topology allows the inverter to be attractively suitable for high power application [39] due to voltage-rating of an inverter can easily be extended by increasing the number of cells in a module or by cascading more modules in an inverter. The SFC-MLI produced good quality voltage which significantly reduces the number of power switches and gate drivers. It is more practical in high power grid application because of its simple layout and modularization. Moreover, in FACTs application, SFC inverter consists of a large number of the DC-voltage sources. These voltage sources are usually realized by galvanically isolated DC-capacitors where the exogenous power source is eliminated. One drawback of SFC inverter is chargebalancing problems that plague many multilevel topologies. A charge imbalance originates from the tolerance of capacitance, non-ideal switching losses, leakage currents, asymmetrical switching, transients in the system, asymmetrical ac-side current, and uneven charging and discharging of multiple DC-sources at different voltage levels. A DC voltage imbalance will degrade the quality of the voltage output; in severe cases, this could lead to the complete collapse of the power-inversion system [40]. Balancing these voltages is a major research challenge in multilevel inverters. In the aforementioned packed U-cell applications, the DC-link voltages balancing are not necessary. In this paper, symmetric flying capacitor five-level multilevel inverter is proposed for grid-connected application. In previous literature, the idea of SFC-MLI for grid-connected reactive power control application has not been presented. The main contribution of this paper is listed below:

capacitor topology suffers from a higher number of capacitors along with the increment of capacitor size and design complexity. Among these conventional MLIs, cascaded H-bridge got more attention for STATCOM applications [4]. Along with the exploration of cascaded Hbridge, researchers paid attention to evolve newer application oriented topologies with fewer components count and with simpler structure [5]. To produce a higher number of output voltage levels using a less number of switching devices, numerous newly structure multilevel topologies have been introduced in the literature [6–18]. The reduction of switches in the MLI topologies has to lead to enormous significance in academia and the industry. The reduction in switching number further reduces the number of components including gate drives. However, these topologies are simple, but voltage splitting and extending them to three-phase, the configuration and control become more complex [19]. Great attention needs to pay that the cell structure is a building block of the cascaded MLI. To minimize the switching power losses and cost in a cell-based MLI, it is important to conceive a cell configuration which higher voltage levels with the optimized number of devices. Therefore, to produce three-levels of voltage, the full H-bridge consider as a cell. To getting five-levels at the output side, cascading two full Hbridges. This leads to an increase in a switching components. To further optimize the number of switching devices and minimize the switch losses in cascaded H-bridge inverter, the idea of the packed U-cells (PUC/ asymmetric flying capacitor) topology fed by unequal DC constant sources has been suggested by Ounejjar and Al-Haddad in [6]. Compared to the full H-bridge cell configuration, the packed U-cell structure is more compact. This paper focuses on the modified structure of new developed packed U-cell (flying capacitor) MLI. There are several approaches suggested to reduce the device count in MLIs topologies [1]. The approaches used for reducing device count are classified into three groups: (1) developing new MLIs topologies; (2) asymmetric DC-sources used in an inverter; and (3) combining both approaches [20]. Utilizing unequal voltage sources in packed U-cell inverter can eliminate redundant output voltage levels. Therefore, high voltage levels can be obtained using smaller number of components in an inverter. This may lead to reduction in the cost and area of the whole inverter. In current literature, a single constant voltage source with capacitors packed U-cell topology is utilized for several applications i.e., a boost converter, active power filter, photovoltaic, and dynamic voltage restorer applications [21–26]. Although packed U-cell has numerous merits over traditional topologies, however, the same polarity packed U-cell still need to be improved. The major drawback of this topology is: unable to produce the summation of DC voltages at the output side. The newly developed structure proposed in [7–10,27,11–13,28,14–17] achieved higher voltage levels by utilizing less number of a component in an inverter. However, these topologies suffer from complex control DC-voltages and asymmetric structure. This leads the asymmetric power rating of components, and an increase in the voltage levels required modification in voltage rating of DC-capacitors [29]. In addition, the inverter that composed by asymmetric voltage rating devices cannot achieve every output voltage steps by increasing DC-voltage sources [30]. These limitations lead the existing topologies impractical and not well suitable candidates for medium–power grid-connected applications. For grid-connected applications i.e., STATCOM and active power filter (APF), modular structure MLI composed of basic modules or cells are an attractive solution which split the desired voltage [31]. Nevertheless, to increase the efficiency and overcome the aforementioned limitations, many researchers have presented numerous modified packed U-cells configurations are designed [32,33]. The modified packed U-cell (symmetric flying capacitor (SFC)) topology that is also suggested by several authors [34–37] that gain the attraction because of ease to balance DC-capacitors voltage, and inherent faulttolerant capability, compared with other topologies it leads to mitigation of individual switch stresses [38]. Based on aforementioned merits,

• A detailed comparative study of the asymmetric and symmetric

FCbased on DC-capacitor arrangement is carried out to demonstrate the distinctive characteristics and features of the SFC inverter. The power losses across the IGBT/diode and passive devices have also been discussed. Practically some effort needs to utilize inverter switches properly i.e., the balancing of DC-capacitors voltage with a minimum number of switches that lead to a reduced number of redundant switching states (RSS) for same voltage level. In order to regulate instantaneous DC-capacitors voltage in various conditions, two voltage balancing methods are utilized. The first technique is based on the standard multilevel modulation method. It employs an RSS table associated with the level-shifted PWM technique to achieve capacitor voltage balancing. In addition, it is easy to implement with less control complexity and has less computational burden therefore, it can be easily generated for an inverter with any desired number of levels. The concept of the second proposed method referred to herein as the multi-loop control approach which regulates instantaneous DC-capacitor voltage by implementing a feedback control scheme with output current feed-forward compensation strategy. Initially, the single-phase grid-connected system comprising the suggested topology is simulated, and its loss evaluation is manifested through simulated results. As for the authorś knowledge, the laboratory scaled-down prototype of the proposed inverter is developed for the first time to validate the proposed scheme. The detailed simulation and experimental results under steady state and transient operating conditions are added to validate the proposed inverter. MLI

•

•

The remainder of this paper is organized as follows. The structure, operating principle, and derived analytical equations to calculate the nodal voltage and current of asymmetric and symmetric flying capacitor FC-MLI and establishes the DC capacitor ripple voltage equations and the criterion for sizing the DC capacitors are presented in Section 2. Active and passive components power losses and efficiency calculation is discussed in Section 3. Switching technique and proposed control method are detailed in Section 4. Section 5 presents the comprehensive compression between asymmetric and symmetric flying capacitor multilevel inverters. Results and discussion achieved from Simulink, as 2

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Fig. 1. New developed

FC-MLI

topologies.

capacitor (VCn ) is calculate by following equation:

well as laboratory test results obtained from a real prototype implementation of proposed topology, are presented in Section 6. Finally, the conclusions drawn from the study is given in Section 7.

VCn = (2n − 1) Vdc

(1)

nth

here, n = 1, 2 represent the number of capacitors. To achieve higher output voltage levels from Eq. (1), the voltage rating of first capacitor VC1 is equal to Vdc and second capacitor voltage rating VC2 is equal to 3Vdc . The output obtained from the seven levels is ± 3Vdc, ± 2Vdc, ± Vdc , and 0. The output voltage of asymmetric ASP-SFC-MLI can expressed as follows:

2. New developed flying capacitor topologies The researchers are continuously struggling to increase number of output voltage levels with the use of minimum component count. It is obvious that in an increased the number of DC-source leads to increase the voltage steps which enhance the inverter efficiency. In this paper, merits and demerits of flying capacitor topologies proposed in [6,34] are addressed. The performance of both topologies are analyzed with same number of DC-sources and power switches. Furthermore, FC topology is categorized into two parts according to capacitors arrangement, is shown in Fig. 1. SP-Same

n+1

vab =

[(−1) j + 1 (1 − Sj )(Vdc (j + 1) − Vdc (j) )] (2)

j=1

ij =

(−1) j + 1 (Sj

− Sj + 1) × iab.

(3)

Since, only three pair of switches used in an inverter, then eight possible modes combinations can be identified as listed in Table 1. The zero voltage level has two redundant switching modes and the other six switching modes represent the six suitable inverter voltage levels as express follows:

polarity (SP-FC-MLI) polarity (AP-FC-MLI).

AP-Alternate

2.1. Same Polarity (SP)

∑

FC-MLI

1. 2. 3. 4.

Same polarity FC topology has been shown in Fig. 2. It is composed by six switches and two DC-links. The DC-links consists of constant voltage sources and/or capacitors depends on applications. According to arrangement of DC-links connection, first DC-link connect to another with same polarity through power switches. Thats why, it is called same polarity (SP) flying capacitor MLI in this paper. The same polarity FC topology is divided into two subparts,

Modes Modes Modes Modes

1 3 5 7

and and and and

2 4 6 8

generate 0Vdc are possible switching states to develop ± 3Vdc are switching combination for ± Vdc produce ± 2Vdc voltage levels

The maximum levels (Nsteps ) of inverter voltage and power switches (NIGBT ) can be expressed by the following mathematical expression:

• Asymmetric - • Symmetric - -

SP FC MLI

Nsteps = 2nC + 1 − 1

(4)

NIGBT = 2nC + 2

(5)

here, nC is total number of

SP FC MLI

In asymmetric FC-MLI, the voltage rating of DC-sources used in an inverter are asymmetrical with each other. In symmetric flying capacitor MLI, the DC-sources are correspondingly symmetric to each other.

DC-capacitors.

2.1.2. Symmetric SP-FC-MLI Asymmetric multilevel inverter leads to increase the output voltage levels, but use of asymmetric inverters is not really extended due to different voltage rating devices. This feature caused to lost the modularity of inverter and makes unsuitable for industrial application. To overcome these shortcoming of asymmetric MLI, symmetric devices to be used in an inverter to make it modular and well suited for industrial application. Utilizing symmetric voltage sources in same polarity FC inverter, the number of output voltage levels are reduced by connecting the same polarities of capacitors as shown in Fig. 2b. This may leads to increase the cost and reduce the efficiency of the inverter. Due to subtractive

2.1.1. Asymmetric SP-FC-MLI The operating principle of asymmetric voltage sources with SP-FC is analyzed with the help of two DC-link capacitors C1 and C2 . These DC-link capacitors are connected with the same polarity (SP) each other through power switches, as shown in Fig. 2a. The asymmetrical voltage rating capacitors lead to increased output voltage levels by utilizing reduced number of active switches. Therefore, the asymmetric voltage rating capacitors utilized in an inverter. The voltage rating of each DC3

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Fig. 2. Same polarity

Table 1 Switching states of Modes

1 2 3 4 5 6 7 8

Nsteps = 4nC − 1. SP-FC-MLI

Switching states

S2

S3

Asymmetric

1 0 0 1 1 0 0 1

1 0 1 0 1 0 1 0

1 0 1 0 0 1 0 1

0 0 3Vdc − 3Vdc Vdc − Vdc 2Vdc − 2Vdc

SP-FC

(vab)

Symmetric

SP-FC

(vab)

0 0 Vdc − Vdc Vdc − Vdc 0 0

1. 2. 3. 4.

Modes Modes Modes Modes

1 3 5 7

and and and and

2 4 6 8

produce 0Vdc are the switching states to synthesize ± 2Vdc construct ± Vdc obtain ± 3Vdc voltage levels

The voltage stress on each switch Vstress (j) can be easily obtained as follows:

behavior, the SP-SFC is not a suitable candidate for symmetric SP-FC topology, therefore, it is not discussed in this paper. The conduction states and modes of symmetric SP-FC inverter is listed in Table 1. 2.2. Alternate Polarity (AP)

(7)

To achieve maximum voltage levels from the asymmetric AP-FC-MLI, the C1 voltage rating must be twice that of C2 . In Table 2, eight possible switching modes are listed to construct seven-levels at the output voltage of the inverter. The seven output voltage levels are achieved by controlling switches according to following modes:

Output voltage

S1

Vstress (j) = VC (j − 1) + VCj.

(8)

2.2.2. Symmetric AP-FC-MLI This paper focus on symmetric AP-FC topology as shown in Fig. 3b. Fig. 4 shows the symmetric AP-FC based STATCOM which is connected to main grid Vgrid through filtering inductor L. In the symmetric AP-FC-MLI, the output voltages are adding due to series connection of DC-link capacitors. In this subsection, the working principle of five-level AP-SFC-MLI is described with the help of n = 2 identical DC-link capacitors and n + 1 = 3 complementary pair of switches (Sn, Sn ). For complementary switch pair, turning ON one switch excludes the other from being turned OFF. The three complementary pairs are S1, S1, S2, S2 and S3, S3 . Gating signals S1, S2, S3 , are generated by inverting S1, S2 ,and S3 . In each switching mode, half of the switches are conducting to produce the desired output voltage level. 2Sn = 8 valid operating modes can be achieved through complementary pairs of switches (Sn ). The operating modes are described in Table 2 with the possible output voltage levels and conduction paths are shown in Fig. 5. The output voltage (vab ) and the source current (iab ) of the SFC inverter are found through following mathematical expression as follows:

FC-MLI

The basic structure of alternate polarity FC-MLI is shown in Fig. 3. The (n) levels are synthesizing by connecting 2 isolated DC-voltage sources and six power switches. The AP-FC-MLI consists of reverse connected of cells. Each cell consists of a pair of active switches and a capacitor clamped between the switches. Each switch has the ability to conduct bidirectional current. The active switches are connected in reverse direction (with the opposite polarities) with each other. According to the capacitors voltage ratings, the AP-FC can be further divided in two parts: 1. Asymmetric AP-FC-MLI 2. Symmetric AP-FC-MLI 2.2.1. Asymmetric AP-FC-MLI The generalized structure of asymmetric AP-FC topology is shown in Fig. 3a. The DC-capacitor voltage ratio (VCj ) and output voltage levels (Nsteps ) are expressed as:

VCj = 2 j − 1Vdc

FC-MLI.

n+1

vab = (6)

∑ j=1

4

[(−1) j + 1 (1 − Sj )(VCj + 1 + VCj )] (9)

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Fig. 3. Alternate polarity Table 2 Switching states of Modes

1 2 3 4 5 6 7 8

FC-MLI.

1 if Sj switch is on Sj = ⎧ ⎨ ⎩ 0 if Sj switch is off

AP-FC-MLI

Switching states

Inverter voltage

S1

S2

S3

Asymmetric

1 0 0 1 1 0 0 1

1 0 1 0 1 0 1 0

1 0 1 0 0 1 0 1

0 0 2Vdc − 2Vdc Vdc − Vdc 3Vdc − 3Vdc

AP-AFC

(vab)

Symmetric

AP-SFC

(11)

with S¯j being the complement of Sj . The voltage stress on switch pairs (S1, S1,) and (Sj + 1, Sj + 1,) are equal to Vdc , due to identical voltage rating capacitors, whereas the voltage stress on the rest of the switches are equal to 2Vdc each as shown in Fig. 4. The number of output voltage levels (Nsteps ) can be expressed as:

(vab)

0 0 Vdc − Vdc Vdc − Vdc 2Vdc − 2Vdc

Nsteps = 2nC + 1.

(12)

The blocking voltage on switch is same as asymmetric AP-FC topology, and explain in Section 2.1.1. For safe and proper inverter operation, the output inverter voltage is composed of equal magnitude voltage levels, and the input voltage is equally distributed in the power switches. This is obtained if:

VCj = VC1 = VC2 = Vdc

(13)

2

Vref =

∑

VCj.

j=1

(14)

Different output voltage values are obtained from different patterns of controlling switches. The output voltage has five DC voltage levels i.e. ± 2Vdc , ± Vdc , and 0. The maximum voltage level is ± 2Vdc . The AP-SFC-MLI topology is better due to redundant switching modes. To obtain zero voltage level, Mode 1 and 2 become a redundant state. Mode 3 and 5 are the possible combinations to achieve the Vdc voltage level. Similarly, Mode 4 and 6 have the ability to generate − Vdc voltage level at the output. 2.3. Design of flying capacitors

Fig. 4. Basic structure of five-level

i j = (−1) j + 1 (Sj − Sj + 1) × iab.

Rating of the DC-link capacitor bank of a inverter may have a significant impact on the cost and physical size of a FACTs controller. The capacitor is sized for a specified ripple voltage, maximum 10% of the nominal voltage. The STATCOM mode of operation (i.e., current and voltage in quadrature) yields the highest ripple current in the capacitor and hence the highest voltage ripple [41]. When the inverter is connected with grid in parallel for charging operation, the capacitor voltage ripple losses occur by the difference

SFC-MLI.

(10)

Switching function Sj is defined as: 5

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Fig. 5. Operating and conduction modes of

SFC-MLI.

between the respective input voltage and the voltage across of capacitors [29]. Therefore, the ripple voltage of capacitors (ΔvCj ) is taken from:

ΔvCj =

1 Cj

∫t iC (t ) dt. j

(15)

This voltage ripple in the DC voltage of the capacitors will cause harmonics in the output voltage. Furthermore, it can cause unexpected behavior on the control system action. To control unexpected behaviour of capacitor the feed back control has been designed in Section 4. To reduce the capacitor ripple magnitude, the capacitor must be properly sized. Larger size capacitor results in higher cost, whereas smaller size capacitor lead to unacceptable voltage ripples magnitude. To facilitate the design Fig. 6 gives graph for flying capacitor ΔvCj voltage ripple versus normalized STATCOM output current obtained through MATLAB. The normalization has been done using nominal power, nominal RMS voltages, current and line frequency as base parameters. The model is implemented and tested in MATLAB for different capacitor value. The normalized capacitor value over the inverter current gives an inverse proportional value to the ripple amplitude ΔVCj . The design value around 10 pu can result in optimum trade off between capacitor size and voltage ripples.

Fig. 6. Capacitor voltage ripples value at different current ratings.

3. Losses calculation Multilevel inverters consist of active and passive components. In this paper, the active and passive components losses are considered. The losses sustained due to the active components are conduction losses, blocking losses, and switching losses. The conduction losses are due to ON-state resistance, and the blocking losses are produced by reverse leakage current, these losses are insignificant, and are not 6

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discussed in this paper. The switching losses are generated by changing switching states from ON to OFF and vice versa [42].

Ploss _ on (j) = fs

3.1. Switch losses

Similarly,

The topologies discussed in this paper consist of power switches with antiparallel diodes. A diode provides unidirectional conduction path, whereas active switch has bidirectional conduction abilities. To generate each level of the output voltage, three switching devices will be conduct. The conduction of the switching devices (switch or diode) depend on direction of the inverter current. For example, in Mode 3, if current direction from a to b, the diode S¯1 and S2 will conduct while S3 switch will conduct. If the direction of current is from b to a, then S¯1 , S2 switches and S3 diode will conduct. The analytical estimation of the switching-, conduction-, and totallosses for the proposed inverter is carried out. The method described for power loss calculation in [43], which is based on extrapolation of the manufacturerś datasheet is employed. The switching power device used for the study is SK60GAL123 (semikron) with a rating of 1200 V, and 50 A. The simulated current through each device and their blocking voltage data are considered for the loss calculation. The instantaneous conduction (Pins ) and average conduction (Pavg ) losses of the switching devices can be expressed as follow: [44,34]

Pins (s) = (rs i γ + vs ) iL

(16)

Pins (d) = (rd i + vd ) iL

(17)

Pins = Pins (s) + Pins (d)

(18)

Pavg =

1 π

∫0

π

∑ j=1

1 t ⎞ ⎛ iL ⎛ ⎡⎛ ⎞⎞ ⎤ ⎢ vb (j) t ⎜− t ⎜t − ton⎟⎟ ⎥ = 6 vb (j) iL·ton·fs on ⎠ ⎝ on ⎝ ⎝ ⎠ ⎠ ⎣ ⎦ ⎜

OFF-state

Ploss _ off (j) = fs

∫0

toff

⎟

power losses can be mathematically expressed as:

⎡⎛ t ⎞ ⎛ i¯L ⎛ 1 ⎞⎞ ⎤ ⎢ ⎜vb (j) t ⎟ ⎜− t ⎜t − toff ⎟⎟ ⎥ = 6 vb (j) iL·toff ·fs off off ⎠⎝ ⎝ ⎠⎠ ⎦ ⎣⎝

(23)

(24)

3.2. Passive components losses

[(ns ·vs + nd ·vd ) iL + (ns ·rs·iLγ + 1) + (nd ·iL2)] d ⎛⎜ωt ⎞⎟ ⎝ ⎠

(19)

As discussed earlier in Section 1, for STATCOM application the inverter is equipped with DC-capacitors. These capacitor are connected in parallel with grid in inductive mode of operation. The ripple losses develop the difference between the voltage across DC-capacitors and grid voltage. Therefore, the leakage loss PCleak caused by capacitor leakage current ICleak is [46]:

(20)

⎡1 ⎛ ⎞ ⎤ ⎢ 6 vb (j)·iL ⎜ton + toff ⎟ fs ⎥ ⎝ ⎠ ⎦ ⎣

PCleak = ICleak × VC

ON

and

OFF

(25)

The ESR power loss is equal to 26:

PESR = IC2ripple × RESR

(26)

tanϕ 2πfs C

(27)

RESR =

here, RESR is the capacitor equivalent resistance, and ICripple is the ripple current of the capacitor. RESR has the relation Eq. (27) with the

(21)

Fig. 7.

(22)

In Eq. (22) and (23), Ploss _ on (j) are the turning ON losses, Ploss _ off (j) ( j = 1, 2, 3, …) are the turning OFF losses, Ton and Toff are turning ON and OFF time of switches, respectively. vb is blocking voltage of the switch. iL is conduction current and i¯ is leakage current. Here, fs is switching frequency of active devices of the inverter. From MATLAB simulation, an instantaneous current, which is flowing through the device, is sampled and respective energy loss is computed for each switching transition. The calculated energy loss on each switching transition over a fundamental cycle is added and then multiplied by fundamental frequency to obtain the average switching power loss in a device. The procedure is repeated for all the devices of the converter to get the total switching power loss. Similarly, the sampled device current is multiplied with the saturation voltage (Vsat ) or diode drop (Vf ) over a fundamental cycle depending upon the current direction to get the conduction losses [45]. The switching and conduction losses of the active components is illustrated in Fig. 8. The total losses of the inverter is shown in Fig. 9 where combining conduction losses and switching losses of the active components as follows:

here, rs and rd are the equivalent resistance of the switch and the diode during conduction, respectively. γ is switch characteristics constant, and vs and vd are voltage drops of conduction state of the switch and diode, respectively. iL is load current. ns and nd are the number of switches and diodes during conducting period. The entire switching losses are obtained by typically switch. Later the individual switching losses are then added to the derived entire switching losses of the inverter. A linear approximation of power losses during a switching transition from OFF to ON of the switch can be expressed as shown in Fig. 7: [44,34].

PSw =

ton

PT = Pcond + PSw.

Pcond = Pavg + Pins

2n + 2

∫0

states losses of S1 and S2 . 7

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Fig. 8. Switching and conduction losses of S1 and S2 .

Fig. 10. Comparison of proposed topology with traditional five-levels topologies.

Fig. 9. Total power losses of S1 and S2 .

dissipation factor tanϕ . The total loss of capacitor is expressed as:

PCloss = PCleak + PESR

selected as 3.2 kHz and 1.6 kHz, respectively. From Fig. 10 it has clearly seemed that proposed topology has greater efficiency comparatively traditional topologies due to a reduced number of switches used in an inverter which brings fewer conduction losses. To further increase the efficiency of SFC-MLI and reduce the conduction losses, a three phase configuration for high voltage example discussed below. EXAMPLE: In high power applications where low conduction losses are required, such as mining industries, the conduction losses and heat dissipation are challenging parts for researchers and designers. Until here, the topology was drawn with full IGBT configuration. It is worth mentioning that the SFC topology in hybrid configuration is more suitable for such application. Hybrid in the sense that the switches are of mixed type, IGBT and IGCT, according to their respective voltage stresses in the circuit. In SFC, the S2vdc switches are replaced by IGCT due to low switching frequency stage (fundamental switching frequency) which makes use of IGCTs interesting in terms of conduction losses and better heat dissipation. To reduce the conduction losses and for better heat dissipation, the SFC inverter is better choice compare to cascaded Hbridge. As an example, consider a three phase mining system of 2-kV 3.3MW with star-configured SFC module in each phase. All the Svdc (low voltage) IGBTs selecting FF1800R17IP5 (INFINEONTM) with voltage and current ratings of 1.7-kV and 1800-A, respectively and choosing S2vdc (high voltage) IGBTs with ratings of 3.3-kV and 1800-A (FZ1200R33KF2C (INFINEONTM)). The voltage stresses of the switches are shown in Fig. 4. The total IGBTs used for the 3.3-kV STATCOM are 18 (= 6 × 3). Each SFC module has two floating DC-capacitors with 2000-V DC-mean voltage. The three-phase switching and conduction losses of Svdc and S2vdc power switches are simulated by MATLAB and depict in

(28)

The total value of ripple loss, for one full cycle of output waveform is equalized to the following equation [29]:

Prip =

fS 2

2

∑

Cj ΔVC2j

(29)

j=1

Inductor losses can be estimate is similar fashion. However the inductor current is sinusoidal, hence considering the equivalent resistant RL of the inductor.

PL = RL iL2_ rms = RL

iL _ peak (30)

2

3.3. Efficiency Finally, the overall efficiency of the proposed improved be defined by the following:

η=

Pout PT + PCloss + Prip + PL + Pout

SFC-MLI

can

(31)

Fig. 10 shows the efficiency comparison of traditional topologies with proposed topology. To meet the efficiency requirement of the topologies, the same switching frequency, and the same switching devices rating determined in an iterative simulation model. The efficiency is calculated at various power loads ranging from 2 to 8 kW. The switching frequency for high and low frequency switching devices is 8

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Fig. 13. Output voltage and holding voltage of different Sj switches.

Fig. 11. Comparison of switching and conduction loss of Svdc and S2vdc devices at three phase system.

inductances and placing the snubbers across IGBTs/IGCTs and voltage clamp to minimize switching current path. The voltages of S1 S2 ,and S3 switches for a five-level SFC, operating under sinusoidal modulation is simulated byMATLAB as shown in Fig. 13. The parameter value to achieved Fig. 13 is given in simulation Section 6.1. The total inverter AC voltage vinv is given by the following equation:

Fig. 11. If the two modules of H-bridge are cascaded in three phase system then the conduction losses will leads to increase around 14.4%. Whatś more in SFC the conduction losses can further possible to reduce 2∼3% by replacing S2vdc IGBTs with IGCTs.

vinv = VS1 + VS2 + VS3

4. Switching and control strategy

The SFC-MLI pattern is produced by switching sequentially through the five modes. The redundant states have the advantage that they can be used to regulate capacitors voltage. In order to regulate the identify voltage level and then desired signals are directed to the switches considering DC-link capacitors voltages and redundant switching modes [48,49]. It is possible to define modulation function S(−2Vdc ) to S(2Vdc ) , for each of the switching modes (VM ), based on the following rules:

High frequency switching modulation techniques like level-shifted pulse width modulation and space vector modulation have been utilized to control the gating signals of multilevel inverters [47]. In this paper, the level-shifted carrier with same phase angle, magnitude, and frequency PWM are modulated. The level-shifted carrier signals are compared with the sinusoidal reference waveform to achieve the gating signals equivalent to particular voltage levels, as shown in Fig. 12. The number of shifted-levels carriers (Ncarrier ) can expressed by the following equation:

Ncarrier = vl − 1

(33)

⎧V−2vdc = − (vC1 + vC2)·S−2vdc ⎪V−vdc = − vCj·S−vdc ⎨Vvdc ⎪ ⎩V2vdc

(32)

Where vl is desired number of output voltage levels. The S1 is always conducting in mode 1, 3, 5, and 7 to generate the positive and zero voltage level, and in mode 2, 4, 6, and 8 the S2 conducts always to achieve the negative and zero voltage levels, as listed in Table 2, and 4. By using different voltage rating of switches in an inverter, the modulation technique is different for the multilevel inverter. Therefore, these center switches (S2 and S2 ) are controlled by low-frequency (or fundamental frequency), and rest of switches are controlled by high-frequency. For center high voltage switches, IGCT is better selection due to lower conduction losses. The upper and lower sides high frequency switches can be synthesize using commercially available half-bridge modules which are already optimize for high frequency application. The switching time transient can be further minimized by designing the whole module for minimum stray

= vCj·Svdc = (vC1 + vC2)·S2vdc

(34)

In MLIs, there are still technical issues which need to be improved, such as inverter current and DC-capacitors voltage [50]. The voltage unbalance problems will disturb the quality of the output voltage of the system. In some cases, this could lead to complete failure of the power inverter. In Fig. 14 shows the proposed control which controls the inverter current and capacitors voltage. The total capacitor voltage control is the first level control to regulate the DC voltages. To achieve the voltage regulation, the difference of capacitors voltage reference Vref with the average value of all the feedback DC-link capacitors voltage (VCj ) can apply to proportional and integral controller, as shown in Fig. 14. The capacitors voltage errors e v is define as:

VC1 + VC2 2

(35)

e v = Vref − VC.

(36)

VC =

where Vref is the jth capacitor reference voltage define in Eq. (14). The ∗ is achieved from the output of the instantaneous current reference iinv voltage regulator.

(

∗ iinv = e v k p1 + k i1

∫ dt ) cosθ

(37)

Fig. 15 shows two controllers which applied separately for confirming different transient states operations of the STATCOM. Fig. 15a shows reactive power controller. It applied when reactive power compensation is desired. If sudden change occur in reactive power at load ∗ terminal, the reactive power is estimated and fed to qgrid input of reactive power controller. Reactive power is compensate through

Fig. 12. Level shift carrier waveform with sinusoidal reference waveform. 9

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Fig. 14. Control block diagram. Fig. 15. Block diagrams of reactive current estimator.

system converge the expected stable equilibrium point. The bandwidth of the closed-loop PCC voltage control system is usually selected to be adequately smaller than that of the closed-loop current controllers, that is, 1/ τi . [51]. The iq∗ is calculated as:

Table 3 Swapping technique for balancing of capacitors. Pinv (iinv (iinv (iinv (iinv

× × × ×

vinv ) vinv ) vinv ) vinv )

> > < <

Caps. volt condition

Charging

< > > <

C1 C2 C2 C1

v C1 v C1 v C1 v C1

0 0 0 0

v C2 v C2 v C2 v C2

(

∗ iq∗ = ( vgrid − vgrid ) kp3 + ki3

Same polarity-FC Asymmetric

Output voltage levels Step size (n > 2 ) Switch voltage rating Control DC-capacitor voltage rating Inverter behaviour Redundant non-zero switching states Overall cost

Symmetric

High Very less Non-identical Asymmetric Complex Higher Subtractive No Higher

∗ ei = iinv − iq∗

Alternate polarity-FC Asymmetric

Less Identical Asymmetric Complex Easy High Low Additive No Yes

∗ vinv = ei ·k 4

(

∫ dt ).

(41)

here k 4 is current controller gain. The output of the current regulator is compared to level shifted carriers to generate the modulating signal. To equally charge and discharge capacitors voltages, the swapping technique is proposed. The swapping technique utilize redundant switching states, i.e., the ± v and 0 voltage levels can be achieved in several ways. The look up table can derive form the modification rule of the DC-link voltages listed in Table 3. Using these conditions, the ± Vdc states of the inverter output which can be redundantly selected is utilized to control the charging/ discharging of the capacitor without altering the level shifted PWM. Take an example, if the power of inverter Pinv is positive, C2 voltage is greater than C1 the mode 3 will be selected, the mode 5 will select if the VC1 is greater the VC2 .

Low

traditional PI compensator to converge error to reactive power reference ∗ qgrid value: ∗ iq∗ = (qgrid − qgrid ) kp2 + ki2

(40)

To ensure the convergence of output current to their reference value, proportional controller has been used:

Symmetric

Higher

High

(39)

The aim of the current loop control is to control the reactive power of the STATCOM and regulate the inverter current. The current control strategy design assumes that the capacitor voltage are regulated as established in Eq. (14). The output current error ei be defined as:

Table 4 Comparison of symmetric and asymmetric flying capacitor multilevel inverter. Feature

∫ dt ).

(38)

Fig. 15b shows point of common coupling (PCC) voltage controller for voltage regulation. The voltage at PCC is control by reactive power injection or absorbtion by the STATCOM. To increase the speed of convergence, proportional and integral control measure the grid voltage vgrid error and produce the reactive current reference iq∗ and make the

5. Comparative analysis In this section, a comparison of 10

SP-FC

and

AP-FC-MLIs

are discussed

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Fig. 16. Simulated waveforms when symmetric

AP-FC-MLI

was in steady state. (a) Seven-level asymmetric

Fig. 17. Simulated waveforms when

STATCOM

AP-FC

topology and (b) five-level symmetric

AP-FC

topology.

was in steady state.

Fig. 18. Simulation waveforms in a transient state from capacitive to inductive operation.

increase the number of floating capacitors the step-size will be not symmetric subsequently [18], the harmonics profile is not good. However, this is not practicable with more than two floating capacitors. As explained earlier in Section 2.1, same polarities FC inverter shows subtractive behavior. Due to this feature, the inverter requires higher voltage rating capacitors which leads to increase the cost and area of the inverter. The SP-FC multilevel inverters have no redundant switching states except zero voltage level, thats caused to increase the difficulty of DC-capacitors voltage balancing. Due to asymmetric structure of inverter, the circuit design is more complex [37,52].

briefly. In multilevel inverters, to increase the levels of output voltage essential to increase the number of floating capacitors. This may leads to increased the overall cost of inverter and need complex control algorithm to balance capacitor voltages. The same polarity FC-MLI topology was first modify FC topology to achieved greater output voltage levels by reducing the count of components of inverter [6]. The two possible combination according to capacitor voltage rating the symmetric SP-FC is impractical as mentioned in Section 2.1.2 and not discussed. The step-size of the output voltage levels is the identical on two floating capacitors of asymmetric SP-FC. To 11

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Fig. 19. Simulated waveforms confirming the effectiveness of the swapping technique.

Fig. 20. Simulated waveforms confirming the compensation effectiveness of load voltage control.

Fig. 21. Simulated waveforms confirming the dynamic behavior for inductive load compensation.

Fig. 22. Block diagram for simulating sag voltage.

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Fig. 23. Simulated waveforms of voltage sag conditions.

Fig. 24. Experimental prototype of

SFC-MLI.

redundant non-zero switching states are available. To overcome the above limitations of asymmetric AP-FC, symmetric AP-FC was proposed. The designing of the inverter is easy due to symmetrical structure and identical voltage rating of devices [34,42,36]. The symmetric AP-FC has the same switching and current stress, because similar voltages appears on both DC-link capacitors. Symmetric AP-FC-MLI has greater redundant switching states to achieve five-level voltage levels [6]. The redundant switching states (RSS) have a very significant

The AP-FC attract the attention because the summing up the output voltage due to alternate connection of DC-voltage sources. Therefore, higher voltage levels achieved by using of low voltage rating voltage sources. Furthermore, the AP-FC has the same step-size for any number of output voltage levels and more suitable to increase voltage levels by increasing the number of floating capacitors, may it reduce high-frequency switches. In fact, the designing of asymmetric AP-FC still complicated and difficult to control the DC-capacitors voltage because no 13

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Fig. 25. Experimental waveforms when

AP-SFC-MLI

Fig. 26. Experimental waveforms when

STATCOM

was in steady state.

was in steady state.

Fig. 27. Experimental waveforms in a transient state from capacitive to inductive operation.

Fig. 28. Experimental waveforms confirming the effectiveness of the total voltage control and swapping technique with capacitor voltage control.

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Fig. 29. Experimental waveforms confirming the dynamic behavior for reactive load compensation.

Fig. 30.

DC-link

link capacitor Cmj = 20, 000 μ F, and the sampling time period (Ts ) of 312.5 ms expresses a 3.2 kHz switching frequency. The single capacitor reference voltage in the simulation is equal to 100 V. The grid voltage (Vgrid ) is 110 Vp , and the series connected inductor (L) is 0.7 mH. At the start, no active and reactive power transfers between STATCOM and grid, and inverter operate in stand-alone mode. The steady-state simulated seven-level asymmetric AP-FC and five-level symmetric AP-FC output voltage waveform with the constant DC source (Vdc ) are shown in Fig. 16. The control of balancing DC-capacitor voltages is complex due to asymmetric voltage rating capacitors used in an asymmetric AP-FC inverter as discussed in Section 5. Therefore, symmetric voltage rating DCcapacitors AP-FC are simulated for STATCOM applications. The closed loops steady-state waveforms of the AP-SFC-MLI are investigated. Simulation has been carried out for the proposed system to investigate the steady state and dynamic response of the inverter capacitor voltages. The closed-loop steady state grid-connected output waveforms are shown in Fig. 17. To test the effectiveness and dynamic response of current loop control, initially, there is no-load connected to STATCOM and the reactive power reference is suddenly changed from fully capacitive to fully inductive modes. Fig. 18 shows the simulated waveforms of grid voltage vgrid , STATCOM voltage vinv , and STATCOM current iinv in a transient state. As it can be seen, the proposed control system is able to quickly follow the reactive power reference and the dynamic response is very fast. During the transient state, the whole system performs well with the five-level output voltage. Note that in the STATCOM current, a small degree of distortion exists as shown in Fig. 17 which becomes insignificant at higher values for output current as shown in Fig. 18. The next results confirm the performance of balancing of the DCcapacitors voltage. The behavior of DC-link capacitor voltage balancing technique under modulated signals with swapping algorithms is highlighted. Fig. 19 shows the capacitor voltages variations, with the balancing control deactivated at the beginning. After activating the voltage balancing control the DC-link voltages converged to a predefined reference value with a short transient. This emphasizes the performance of voltage balancing control. From the test results of Fig. 19, it can be clearly seen that voltage balancing methodology keeps the DC-link capacitor voltages constant at their reference value under reactive power change in current. The dynamic performance of the load voltage regulation is also tested. At the beginning of the simulation, no-load is connected while the STATCOM operates in a steady state mode shown in Fig. 20. After a short time period, the load is connected to PCC. It can be observed that the compensation precision of STATCOM is high and the dynamic response is fast. Fig. 21 shows the simulated waveforms for testing reactive power control. Initially, the STATCOM operates at steady state condition and no reactive power is transfer to the utility system. Reactive load 28.28 iL (RMS ) is applied at t = 40 ms at the point of common coupling (PCC). To achieve unity power factor at the load terminals, only STATCOM delivered

capacitor power loss.

Fig. 31. Efficiency of the proposed topology prototype.

role in control to balance and regulate the DC-link capacitor voltages. Because of RSS, the switching modes should be evaluated accurately to determine the path of charging and discharging for the capacitors [37]. It is noteworthy that addressing to aforementioned outstanding merits, the symmetric AP-FC-MLI has better efficiency with two floating capacitors, it is more practical for medium voltage/high power applications [34]. For sake of comparison all points discussed in this section have been summarized in Table 4. For this discussion it is evident that symmetric AP-FC can be feasible candidate for STATCOM applications. 6. Results and discussion 6.1. Simulation results In order to verify proposed idea, simulation tests were carried out. The simulation was run using MATLAB and Simulink for five-level SFC inverter connected to the grid. The simulation topology is based on Fig. 3b and the control loop is simulated according to Fig. 14. The DC15

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power losses of the IGBT. Efficiency profile at different power loads for the inverter is shown in Fig. 31. Power loss involved in the isolation transformer not included in the efficiency calculations.

reactive power to the load while grid contribution becomes zero. The simulated results of Fig. 21 shown that the proposed reactive power control technique rapidly and effectively compensates the reactive current in response to an abrupt change in the reactive power reference iq∗ signal. Finally, we consider the case study of proposed STATCOM for voltage regulation. The system under consideration is shown in Fig. 22. Two varying loads are connected to the 3 kV, the secondary side of the transformer. Switch 1 is used to control the inductive load of 0.7 pu and switch 2 control the connection of variable reactive load (0.7 pu) to the system with line impedance X = 0.1 pu. By closing switch 2, the STATCOM deliver reactive power to the system, and when switch 2 is opened, the STATCOM absorbs reactive power in order to restore the RMS voltage to the reference value. Fig. 23a shows the simulated waveforms to confirm the system operation characteristics under voltage sags without STATCOM. Initially, the load is increased suddenly increase reactive power. In this case, the voltage drops by almost 8% with respect to the reference value. After period of time the switch 2 is reopened and the line voltage again increased and equal to reference value. Fig. 23b shows the simulated waveforms of voltage sag condition with STATCOM. After closing switch 2, the line voltage drops for interval of time but it can compensate by STATCOM in short time. It is observed that the proposed control has mitigated voltage sag (caused by load variations) fairly well. The simulated results concluded that the predicted analysis and simulated results have good dynamic performance and maintain the DClink capacitor voltages constant under changing current conditions.

7. Conclusion In this paper, a comparison of newly developed reduced switches packed U-cell topologies are presented. A comprehensive comparison of same polarity (SP-FC) and alternate polarity (AP-FC) topologies was given, which prove that alternate polarity symmetric flying capacitor (AP-SFC) topology is well suited for grid connected application. The AP-SFC topology possesses extended capability remarkably and also allow the reverse current for inductive loads through existing power switches. This paper also presented the control algorithm to balance all capacitor voltages in an inverter. Moreover, the reduced switches, cost, and volume are notable features of the proposed multilevel inverter. Finally, to confirm the performance and effectiveness of the proposed AP-SFC topology and its control, several simulation and lab test results are presented. Acknowledgment This paper is partially supported by the National Science Foundation of China (61473183, 61521063, U1509211), and Changzhou Tianman Energy Technology, Changzhou, Jiangsu, P.R. China. Appendix A. Supplementary material Supplementary data associated with this article can be found, in the online version, at https://doi.org/10.1016/j.ijepes.2019.105430.

6.2. Experimental results An experimental prototype of the system based on the configurations in Fig. 3b and the control loop developed according to Fig. 14 was realized in the laboratory, as shown in Fig. 24. In order to investigate the performance of the proposed balancing control strategy and modulation method for five-levels symmetric AP-FC-MLI. The tests were conducted by using 100 V DC source voltages, 0.7 mH inductor, and 20, 000 μ F rating capacitors. To modulate the gate signals, the control board uses a combination of Texas Instruments floating point (digital signal controller) DSC TMS320C28346 and the Altera MAX II (EPM570) CPLD to provide comprehensive control and fast protection of the system. Fig. 25 shows the symmetric AP-FC-MLI output waveforms when no reactive power transferred to grid and inverter works as a stand alone. Fig. 26 shows the experimental results which highlights the closed loop voltage control performance under steady state balance condition of the grid-connected inverter. To validate the response of current loop control, reactive power is changed from full capacitive to full inductive in the experimental setup shown in Fig. 27. To investigate the capacitor balancing control, Fig. 28 shows the experimental waveforms of DC-capacitor voltages. As the current is reactive with 90° phase shift with the voltages, the current transfer is high near zero voltage, where become nearly zero at peak voltages, consequently the current is lower when both capacitor are conducting and higher when only one capacitor is conducting. Fig. 29 shows the experiment waveforms to confirms the compensation effectiveness when the reactive power change at load terminal. Initially, the STATCOM is under a steady-state condition After transient state the STATCOM start to deliver reactive power to load side with opposite direction. The experimental results conclude a good correlation with the simulation results. In Fig. 30 the DC-link capacitor losses is carried out. As shown in Fig. 30, the capacitor power loss is found to be less than 1%, in most cases it can negligible. The laboratory prototype efficiency of SFC-MLI for 8 kW is found to be 98.66% considering capacitor power loss, conduction and switching

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