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Experimental investigation of using thermoelectric cooling for computer chips
Journal of King Saud University – Engineering Sciences xxx (xxxx) xxx
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Original article
Experimental investigation of using thermoelectric cooling for computer chips Saleh Al-Shehri a,⇑, Hamed H. Saber b a b
Department of Computer Science and Engineering, Jubail University College, Royal Commission of Jubail and Yanbu, Jubail Industrial City 31961, Saudi Arabia Department of Mechanical Engineering, Jubail University College, Royal Commission of Jubail and Yanbu, Jubail Industrial City 31961, Saudi Arabia
a r t i c l e
i n f o
a b s t r a c t
Article history: Received 22 October 2018 Accepted 27 March 2019 Available online xxxx
Thermoelectric devices are currently being used in many industrial applications for cooling devices and generating electricity. This paper mainly focuses on using thermoelectric for cooling applications, specifically to cool down computer chips. In this study, experimental tests were conducted using a commercial thermoelectric module to investigate its capabilities for cooling hotspot in chip at different heat rates. Two experimental tests were conducted at steady-state condition to cool down hotspot with two different values of heat rates of 10.8 W and 12.1 W. The former heat rate represents the case of hotspot with low heat flux, whereas the latter represents the case of hotspot with high heat flux. The test results showed that at hotspot heat rate of 10.8 W, using thermoelectric current of 5.5 A has resulted in decreasing the hotspot temperature at open circuit condition (111.4 °C) by 54.0 °C. However, at hotspot heat rate of 12.1 W, using thermoelectric current of 6.0 A has resulted in decreasing the hotspot temperature at open circuit condition (138.8 °C) by 61.1 °C. The test results showed that the optimum electrical current at high heat rate was always greater than that at low heat rate. The results provided in this paper is a part of a research project that consists of a number of phases in which the ultimate goal is to develop a simple tool for designing self-cooling framework to cool down chip hotspot at different operating conditions with minimal increase in the overall power requirements. A case study for self-cooling framework is provided in this paper to demonstrate that the chip hotspot at a given operating condition can successfully be cooled at an acceptable temperature with no need for additional power requirements. Ó 2019 Production and hosting by Elsevier B.V. on behalf of King Saud University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
Keywords: Thermoelectric generator Thermoelectric cooler Computer chip Hotspots Seebeck effect Peltier effect
1. Introduction Thermoelectric (TE) technology is currently being used in many industrial and medical applications. One of the thermoelectric applications is to generate electrical power from different sources of thermal energy for both space and terrestrial applications. This is the case of Thermoelectric Generators (TEGs). In the field of waste heat recovery (e.g. wasted, heat in the combustion gases), specifically in automotive industry, thermoelectric devices are currently being used to generate electrical power that can be used to
⇑ Corresponding author. E-mail addresses: (H.H. Saber).
[email protected]
(S.
Al-Shehri),
[email protected]
Peer review under responsibility of King Saud University.
Production and hosting by Elsevier
operate some vehicle components/devices. This has resulted in increase in the gas mileage (GMZ Energy, 2018; Rajpoot et al., 2017; Stabler, 2018). In this application, the hot side of the TEG is heated by the wasted heat or engine coolant, and the cold side is cooled by the engine coolant or ambient air. Another type of thermoelectric applications is to convert electrical power to thermal energy for cooling applications. This is the case of Thermoelectric Coolers (TECs). Charge coupled device (CCD), microelectronic devices, laser diodes, portable picnic coolers and blood analyzers are some applications that use TECs (International Technology Road Map, 2004; Knickerbocker et al., 2002; Knickerbocker et al., 2008). As thermometric devices are static (i.e. no moving parts and therefore silent, reliable and scalable), they are quite attractive in many applications as they operate for long time while requiring less maintenance. As well, thermometric devices are used in a form of modules (each module consists of an array of TE unicouples connected in series), thus increasing the redundancy, relatability and sustainability when they are used in critical applications such as space applications (El-Genk and Saber, 2006a,b,c). Thermoelectric
https://doi.org/10.1016/j.jksues.2019.03.009 1018-3639/Ó 2019 Production and hosting by Elsevier B.V. on behalf of King Saud University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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S. Al-Shehri, H.H. Saber / Journal of King Saud University – Engineering Sciences xxx (xxxx) xxx
coolers are based on the Peltier effect, discovered in 1834, by which applying electrical current across two dissimilar materials can create a temperature difference. The Peltier effect is one of the three thermoelectric effects. The other two effects are known as the Seebeck effect and Thomson effect. The first effect is a junction phenomenon and the last two effects occur inside the thermoelectric materials (Perry and Green, 1984). A typical TE module is made of two thin ceramic plates with a series of Positive (P) and Negative (N) doped semiconductor material such as P- and N- Bismuth-Telluride, P- and N- SiliconGermanium, etc. The ceramic plates on both sides of the TE module act as electrical insulation. The N-type material has an excess of electrons, while the P-type material has a deficit of electrons. One P-type and one N-type make up a unicouple (Fig. 1). The figure-of-merit of P-type and N-type, ZT = a2 r T/k, is used to describe the efficiency of a TE material, where a is the Seebeck coefficient, r is the electrical conductivity, and k is the thermal conductivity. Within the TE module, the TE unicouples are connected electrically in series and thermally in parallel (Fig. 1). A TE module can contain one to several hundred unicouples. As the electrons move from the P-type material to the N-type material through an electrical connector, the electrons jump to a higher energy state absorbing thermal energy from the cold side. Continuing through the material lattice, the electrons flow from the N-type material to the P-type material through an electrical connector, dropping to a lower energy state and releasing energy as heat to the heat sink at the cold side. The heat generation in the modern chips is not uniform. This would cause the value of the heat flux at the hotspot location 2 to 5 times higher than the average heat flux (Viswanath et al., 2000; Prasher et al., 2005). As such, it is expected that the implementation of modern chips will bring severe thermal management challenges at the package level (Goplen and Sapatnekar, 2006). The severity of the thermal challenge in modern chips is due to the formation of hotspots, which occur on varying time and spatial scales. These hotspots, if not adequately cooled, would result in high temperature gradients. This would result in reducing the chip performance (Hamann et al., 2007). Many efforts are ongoing to develop new cooling systems to enhance the heat dissipation from the chips. One of these methods is to use efficient spreaders cooled by saturation or subcooled nucleate boiling of dielectric liquids, such as FC-72 and HFE-7100 (El-Genk et al., 2005,2007; El-Genk and Saber, 2008). The saturation temperatures of these liquids, at the atmospheric pressure, are 56 °C and 61 °C, which help maintain the chip temperatures below 85 °C. In this method, many studies have shown that the high heat transfer coefficient of the nucleate boiling of dielectric fluids resulted in reducing the non-uniformity of the chip surface temperature, hence decreasing the anticipated thermal stresses in it (El-Genk and Saber, 2008). Another method for enhancing heat dissipation from the computer chips is to use Phase Change
Fig. 1. Thermoelectric module having 7 14 TEU.
Materials (PCMs). Garimella (2006) has considered PCMs as a potential candidate for transient hotspot cooling of microelectronics. As PCM acts as a heat storage unit during the events of power flows, it can help in suppressing the increase in the transient junction temperature on the chip surface. Other methods for cooling computer chips include the use of microchannels, high-conductivity thermal interface materials, and TECs (Bar-Cohen and Wang, 2009; Chowdhury et al., 2009; Garimella et al., 2006). Furthermore, hybrid cooling systems including fluidic microchannels and TECs have also been explored for hotspot cooling (Green et al., 2009; Sahu et al., 2009). As indicated earlier, thermal stresses can be created in a device due to the non-uniformly of its temperature distribution. Cooling the entire chip using a cooling device that spreads the cooling effect on the entire chip surface may not decrease the thermal gradient created at hotspot locations or may overcool the rest of the chip surface (Snyder et al., 2006; Sullivan et al., 2012). However, the anticipated thermal stresses can be minimized in such device by developing a proper cooling system with the potential of reducing the non-uniformity of temperature distribution. Consequently, cooling hotspot locations separately to insure its highest temperature blow a certain temperature threshold would be a better choice. Since hotspots occur on varying temporal and spatial scales, such cooling methods should be scalable on demand and actively controlled to cool hotspots as necessary. One of the scalable candidates of the promising technology that can be used to develop cooling systems for computer chips is to use thermoelectric devices (e.g. see Green et al., 2009; Prasher et al., 2005; Viswanath et al., 2000). Chowdhury et al. (2009) developed TEC modules made of ultrathin (100 lm) Bi2Te3 based super-lattices and integrated these modules to the thermal spreader of the electronic package. These modules helped reduce the hotspot temperature up to 15 °C. For hotspot cooling in stacked chips with two dies using TECs, Redmond et al. (2013) have shown that the effect of thermal contact resistance between dies, inside the TEC module, and between TEC and thermal spreader has a significant effect on the overall performance of the TECs. Gupta et al. (2011) developed a model for a single TEC integrated with an electronic package in order to investigate the characteristics of the transient thermal behavior of hotspots under the TEC operation with different thermal contact resistance and electrical contact resistance inside a TEC module. Sullivan et al. (2012) developed a computational model to analyze the cooling of hotspots on a chip using nine Peltier coolers attached at the bottom side of the thermal spreader in both steady-state mode and transient mode. The current research direction in designing microelectronic devices is to minimize the size of the chip while increasing its clock speed at higher frequencies. This produces high power dissipation density and as well increases the chip temperature. As shown in the study by Shakouri and Zhang (2005), the temperature inside a chip can vary by 5 °C to 30 °C from one location to another. In a Compaq Alpha 21364 processor under executing a software load, Skadron et al. (2004) have shown that the temperature difference between the hotspot location and the other parts of the chip was 21 °C. This results in forming hotspots in chips. The high temperature in the chips can not only increase their failure rate but also reduce their performance. As such, thermal management plays an important role in designing computer chips. Due to their scalability, the optimized thermoelectric devices can be fabricated in various sizes with different cooling capacities. The scalability feature can be used to design thermoelectric devices of different sizes to cool down only the chip hotspot locations while leaving the other non-hotspot locations uncooled. This eventually would help minimize the non-uniformity of temperature distribution across the chip and hence reduce the anticipated thermal stresses. The
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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objective of this study is to conduct experimental tests using a commercial TE module at different operating conditions in order to investigate its potential capability for cooling chip hotspots at a temperature below certain threshold value. The work in the current research project consists of a number of phases that include experimental testing, and 3D numerical modeling and optimizations of cascaded and non-cascaded TECs and TEGs. By taking the opportunity of the non-uniformity of the temperature distribution on chip surface as indicated earlier, it is important to point out that the final goal of this research project is to develop a simple tool for designing self-cooling framework for cooling hotspots at different operating conditions with no need for external electrical power. In this self-cooling framework, the optimized cascaded and non-cascaded TEGs are installed on the cooler chip areas in order to harvest electrical power from the chip-wasted heat. On the other hand, the chip hotspot areas will be cooled by installing the optimized cascaded and non-cascaded TECs on these areas where the TECs will be powered by the harvested electrical power from the TEGs. A sample result will be provided in this paper to show that the harvested electrical power by the TEGs can be enough to power the TECs for given operating condition. The work presented in this paper, which is Phase I of the research project, is the first step toward a comprehensive solution for using thermoelectric devices for cooling fast computer chips with hotspots of different heat fluxes. 2. Experimental test setup and test procedure To demonstrate cooling hotspots at different heat fluxes, two experimental tests were conducted at steady-state condition with two values of heat rates of 10.8 W and 12.1 W. To distinguish between these two tests throughout this paper, unless otherwise specified, we refer to the test with the heat rate of 10.8 W as ‘‘low-heat rate test” and the test with the heat rate of 12.1 W as ‘‘high-heat rate test”. Because it was difficult to obtain detailed information about the current chip layouts and the hotpot locations from chip manufacturers, it was not possible to conduct these tests on a real chip at this stage. As such, the chip was mimicked by electrical heaters with different heat rates to emulate executing software loads. As indicated earlier, the temperature distribution in the computer chip is not uniform due to the existence of hotspot locations with high heat fluxes. To explore this issue, a schematic of the test assembly is shown in Fig. 2 in which the heat generation by the chip was mimicked using two electrical heaters, namely: (a) a ceramic heater of small size to mimic the chip hotspot, and (b) a polyimide flexible heater of large size to mimic the other part of the chip. Fig. 2 shows that a thermal spreader made of a thin sheet of aluminum of 60 mm 60 mm and 2 mm thick is attached to the bottom surfaces of the electrical heaters. The heat is removed
from the test assembly using a finned heat sink, which is attached to a mechanical fan as shown in Fig. 3a. In this phase of the research project, the aim is not to directly mimic the processor. Instead, the focus is on investigating the possibility to overcome the hotspot phenomena of different heat rates. Therefore, in the experimental setup, only one hotspot was mimicked using small ceramic heater having a maximum temperature of 800 °C (Fig. 3b). With this ceramic heater, it is possible in this study to create hotspots at high temperatures and then investigate the potential capability of using a thermoelectric cooler to reduce these temperatures at acceptable values (85 °C as provided by El-Genk et al. (2005, 2007), and El-Genk and Saber (2008)). The other part of the chip with low heat flux was mimicked using polyimide flexible heater having maximum temperature of 180 °C. As shown in Fig. 3c, this heater is large enough to represent the other area of the chip of low heat flux. Additionally, it was easier to install this heater due to its flexibly and as well insuring good thermal contact at the interface between the heater and the thermal spreader made of aluminum sheet. In this study, different electrical powers were provided to the ceramic heater and the polyimide flexible heater so as to generate appropriate heat rates that can approximately mimic: (a) the chip hotspot, and (b) the other chip part. In this paper, we refer to the other chip part of low heat flux (i.e. the polyimide flexible heater) as ‘‘background”. A commercial TE module (TEC1-12707) of 40 mm 40 mm and 5 mm thick was used in this study (Fig. 3d). This TE module was installed underneath the aluminum sheet as shown in Fig. 4c. Finally, a mechanical fan was attached to the finned heat sink as shown in Figs. 2 and 3a. To minimize the thermal contact resistance between the aluminum sheet, TE module and the heat sink (see Fig. 2), a highly conductive thermal paste (168 mm thick) having a thermal conductivity of 1.93 W/(m.K) was applied at the interfaces between these components as shown in Fig. 2 and Fig. 4a,b. For the thermal paste (168 mm thick), the thermal resistance at these interfaces is 8.7 10 5 m2.K/W. The temperatures at various locations were measured using K-type thermocouples. The thermocouple locations are shown in Fig. 5. To minimize the side heat losses, however, thermal insulation layers made of extruded polystyrene (XPS) having thermal conductivity of 0.03 W/(m.K) were used to insulate the whole test assembly (see Fig. 6). To insure that the ceramic heater and the polyimide flexible heater are thermally in good contact with the aluminum sheet, a
(a) Heat Sink Assembly
(b) Ceramic Heater
Maximum temperature = 800oC
(c) Polyimide Flexible Heater
(d) Thermoelectric Module
Maximum temperature = 180oC
Fig. 2. Schematic of side view of the test setup assembly.
Fig. 3. Different components of the test assembly.
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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Fig. 4. (a) and (b) show thermal paste on top of TE module, and (c) shows the TE module located underneath the aluminum sheet.
Fig. 5. Top view of the heaters that mimicked the computer chip and the locations of K-type thermocouples.
the hotspot area and cold area of the microprocessor. Whereas the thin aluminum sheet mimics the thermal spreader. In the electronic integrated circuit, the microprocessor is normally attached to the motherboard from one side while the other side is mechanically fastened with the thermal spreader to insure a good thermal contact at the microprocessor – thermal spreader interface. In this excremental setup, the electrical heaters that mimicked the microprocessor should also be in good thermal contact with the thermal spreader that was mimicked by the thin aluminum sheet. Subsequently, to hold the different components of the test assembly and as well insuring that the electrical heaters and the thermal spreader are in good contact, two concreate blocks (1.19 kg and 0.775 kg) were placed on the top layer of the XPS as shown Fig. 6. The tests were conducted with four (4) individual power supplies with a stand-alone controller for each to power the mechanical fan, the TE module, the polyimide flexible heater and the ceramic heater. In this case, the different test components as well as the operating conditions can easily be controlled independently. By applying different electrical powers to the power supply that is connected to the mechanical fan when using different shapes of finned heat sinks, other tests are currently being conducted in this research project to: Investigate the capabilities of using 24 customized TEGs and one TEC for cooling a hotspot, and Obtain the necessary experiment data to validate the 3-D dimensional model that was recently develop in this research project so that this model can be used with confidence to develop a simple tool for designing self-cooling frameworks for cooling chip hotspots at different operating conditions with no need for additional electrical power. With the test setup described in the previous section, two tests were conducted, namely: (a) low-heat rate test, and (b) high-heat rate test. The obtained test results are provided next. 4. Results and discussions This section discusses the test parameters and the obtained results of the low-heat rate test and high-rate test. 4.1. Low-heat rate test The test parameters for different power supplies in the low-heat rate test include the following:
Fig. 6. Thermal insulation (XPS) placements.
very thin layer with unmeasurable thickness of the same thermal paste that was used at the other interfaces was applied between the heaters and the aluminum sheet. Finally, the ceramic heater that represented the hotspot was fixed to the thermal spreader by a little quantity of super glue that was applied under the topright corner.
3. Testing at steady-state condition As indicated earlier, the ceramic heater and polyimide flexible heater with different generation rates would approximately mimic
The power supply connected to the polyimide flexible heater that mimics the part of the chip of low heat flux, called in this paper ‘‘background”: Voltage = 9.22 V, Current = 0.45 A (4.15 W). The power supply connected to the ceramic heater that mimics the chip hotspot: Voltage = 5.85 V, Current = 1.85 A (10.82 W). The power supply connected to the mechanical fan: Voltage = 10.0 V, Current = 0.23 A (2.3 W). In this test, the total heat rate that was applied on the aluminum sheet (to mimic the thermal spreader) was 14.97 W (4.15 W by the polyimide flexible heater and 10.82 W by the ceramic heater). These represented a background heat flux of 0.33 W/ cm2 and a hotspot heat flux of 10.82 W/cm2. For the power supply that is connected to the TE module, the electrical current was gradually increased from 0.0 A (open circuit condition) to 9.0 A with an incremental step of 0.5 A. For each specified electrical current, the voltage of the power supply was adjusted to obtain that current to within ±1%. In each current step,
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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the measured data was carefully monitored until the steady-state condition was achieved in which the change in the temperature measurements with time was within ±0.2 °C. There are three thermoelectric effects, namely: Seebeck effect, Peltier effect and Thomson effect. With these thermoelectric effects at a temperature gradient across the TE unicouple or module, electrical power can be generated. In this case, the TE unicouple or module is working in the electrical power generation mode (TEG). On the other hand, when an electrical voltage is applied across a TE unicouple or module, cooling or heating phenomena occurs. In this case, the TE unicouple or module is working in the cooling mode (TEC). As will be shown later, the harvested power from the chip-wasted heat by TEGs can be used to power a TEC for cooling a hotspot to an acceptable temperature with selfcooling framework. The effect of TE current on the temperatures at different locations for the case of low-heat rate is shown in Fig. 7. It is important to point-out that a continuous charge current through TE unicouple or module results in two competing effects, namely: Heat is absorbed from the hot junctions due to Peltier effect (QP). This amount of the absorbed heat is directly proportional to the Seebeck coefficients (a) of both P- and N- thermoelectric materials and the electrical current passing through the hot junctions. As such, for given thermoelectric materials, the absorbed heat rate increases with increasing the electrical current resulted in decreasing the hot junction temperatures. Heat generation due to Thomson effect (Qs) and Joule heating (QJ). The rate of heat generation due to Thomson effect depends mainly on the Seebeck coefficient of the thermoelectric materials with the temperature (Qs = 0 for the case of constant Seebeck coefficienta), and directly proportional to both the temperature gradient across the thermoelectric materials and the electrical current passing through the TE unicouple or module. Also, the rate of heat generation due to Joule heating depends on the electrical resistivity of different materials in the TE unicouple or module, and directly proportional to the square value of the electrical current passing through the TE unicouple or module. As such, for given thermoelectric materials, the total heat generation rate due to both Thomson effect and Joule heating increases with increasing the electrical current passing through the TE module, resulting in an increase in the junctions temperatures. Fig. 7 shows that the highest temperatures at different locations occurred at the open circuit condition (i.e. I = 0.0 at which no
Fig. 7. Effect of TE current on the temperatures at different locations for the case of hotspot heat rate of 10.82 W and background heat rate of 4.15 W.
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thermoelectric effects, Qs = QP = QJ = 0.0). At this condition, the heat transfer from the hot side to the cold side of the TE module is mainly by conduction. By applying electrical power to the TE module, the temperatures at different locations gradually decrease with increasing the TE electrical current, and eventually reach their lowest values at the optimum operating condition at which the TE current was approximately equal to 5.5 A (Fig. 7). For the electrical current less than or equal 5.5 A, the amount of heat rate absorbed at the hot junctions by Peltier effect overweighs the total heat generation rate due to both Thomson effect and Joule heating resulting in a decrease in these temperatures with increasing the electrical current. As shown in Fig. 7, a further increase in the TE current (i.e. I > 5.5 A) resulted in increasing the temperatures at different locations. This is because the total heat generation rate due to both Thomson effect and Joule heating overweighs the absorbed heat rate at the hot junctions by Peltier effect. Note that a high electrical current can cause the temperatures at different locations to be even higher than that at the open circuit condition. In this case, the operation of the TE module is no longer in the cooling mode (TEC) but it is in the heating mode called ‘‘Thermoelectric Heater (TEH)” such as the application of heat pumps which is not the focus of this study. As provided by El-Genk et al. (2005, 2007), and ElGenk and Saber (2008), the highest chip temperature should be maintained below 85 °C. Fig. 7 shows the thermoelectric electric current that corresponds to the hotspot temperature of 85 °C is 1.54 A. In this test, the operating range of the TE current to maintain the hotspot temperature from 85 °C to its lowest value (57.4 °C) is 1.54 A–5.5 A. For cooling computer chips using TEC, considerations must be given to identify the optimum electrical current at which the temperatures at different locations reach their lowest values. The question is ‘‘for a given TE module, does the value of the optimum electrical current change with the chip heat rate?” To answer this question, another experimental test was conducted at higher heat rate as provided and discussed next. 4.2. High-heat rate test The test parameters for different power supplies in the highheat rate test include the following: The power supply connected to the polyimide flexible heater (background): Voltage = 9.22 V, Current = 0.45 A (4.15 W). The input power to the polyimide flexible heater was kept the same as that in the case of low-heat rate test. The power supply connected to the ceramic heater (hotspot): Voltage = 6.25 V, Current = 1.93 A (12.06 W). The input power to the ceramic heater was 11.5% higher than that in the case of low-heat rate test. The power supply connected to the mechanical fan: Voltage = 10.0 V, Current = 0.23 A (2.3 W). The input power to the mechanical fan was kept the same as that in the case of lowheat rate test. In this test, the total heat rate that was applied on the aluminum sheet that mimicked the thermal spreader was 16.21 W (4.15 W by the polyimide flexible and 12.06 W by the ceramic heater). This represented a background heat flux of 0.33 W/cm2, which is the same as the previous test, and a hotspot heat flux of 12.06 W/ cm2. A similar test procedure as described in the case of low-heat rate test was also applied in this test, where the thermoelectric electrical current was gradually increased from 0.0 A (open circuit condition) to 9.0 A with a current incremental step of 0.5 A. In each step, the collected data was monitored until the steady-state con-
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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dition was achieved in which the changes in the temperatures at different locations with time were negligible. For the high-heat rate test, Fig. 8 shows the effect of TE current on the temperatures at different locations. As shown in this figure, the behavior of the change in these temperatures with the TE current in this test is quite similar to the case of the low-heat rate test. The lowest hotspot temperature in the high-heat rate test (77.7 °C) occurs at an optimum TE current of 6.0 A. Moreover, the TE current that corresponds to the hotspot temperature of 85.0 °C is 3.41 A (Fig. 8). As such, the operating range of the TE current to maintain the hotspot temperature from 85.0 °C to its lowest value is 3.41 A– 6.0 A. As shown in Fig. 7 for the whole range of TE current (0.0–9.0 A), the hotspot temperature for the high-heat rate test is higher than that for the low-heat rate test. Although the background heat rate was the same for both tests (4.15 W), the background temperature for the high-heat rate test was higher than that for the low-heat rate test due to the lateral heat transfer by conduction through the aluminum sheet of 2 mm thick (Fig. 8). Have had a thinner aluminum sheet (i.e. the lateral heat transfer by conduction through the aluminum sheet would be insignificant), the background temperature for both high- and low-heat rate tests would be approximately the same. At the open circuit condition, the hotspot temperatures for the high and low-heat rate tests were 138.8 °C and 111.4 °C, respectively. This represents an increase in the hotspot temperature by 27.4 K due to increasing the hotspot heat rate by 11.5%. Fig. 7 shows that the optimum electrical current for the highheat rate test (approximately 6.0 A) is higher than that for the low-heat rate test (approximately 5.5 A, see Fig. 8). This phenomenon is in agreement with the obtained results, to be published later, for using self-cooling framework for cooling processor hotspots. At the optimum operating conditions, the lowest hotspot temperatures were, respectively, 77.7 °C and 57.4 °C for the high- and low-heat rate tests. This represents an increase in the lowest hotspot temperature by 20.3 °C as a result of increasing the hotspot heat rate by 11.5%. The TE module that was used in this study was not similar to those used by other investigators. At the optimum load current for the TE module, large reductions in hotspot temperatures were achieved in this study compared to those of other related studies. For example, at the optimum electrical currents of 5.5 A and 6.0 A for the hotspot heat rates of 10.8 and 12.1 W, respectively, reductions of hotspot temperatures (i.e. the temperature difference for the hotspot between the case of open circuit condition and the case of optimum condition) by 54.0 °C and 61.1 °C, were achieved. However, hotspot temperature reductions by 5.6 °C, 6–7 °C and 10 °C
were achieved by Redmond et al. (2013), Gupta et al. (2011) and Sullivan et al. (2012), respectively. As such, it is important to operate the TE module at its optimum electrical current so as to achieve the highest reduction in the hotspot temperatures. As an initial step, this paper mainly focuses on investigating the highest reductions in the temperature at different locations as result of using thermoelectric cooler. As shown in Fig. 8, the highest temperature reductions in the background (represented by polyimide flexible heater to mimic the cold part of the chip) for low-heat rate test and high-heat rate test were 44.8 °C (from 51.1 °C to 6.3 °C) and 48.8 °C (from 57.3 °C to 8.5 °C), respectively. Fig. 7 shows that the highest corresponding reductions in the hotspot temperatures were 54.0 °C (from 111.4 °C to 57.4 °C) and 61.1 °C (from 138.8 °C to 77.7 °C). For a given TE current, using only one TE module to dissipate the heat from the two heaters (that mimicked the microprocessor/chip with one hotspot) at different heat rates has resulted in large differences at the surface temperatures of the heaters. For example, with an electrical current of 4.0 A in the case of lowheat rate test, the temperature difference between the hotspot (60.6 °C) and background (9.3 °C) was 51.3 °C. For the case of high-rate test with the same TE current (4 A), the temperature difference between the hotspot (81.3 °C) and background (11.5 °C) was 69.8 °C. It is important to point to that there is no issue for having a part of the chip at low temperature such as 10 °C or less as long as the highest temperature in the other parts not to exceed a certain temperature threshold. For a long chip lifetime, however, a proper cooling system is the one that simultaneously insures the highest chip temperature below certain temperature threshold (e.g. 85 °C) and a small temperature difference between the hot area and the cold area in order to minimize the thermal stress in the chip.
4.3. Self-cooling framework – Case study Most recently, a 3D numerical and optimization model was developed to investigate the capabilities of using non-cascaded and cascaded TE modules for cooling the hotspots in computer chips with minimal increase in the overall power requirements when these modules were used in the cooling mode (TECs) and electrical power generation mode (TEGs). As indicated earlier, the current research project consists of a number of phases in which the ultimate goal of this project is to develop a simple tool that can be used for designing self-cooling frameworks for cooling hotspots at different operating conditions. Currently, a number of small TE modules are being used in the same experimental setup of this paper as following: (1) One (1) TEC is installed on the hot area to cool down a hotspot having different heat rates. (2) Twenty-four (24) TEGs are installed on the cold area to generate electrical power. (3) The generated electrical power by the TEGs is used to power the TEC.
Fig. 8. Effect of TE current on the temperatures at different locations for the case of hotspots heat rate of 12.06 W and background heat rate of 4.15 W.
As an example for a self-cooling framework, to demonstrate whether the harvested electrical power by TEGs can be enough to power TECs for a given chip operating condition, the 3-D model developed in this research project was used in this study to conduct a case study with 5 5 TE modules as shown in Fig. 9. The size of each module is 3 mm 3 mm and consists of 7 14 unicouples having dimensions and material properties as provided in Table 1. In this case study, the bottom surfaces of the TEC and TEGs are attached to heat sink surface at temperature of 40 °C (Fig. 9a, b). This case study was conducted for a chip size of
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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Fig. 9. Schematics of 15 mm 15 mm computer chip with the attached 3 mm 3 mm TEC and TEGs, and temperature distribution (in oC) of the chip surface.
15 mm 15 mm having a total heat generation rate of 140 W, which is distributed as following: A part of the chip area of 3 mm 3 mm has a hotspot having heat generation rate of 20 W. This heat generation rate corresponds to a heat flux of 222.2 W/cm2. A 3 mm 3 mm TEC was placed on the hotspot as shown in Fig. 9b. The other chip areas have a heat generation rate of 120 W (5 W for each area of 3 mm 3 mm). The heat generation rate of each area (24 areas in total) corresponds to a heat flux of 55.6 W/cm2. As shown in Fig. 9b, 24 TEGs are placed on these areas. The heat generation rate in modern computer chips is nonuniform where the peak-to-average heat flux ratio can vary from 2 to 5 (Snyder et al., 2006; El-Genk and Saber, 2008). In this case
study, with the peak heat flux of 222.2 W/cm2 and average heat flux of 62.2 W/cm2, the ratio of the heat flux of the hotspot area to that of all areas of the chip is 3.6. As a constrain for the maximum temperature on the chip surface to be less than or equal 85 °C (El-Genk et al. 2005, 2007); El-Genk and Saber, 2008), numerical simulation was conducted to determine the maximum amount of the harvested electrical power by the TEGs that is needed to power the TEC so as to fulfil this constraint. In this case study when the 24 TEGs were connected in series, the obtained maximum amount of the harvested electrical power by the TEGs was 1.63 W. When the maximum amount of the harvested electrical power by the 24 TEGs (1.63 W) was used to power the TEC, this case is referred in this paper as ‘‘TEC-TEGs ON”. In this case, Fig. 9c shows the temperature distribution of the entire chip surface. As shown in this figure, the maximum hotspot temperature (73.6 °C) was less
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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Table 1 Material properties and thickness of different materials used in TE module. Part* Material
P-Legs** P-Bi2Te3
N-Legs** N-Bi2Te3
Electrical Conductors Copper
Electrical Insulators Ceramic
a r q
301 9.259E + 04 7700 154 1.2 48
301 9.259E + 04 7700 154 1.2 48
— 5.988E + 07 8960 385 400 46
— — 17,800 132 1.75 12.5
Cp k d
* a = Seebeck coefficient (mV/K), r = electrical conductivity (S/m), q = density (kg/m3), Cp = specific heat capacity (J/kg.K), k = thermal conductivity (W/m.K), d = Thickness (lm). ** Cross-section area = 198.21 lm 198.21 lm and spacing between the P- and N-legs, called pitch = 15 lm.
than 85.0 °C. As well, the average temperature on the entire chip surface was 61.7 °C (Fig. 9c). As such, the harvested electrical power by the TEGs was enough to power the TEC for cooling the hotspot and satisfying the constraint above at no additional electrical power requirement. It is important to point out that the temperature difference between the maximum hotspot temperature and the average hotspot temperature (70.6 °C) was only 3.0 °C. Consequently, using a self-cooling framework can result in reducing the non-uniformity in the chip temperature distribution. As indicated earlier, designing a cooling system that minimizes the non-uniformity of the temperature distribution in the computer chip can greatly contribute in reducing the anticipated thermal stresses inside the chip. To show the significance of using the maximum amount of the harvested electrical power by the 24 TEGs to power the TEC in the case ‘‘TEC-TEGs ON”, another numerical simulation was conducted for the case of open circuit condition for both the TEC and the 24 TEGs. This case is referred in this paper as ‘‘TEC-TEGs OFF”. In this case, Fig. 9d shows the temperature distribution of the entire chip surface. As shown in this figure, the highest value of the chip surface temperature was 158.0 °C. In this case, the average surface temperature of the hotspot was 142.9 °C, while the average surface temperature of the entire chip was 74.1 °C. Powering the TEC by the harvested power by the 24 TEGs (1.63 W), however, has resulted in: Reducing the highest chip surface temperature by 84.4 °C (from 158.0 °C in the case ‘‘TEC-TEGs OFF” to 73.6 °C in the case ‘‘TECTEGs ON”), and Reducing the average hotspot temperature by 72.3 °C (from 142.9 °C in the case ‘‘TEC-TEGs OFF” to 70.6 °C in the case ‘‘TEC-TEGs ON”). Last but not the least, as shown in Fig. 9c and d, unlike the case ‘‘TEC-TEGs OFF”, the hotspot location in the case ‘‘TEC-TEGs ON” was approximately disappeared from the chip surface. In summary, the novelty of the approach described above by using selfcooling framework for cooling computer chips has resulted in: (1) Reducing the non-uniformity of the temperature distribution on the chip surface, and hence help minimize the anticipated thermal stresses in the chip, and (2) Decreasing the power requirements for cooling computer chips using thermoelectric devices. No additional electrical power was needed in the demonstrated case above to maintain the hotspot temperature below 85 °C.
low-heat rate test and 12.1 W for the high-heat rate test) were conducted at steady-state condition in which an aluminum sheet was used to mimic the thermal spreader and heated by ceramic heater to create a hotspot, and polyimide flexible heater to provide the background heat rate. The two electrical heaters were used to mimic the microprocessor/chip. A commercial TE module attached to heat sink and mechanical fan was used to cool down the aluminum sheet at different thermoelectric electrical currents. The results of the low-heat rate test showed that the hotspot temperature at open circuit condition (111.4 °C) can be decreased to 57.4 °C at the optimum electrical current of 5.5 A, which represented a reduction in the hotspot temperature by 54.0 °C (or by 94%). For high-heat rate test, results showed that the hotspot temperature at open circuit condition (138.8 °C) can be decreased to 77.7 °C at the optimum electrical current of 6.0 A, which represented a reduction in the hotspot temperature by 61.1 °C (or by 79%). The optimum TE current for the high-heat rate test was greater than that for the low-heat rate test. This phenomenon is in agreement with other related studies. The work presented in this study is a part of a research project that consists of a number of phases including experimental testing, and 3D numerical modeling and optimizations of cascaded and non-cascaded thermoelectric coolers (TECs) and cascaded and non-cascaded thermoelectric generators (TEGs). The ultimate goal of this project is to develop a simple tool for designing self-cooling framework for cooling chip hotspots at different operating conditions with minimal increase in the overall power requirements. In this self-cooling framework, cascaded and non-cascaded TEGs are installed on the cooler chip areas in order to harvest electrical power from the chip-wasted heat. Whereas the chip hotspot areas are cooled using cascaded and non-cascaded TECs that are powered by the harvested electrical power from the TEGs. For a given chip operating condition, a case study was conducted in this paper to demonstrate whether or not the harvested electrical power by the TEGs is enough to power a TEC located on a hotpot. The results showed that the harvested electrical power by the TEGs was not only enough to power the TEC but also insuring the hotspot temperature remains below a certain temperature threshold (85 °C). As well, with the self-cooling framework, the location of the hotspot was approximately disappeared from the chip surface with no requirement for additional electrical power. More results about developing self-cooling framework for cooling chip hotspots at different operating conditions with cascaded and non-cascaded TEGs and TECs will be published later.
Acknowledgments 5. Summary and conclusions Experimental tests were conducted to investigate the potential capabilities of TE technology to cool down chip hotpots at different heat rates. In this study, two experimental tests (10.8 W for the
This research was funded by the Colleges and Institutes Sector (CIS) at the Royal Commission for Jubail & Yanbu, Kingdom of Saudi Arabia. The authors would like to thank Professor Wahid Maref from University of Quebec for his technical support.
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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Original article
Experimental investigation of using thermoelectric cooling for computer chips Saleh Al-Shehri a,⇑, Hamed H. Saber b a b
Department of Computer Science and Engineering, Jubail University College, Royal Commission of Jubail and Yanbu, Jubail Industrial City 31961, Saudi Arabia Department of Mechanical Engineering, Jubail University College, Royal Commission of Jubail and Yanbu, Jubail Industrial City 31961, Saudi Arabia
a r t i c l e
i n f o
a b s t r a c t
Article history: Received 22 October 2018 Accepted 27 March 2019 Available online xxxx
Thermoelectric devices are currently being used in many industrial applications for cooling devices and generating electricity. This paper mainly focuses on using thermoelectric for cooling applications, specifically to cool down computer chips. In this study, experimental tests were conducted using a commercial thermoelectric module to investigate its capabilities for cooling hotspot in chip at different heat rates. Two experimental tests were conducted at steady-state condition to cool down hotspot with two different values of heat rates of 10.8 W and 12.1 W. The former heat rate represents the case of hotspot with low heat flux, whereas the latter represents the case of hotspot with high heat flux. The test results showed that at hotspot heat rate of 10.8 W, using thermoelectric current of 5.5 A has resulted in decreasing the hotspot temperature at open circuit condition (111.4 °C) by 54.0 °C. However, at hotspot heat rate of 12.1 W, using thermoelectric current of 6.0 A has resulted in decreasing the hotspot temperature at open circuit condition (138.8 °C) by 61.1 °C. The test results showed that the optimum electrical current at high heat rate was always greater than that at low heat rate. The results provided in this paper is a part of a research project that consists of a number of phases in which the ultimate goal is to develop a simple tool for designing self-cooling framework to cool down chip hotspot at different operating conditions with minimal increase in the overall power requirements. A case study for self-cooling framework is provided in this paper to demonstrate that the chip hotspot at a given operating condition can successfully be cooled at an acceptable temperature with no need for additional power requirements. Ó 2019 Production and hosting by Elsevier B.V. on behalf of King Saud University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
Keywords: Thermoelectric generator Thermoelectric cooler Computer chip Hotspots Seebeck effect Peltier effect
1. Introduction Thermoelectric (TE) technology is currently being used in many industrial and medical applications. One of the thermoelectric applications is to generate electrical power from different sources of thermal energy for both space and terrestrial applications. This is the case of Thermoelectric Generators (TEGs). In the field of waste heat recovery (e.g. wasted, heat in the combustion gases), specifically in automotive industry, thermoelectric devices are currently being used to generate electrical power that can be used to
⇑ Corresponding author. E-mail addresses: (H.H. Saber).
[email protected]
(S.
Al-Shehri),
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operate some vehicle components/devices. This has resulted in increase in the gas mileage (GMZ Energy, 2018; Rajpoot et al., 2017; Stabler, 2018). In this application, the hot side of the TEG is heated by the wasted heat or engine coolant, and the cold side is cooled by the engine coolant or ambient air. Another type of thermoelectric applications is to convert electrical power to thermal energy for cooling applications. This is the case of Thermoelectric Coolers (TECs). Charge coupled device (CCD), microelectronic devices, laser diodes, portable picnic coolers and blood analyzers are some applications that use TECs (International Technology Road Map, 2004; Knickerbocker et al., 2002; Knickerbocker et al., 2008). As thermometric devices are static (i.e. no moving parts and therefore silent, reliable and scalable), they are quite attractive in many applications as they operate for long time while requiring less maintenance. As well, thermometric devices are used in a form of modules (each module consists of an array of TE unicouples connected in series), thus increasing the redundancy, relatability and sustainability when they are used in critical applications such as space applications (El-Genk and Saber, 2006a,b,c). Thermoelectric
https://doi.org/10.1016/j.jksues.2019.03.009 1018-3639/Ó 2019 Production and hosting by Elsevier B.V. on behalf of King Saud University. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/).
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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S. Al-Shehri, H.H. Saber / Journal of King Saud University – Engineering Sciences xxx (xxxx) xxx
coolers are based on the Peltier effect, discovered in 1834, by which applying electrical current across two dissimilar materials can create a temperature difference. The Peltier effect is one of the three thermoelectric effects. The other two effects are known as the Seebeck effect and Thomson effect. The first effect is a junction phenomenon and the last two effects occur inside the thermoelectric materials (Perry and Green, 1984). A typical TE module is made of two thin ceramic plates with a series of Positive (P) and Negative (N) doped semiconductor material such as P- and N- Bismuth-Telluride, P- and N- SiliconGermanium, etc. The ceramic plates on both sides of the TE module act as electrical insulation. The N-type material has an excess of electrons, while the P-type material has a deficit of electrons. One P-type and one N-type make up a unicouple (Fig. 1). The figure-of-merit of P-type and N-type, ZT = a2 r T/k, is used to describe the efficiency of a TE material, where a is the Seebeck coefficient, r is the electrical conductivity, and k is the thermal conductivity. Within the TE module, the TE unicouples are connected electrically in series and thermally in parallel (Fig. 1). A TE module can contain one to several hundred unicouples. As the electrons move from the P-type material to the N-type material through an electrical connector, the electrons jump to a higher energy state absorbing thermal energy from the cold side. Continuing through the material lattice, the electrons flow from the N-type material to the P-type material through an electrical connector, dropping to a lower energy state and releasing energy as heat to the heat sink at the cold side. The heat generation in the modern chips is not uniform. This would cause the value of the heat flux at the hotspot location 2 to 5 times higher than the average heat flux (Viswanath et al., 2000; Prasher et al., 2005). As such, it is expected that the implementation of modern chips will bring severe thermal management challenges at the package level (Goplen and Sapatnekar, 2006). The severity of the thermal challenge in modern chips is due to the formation of hotspots, which occur on varying time and spatial scales. These hotspots, if not adequately cooled, would result in high temperature gradients. This would result in reducing the chip performance (Hamann et al., 2007). Many efforts are ongoing to develop new cooling systems to enhance the heat dissipation from the chips. One of these methods is to use efficient spreaders cooled by saturation or subcooled nucleate boiling of dielectric liquids, such as FC-72 and HFE-7100 (El-Genk et al., 2005,2007; El-Genk and Saber, 2008). The saturation temperatures of these liquids, at the atmospheric pressure, are 56 °C and 61 °C, which help maintain the chip temperatures below 85 °C. In this method, many studies have shown that the high heat transfer coefficient of the nucleate boiling of dielectric fluids resulted in reducing the non-uniformity of the chip surface temperature, hence decreasing the anticipated thermal stresses in it (El-Genk and Saber, 2008). Another method for enhancing heat dissipation from the computer chips is to use Phase Change
Fig. 1. Thermoelectric module having 7 14 TEU.
Materials (PCMs). Garimella (2006) has considered PCMs as a potential candidate for transient hotspot cooling of microelectronics. As PCM acts as a heat storage unit during the events of power flows, it can help in suppressing the increase in the transient junction temperature on the chip surface. Other methods for cooling computer chips include the use of microchannels, high-conductivity thermal interface materials, and TECs (Bar-Cohen and Wang, 2009; Chowdhury et al., 2009; Garimella et al., 2006). Furthermore, hybrid cooling systems including fluidic microchannels and TECs have also been explored for hotspot cooling (Green et al., 2009; Sahu et al., 2009). As indicated earlier, thermal stresses can be created in a device due to the non-uniformly of its temperature distribution. Cooling the entire chip using a cooling device that spreads the cooling effect on the entire chip surface may not decrease the thermal gradient created at hotspot locations or may overcool the rest of the chip surface (Snyder et al., 2006; Sullivan et al., 2012). However, the anticipated thermal stresses can be minimized in such device by developing a proper cooling system with the potential of reducing the non-uniformity of temperature distribution. Consequently, cooling hotspot locations separately to insure its highest temperature blow a certain temperature threshold would be a better choice. Since hotspots occur on varying temporal and spatial scales, such cooling methods should be scalable on demand and actively controlled to cool hotspots as necessary. One of the scalable candidates of the promising technology that can be used to develop cooling systems for computer chips is to use thermoelectric devices (e.g. see Green et al., 2009; Prasher et al., 2005; Viswanath et al., 2000). Chowdhury et al. (2009) developed TEC modules made of ultrathin (100 lm) Bi2Te3 based super-lattices and integrated these modules to the thermal spreader of the electronic package. These modules helped reduce the hotspot temperature up to 15 °C. For hotspot cooling in stacked chips with two dies using TECs, Redmond et al. (2013) have shown that the effect of thermal contact resistance between dies, inside the TEC module, and between TEC and thermal spreader has a significant effect on the overall performance of the TECs. Gupta et al. (2011) developed a model for a single TEC integrated with an electronic package in order to investigate the characteristics of the transient thermal behavior of hotspots under the TEC operation with different thermal contact resistance and electrical contact resistance inside a TEC module. Sullivan et al. (2012) developed a computational model to analyze the cooling of hotspots on a chip using nine Peltier coolers attached at the bottom side of the thermal spreader in both steady-state mode and transient mode. The current research direction in designing microelectronic devices is to minimize the size of the chip while increasing its clock speed at higher frequencies. This produces high power dissipation density and as well increases the chip temperature. As shown in the study by Shakouri and Zhang (2005), the temperature inside a chip can vary by 5 °C to 30 °C from one location to another. In a Compaq Alpha 21364 processor under executing a software load, Skadron et al. (2004) have shown that the temperature difference between the hotspot location and the other parts of the chip was 21 °C. This results in forming hotspots in chips. The high temperature in the chips can not only increase their failure rate but also reduce their performance. As such, thermal management plays an important role in designing computer chips. Due to their scalability, the optimized thermoelectric devices can be fabricated in various sizes with different cooling capacities. The scalability feature can be used to design thermoelectric devices of different sizes to cool down only the chip hotspot locations while leaving the other non-hotspot locations uncooled. This eventually would help minimize the non-uniformity of temperature distribution across the chip and hence reduce the anticipated thermal stresses. The
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objective of this study is to conduct experimental tests using a commercial TE module at different operating conditions in order to investigate its potential capability for cooling chip hotspots at a temperature below certain threshold value. The work in the current research project consists of a number of phases that include experimental testing, and 3D numerical modeling and optimizations of cascaded and non-cascaded TECs and TEGs. By taking the opportunity of the non-uniformity of the temperature distribution on chip surface as indicated earlier, it is important to point out that the final goal of this research project is to develop a simple tool for designing self-cooling framework for cooling hotspots at different operating conditions with no need for external electrical power. In this self-cooling framework, the optimized cascaded and non-cascaded TEGs are installed on the cooler chip areas in order to harvest electrical power from the chip-wasted heat. On the other hand, the chip hotspot areas will be cooled by installing the optimized cascaded and non-cascaded TECs on these areas where the TECs will be powered by the harvested electrical power from the TEGs. A sample result will be provided in this paper to show that the harvested electrical power by the TEGs can be enough to power the TECs for given operating condition. The work presented in this paper, which is Phase I of the research project, is the first step toward a comprehensive solution for using thermoelectric devices for cooling fast computer chips with hotspots of different heat fluxes. 2. Experimental test setup and test procedure To demonstrate cooling hotspots at different heat fluxes, two experimental tests were conducted at steady-state condition with two values of heat rates of 10.8 W and 12.1 W. To distinguish between these two tests throughout this paper, unless otherwise specified, we refer to the test with the heat rate of 10.8 W as ‘‘low-heat rate test” and the test with the heat rate of 12.1 W as ‘‘high-heat rate test”. Because it was difficult to obtain detailed information about the current chip layouts and the hotpot locations from chip manufacturers, it was not possible to conduct these tests on a real chip at this stage. As such, the chip was mimicked by electrical heaters with different heat rates to emulate executing software loads. As indicated earlier, the temperature distribution in the computer chip is not uniform due to the existence of hotspot locations with high heat fluxes. To explore this issue, a schematic of the test assembly is shown in Fig. 2 in which the heat generation by the chip was mimicked using two electrical heaters, namely: (a) a ceramic heater of small size to mimic the chip hotspot, and (b) a polyimide flexible heater of large size to mimic the other part of the chip. Fig. 2 shows that a thermal spreader made of a thin sheet of aluminum of 60 mm 60 mm and 2 mm thick is attached to the bottom surfaces of the electrical heaters. The heat is removed
from the test assembly using a finned heat sink, which is attached to a mechanical fan as shown in Fig. 3a. In this phase of the research project, the aim is not to directly mimic the processor. Instead, the focus is on investigating the possibility to overcome the hotspot phenomena of different heat rates. Therefore, in the experimental setup, only one hotspot was mimicked using small ceramic heater having a maximum temperature of 800 °C (Fig. 3b). With this ceramic heater, it is possible in this study to create hotspots at high temperatures and then investigate the potential capability of using a thermoelectric cooler to reduce these temperatures at acceptable values (85 °C as provided by El-Genk et al. (2005, 2007), and El-Genk and Saber (2008)). The other part of the chip with low heat flux was mimicked using polyimide flexible heater having maximum temperature of 180 °C. As shown in Fig. 3c, this heater is large enough to represent the other area of the chip of low heat flux. Additionally, it was easier to install this heater due to its flexibly and as well insuring good thermal contact at the interface between the heater and the thermal spreader made of aluminum sheet. In this study, different electrical powers were provided to the ceramic heater and the polyimide flexible heater so as to generate appropriate heat rates that can approximately mimic: (a) the chip hotspot, and (b) the other chip part. In this paper, we refer to the other chip part of low heat flux (i.e. the polyimide flexible heater) as ‘‘background”. A commercial TE module (TEC1-12707) of 40 mm 40 mm and 5 mm thick was used in this study (Fig. 3d). This TE module was installed underneath the aluminum sheet as shown in Fig. 4c. Finally, a mechanical fan was attached to the finned heat sink as shown in Figs. 2 and 3a. To minimize the thermal contact resistance between the aluminum sheet, TE module and the heat sink (see Fig. 2), a highly conductive thermal paste (168 mm thick) having a thermal conductivity of 1.93 W/(m.K) was applied at the interfaces between these components as shown in Fig. 2 and Fig. 4a,b. For the thermal paste (168 mm thick), the thermal resistance at these interfaces is 8.7 10 5 m2.K/W. The temperatures at various locations were measured using K-type thermocouples. The thermocouple locations are shown in Fig. 5. To minimize the side heat losses, however, thermal insulation layers made of extruded polystyrene (XPS) having thermal conductivity of 0.03 W/(m.K) were used to insulate the whole test assembly (see Fig. 6). To insure that the ceramic heater and the polyimide flexible heater are thermally in good contact with the aluminum sheet, a
(a) Heat Sink Assembly
(b) Ceramic Heater
Maximum temperature = 800oC
(c) Polyimide Flexible Heater
(d) Thermoelectric Module
Maximum temperature = 180oC
Fig. 2. Schematic of side view of the test setup assembly.
Fig. 3. Different components of the test assembly.
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Fig. 4. (a) and (b) show thermal paste on top of TE module, and (c) shows the TE module located underneath the aluminum sheet.
Fig. 5. Top view of the heaters that mimicked the computer chip and the locations of K-type thermocouples.
the hotspot area and cold area of the microprocessor. Whereas the thin aluminum sheet mimics the thermal spreader. In the electronic integrated circuit, the microprocessor is normally attached to the motherboard from one side while the other side is mechanically fastened with the thermal spreader to insure a good thermal contact at the microprocessor – thermal spreader interface. In this excremental setup, the electrical heaters that mimicked the microprocessor should also be in good thermal contact with the thermal spreader that was mimicked by the thin aluminum sheet. Subsequently, to hold the different components of the test assembly and as well insuring that the electrical heaters and the thermal spreader are in good contact, two concreate blocks (1.19 kg and 0.775 kg) were placed on the top layer of the XPS as shown Fig. 6. The tests were conducted with four (4) individual power supplies with a stand-alone controller for each to power the mechanical fan, the TE module, the polyimide flexible heater and the ceramic heater. In this case, the different test components as well as the operating conditions can easily be controlled independently. By applying different electrical powers to the power supply that is connected to the mechanical fan when using different shapes of finned heat sinks, other tests are currently being conducted in this research project to: Investigate the capabilities of using 24 customized TEGs and one TEC for cooling a hotspot, and Obtain the necessary experiment data to validate the 3-D dimensional model that was recently develop in this research project so that this model can be used with confidence to develop a simple tool for designing self-cooling frameworks for cooling chip hotspots at different operating conditions with no need for additional electrical power. With the test setup described in the previous section, two tests were conducted, namely: (a) low-heat rate test, and (b) high-heat rate test. The obtained test results are provided next. 4. Results and discussions This section discusses the test parameters and the obtained results of the low-heat rate test and high-rate test. 4.1. Low-heat rate test The test parameters for different power supplies in the low-heat rate test include the following:
Fig. 6. Thermal insulation (XPS) placements.
very thin layer with unmeasurable thickness of the same thermal paste that was used at the other interfaces was applied between the heaters and the aluminum sheet. Finally, the ceramic heater that represented the hotspot was fixed to the thermal spreader by a little quantity of super glue that was applied under the topright corner.
3. Testing at steady-state condition As indicated earlier, the ceramic heater and polyimide flexible heater with different generation rates would approximately mimic
The power supply connected to the polyimide flexible heater that mimics the part of the chip of low heat flux, called in this paper ‘‘background”: Voltage = 9.22 V, Current = 0.45 A (4.15 W). The power supply connected to the ceramic heater that mimics the chip hotspot: Voltage = 5.85 V, Current = 1.85 A (10.82 W). The power supply connected to the mechanical fan: Voltage = 10.0 V, Current = 0.23 A (2.3 W). In this test, the total heat rate that was applied on the aluminum sheet (to mimic the thermal spreader) was 14.97 W (4.15 W by the polyimide flexible heater and 10.82 W by the ceramic heater). These represented a background heat flux of 0.33 W/ cm2 and a hotspot heat flux of 10.82 W/cm2. For the power supply that is connected to the TE module, the electrical current was gradually increased from 0.0 A (open circuit condition) to 9.0 A with an incremental step of 0.5 A. For each specified electrical current, the voltage of the power supply was adjusted to obtain that current to within ±1%. In each current step,
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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the measured data was carefully monitored until the steady-state condition was achieved in which the change in the temperature measurements with time was within ±0.2 °C. There are three thermoelectric effects, namely: Seebeck effect, Peltier effect and Thomson effect. With these thermoelectric effects at a temperature gradient across the TE unicouple or module, electrical power can be generated. In this case, the TE unicouple or module is working in the electrical power generation mode (TEG). On the other hand, when an electrical voltage is applied across a TE unicouple or module, cooling or heating phenomena occurs. In this case, the TE unicouple or module is working in the cooling mode (TEC). As will be shown later, the harvested power from the chip-wasted heat by TEGs can be used to power a TEC for cooling a hotspot to an acceptable temperature with selfcooling framework. The effect of TE current on the temperatures at different locations for the case of low-heat rate is shown in Fig. 7. It is important to point-out that a continuous charge current through TE unicouple or module results in two competing effects, namely: Heat is absorbed from the hot junctions due to Peltier effect (QP). This amount of the absorbed heat is directly proportional to the Seebeck coefficients (a) of both P- and N- thermoelectric materials and the electrical current passing through the hot junctions. As such, for given thermoelectric materials, the absorbed heat rate increases with increasing the electrical current resulted in decreasing the hot junction temperatures. Heat generation due to Thomson effect (Qs) and Joule heating (QJ). The rate of heat generation due to Thomson effect depends mainly on the Seebeck coefficient of the thermoelectric materials with the temperature (Qs = 0 for the case of constant Seebeck coefficienta), and directly proportional to both the temperature gradient across the thermoelectric materials and the electrical current passing through the TE unicouple or module. Also, the rate of heat generation due to Joule heating depends on the electrical resistivity of different materials in the TE unicouple or module, and directly proportional to the square value of the electrical current passing through the TE unicouple or module. As such, for given thermoelectric materials, the total heat generation rate due to both Thomson effect and Joule heating increases with increasing the electrical current passing through the TE module, resulting in an increase in the junctions temperatures. Fig. 7 shows that the highest temperatures at different locations occurred at the open circuit condition (i.e. I = 0.0 at which no
Fig. 7. Effect of TE current on the temperatures at different locations for the case of hotspot heat rate of 10.82 W and background heat rate of 4.15 W.
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thermoelectric effects, Qs = QP = QJ = 0.0). At this condition, the heat transfer from the hot side to the cold side of the TE module is mainly by conduction. By applying electrical power to the TE module, the temperatures at different locations gradually decrease with increasing the TE electrical current, and eventually reach their lowest values at the optimum operating condition at which the TE current was approximately equal to 5.5 A (Fig. 7). For the electrical current less than or equal 5.5 A, the amount of heat rate absorbed at the hot junctions by Peltier effect overweighs the total heat generation rate due to both Thomson effect and Joule heating resulting in a decrease in these temperatures with increasing the electrical current. As shown in Fig. 7, a further increase in the TE current (i.e. I > 5.5 A) resulted in increasing the temperatures at different locations. This is because the total heat generation rate due to both Thomson effect and Joule heating overweighs the absorbed heat rate at the hot junctions by Peltier effect. Note that a high electrical current can cause the temperatures at different locations to be even higher than that at the open circuit condition. In this case, the operation of the TE module is no longer in the cooling mode (TEC) but it is in the heating mode called ‘‘Thermoelectric Heater (TEH)” such as the application of heat pumps which is not the focus of this study. As provided by El-Genk et al. (2005, 2007), and ElGenk and Saber (2008), the highest chip temperature should be maintained below 85 °C. Fig. 7 shows the thermoelectric electric current that corresponds to the hotspot temperature of 85 °C is 1.54 A. In this test, the operating range of the TE current to maintain the hotspot temperature from 85 °C to its lowest value (57.4 °C) is 1.54 A–5.5 A. For cooling computer chips using TEC, considerations must be given to identify the optimum electrical current at which the temperatures at different locations reach their lowest values. The question is ‘‘for a given TE module, does the value of the optimum electrical current change with the chip heat rate?” To answer this question, another experimental test was conducted at higher heat rate as provided and discussed next. 4.2. High-heat rate test The test parameters for different power supplies in the highheat rate test include the following: The power supply connected to the polyimide flexible heater (background): Voltage = 9.22 V, Current = 0.45 A (4.15 W). The input power to the polyimide flexible heater was kept the same as that in the case of low-heat rate test. The power supply connected to the ceramic heater (hotspot): Voltage = 6.25 V, Current = 1.93 A (12.06 W). The input power to the ceramic heater was 11.5% higher than that in the case of low-heat rate test. The power supply connected to the mechanical fan: Voltage = 10.0 V, Current = 0.23 A (2.3 W). The input power to the mechanical fan was kept the same as that in the case of lowheat rate test. In this test, the total heat rate that was applied on the aluminum sheet that mimicked the thermal spreader was 16.21 W (4.15 W by the polyimide flexible and 12.06 W by the ceramic heater). This represented a background heat flux of 0.33 W/cm2, which is the same as the previous test, and a hotspot heat flux of 12.06 W/ cm2. A similar test procedure as described in the case of low-heat rate test was also applied in this test, where the thermoelectric electrical current was gradually increased from 0.0 A (open circuit condition) to 9.0 A with a current incremental step of 0.5 A. In each step, the collected data was monitored until the steady-state con-
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dition was achieved in which the changes in the temperatures at different locations with time were negligible. For the high-heat rate test, Fig. 8 shows the effect of TE current on the temperatures at different locations. As shown in this figure, the behavior of the change in these temperatures with the TE current in this test is quite similar to the case of the low-heat rate test. The lowest hotspot temperature in the high-heat rate test (77.7 °C) occurs at an optimum TE current of 6.0 A. Moreover, the TE current that corresponds to the hotspot temperature of 85.0 °C is 3.41 A (Fig. 8). As such, the operating range of the TE current to maintain the hotspot temperature from 85.0 °C to its lowest value is 3.41 A– 6.0 A. As shown in Fig. 7 for the whole range of TE current (0.0–9.0 A), the hotspot temperature for the high-heat rate test is higher than that for the low-heat rate test. Although the background heat rate was the same for both tests (4.15 W), the background temperature for the high-heat rate test was higher than that for the low-heat rate test due to the lateral heat transfer by conduction through the aluminum sheet of 2 mm thick (Fig. 8). Have had a thinner aluminum sheet (i.e. the lateral heat transfer by conduction through the aluminum sheet would be insignificant), the background temperature for both high- and low-heat rate tests would be approximately the same. At the open circuit condition, the hotspot temperatures for the high and low-heat rate tests were 138.8 °C and 111.4 °C, respectively. This represents an increase in the hotspot temperature by 27.4 K due to increasing the hotspot heat rate by 11.5%. Fig. 7 shows that the optimum electrical current for the highheat rate test (approximately 6.0 A) is higher than that for the low-heat rate test (approximately 5.5 A, see Fig. 8). This phenomenon is in agreement with the obtained results, to be published later, for using self-cooling framework for cooling processor hotspots. At the optimum operating conditions, the lowest hotspot temperatures were, respectively, 77.7 °C and 57.4 °C for the high- and low-heat rate tests. This represents an increase in the lowest hotspot temperature by 20.3 °C as a result of increasing the hotspot heat rate by 11.5%. The TE module that was used in this study was not similar to those used by other investigators. At the optimum load current for the TE module, large reductions in hotspot temperatures were achieved in this study compared to those of other related studies. For example, at the optimum electrical currents of 5.5 A and 6.0 A for the hotspot heat rates of 10.8 and 12.1 W, respectively, reductions of hotspot temperatures (i.e. the temperature difference for the hotspot between the case of open circuit condition and the case of optimum condition) by 54.0 °C and 61.1 °C, were achieved. However, hotspot temperature reductions by 5.6 °C, 6–7 °C and 10 °C
were achieved by Redmond et al. (2013), Gupta et al. (2011) and Sullivan et al. (2012), respectively. As such, it is important to operate the TE module at its optimum electrical current so as to achieve the highest reduction in the hotspot temperatures. As an initial step, this paper mainly focuses on investigating the highest reductions in the temperature at different locations as result of using thermoelectric cooler. As shown in Fig. 8, the highest temperature reductions in the background (represented by polyimide flexible heater to mimic the cold part of the chip) for low-heat rate test and high-heat rate test were 44.8 °C (from 51.1 °C to 6.3 °C) and 48.8 °C (from 57.3 °C to 8.5 °C), respectively. Fig. 7 shows that the highest corresponding reductions in the hotspot temperatures were 54.0 °C (from 111.4 °C to 57.4 °C) and 61.1 °C (from 138.8 °C to 77.7 °C). For a given TE current, using only one TE module to dissipate the heat from the two heaters (that mimicked the microprocessor/chip with one hotspot) at different heat rates has resulted in large differences at the surface temperatures of the heaters. For example, with an electrical current of 4.0 A in the case of lowheat rate test, the temperature difference between the hotspot (60.6 °C) and background (9.3 °C) was 51.3 °C. For the case of high-rate test with the same TE current (4 A), the temperature difference between the hotspot (81.3 °C) and background (11.5 °C) was 69.8 °C. It is important to point to that there is no issue for having a part of the chip at low temperature such as 10 °C or less as long as the highest temperature in the other parts not to exceed a certain temperature threshold. For a long chip lifetime, however, a proper cooling system is the one that simultaneously insures the highest chip temperature below certain temperature threshold (e.g. 85 °C) and a small temperature difference between the hot area and the cold area in order to minimize the thermal stress in the chip.
4.3. Self-cooling framework – Case study Most recently, a 3D numerical and optimization model was developed to investigate the capabilities of using non-cascaded and cascaded TE modules for cooling the hotspots in computer chips with minimal increase in the overall power requirements when these modules were used in the cooling mode (TECs) and electrical power generation mode (TEGs). As indicated earlier, the current research project consists of a number of phases in which the ultimate goal of this project is to develop a simple tool that can be used for designing self-cooling frameworks for cooling hotspots at different operating conditions. Currently, a number of small TE modules are being used in the same experimental setup of this paper as following: (1) One (1) TEC is installed on the hot area to cool down a hotspot having different heat rates. (2) Twenty-four (24) TEGs are installed on the cold area to generate electrical power. (3) The generated electrical power by the TEGs is used to power the TEC.
Fig. 8. Effect of TE current on the temperatures at different locations for the case of hotspots heat rate of 12.06 W and background heat rate of 4.15 W.
As an example for a self-cooling framework, to demonstrate whether the harvested electrical power by TEGs can be enough to power TECs for a given chip operating condition, the 3-D model developed in this research project was used in this study to conduct a case study with 5 5 TE modules as shown in Fig. 9. The size of each module is 3 mm 3 mm and consists of 7 14 unicouples having dimensions and material properties as provided in Table 1. In this case study, the bottom surfaces of the TEC and TEGs are attached to heat sink surface at temperature of 40 °C (Fig. 9a, b). This case study was conducted for a chip size of
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Fig. 9. Schematics of 15 mm 15 mm computer chip with the attached 3 mm 3 mm TEC and TEGs, and temperature distribution (in oC) of the chip surface.
15 mm 15 mm having a total heat generation rate of 140 W, which is distributed as following: A part of the chip area of 3 mm 3 mm has a hotspot having heat generation rate of 20 W. This heat generation rate corresponds to a heat flux of 222.2 W/cm2. A 3 mm 3 mm TEC was placed on the hotspot as shown in Fig. 9b. The other chip areas have a heat generation rate of 120 W (5 W for each area of 3 mm 3 mm). The heat generation rate of each area (24 areas in total) corresponds to a heat flux of 55.6 W/cm2. As shown in Fig. 9b, 24 TEGs are placed on these areas. The heat generation rate in modern computer chips is nonuniform where the peak-to-average heat flux ratio can vary from 2 to 5 (Snyder et al., 2006; El-Genk and Saber, 2008). In this case
study, with the peak heat flux of 222.2 W/cm2 and average heat flux of 62.2 W/cm2, the ratio of the heat flux of the hotspot area to that of all areas of the chip is 3.6. As a constrain for the maximum temperature on the chip surface to be less than or equal 85 °C (El-Genk et al. 2005, 2007); El-Genk and Saber, 2008), numerical simulation was conducted to determine the maximum amount of the harvested electrical power by the TEGs that is needed to power the TEC so as to fulfil this constraint. In this case study when the 24 TEGs were connected in series, the obtained maximum amount of the harvested electrical power by the TEGs was 1.63 W. When the maximum amount of the harvested electrical power by the 24 TEGs (1.63 W) was used to power the TEC, this case is referred in this paper as ‘‘TEC-TEGs ON”. In this case, Fig. 9c shows the temperature distribution of the entire chip surface. As shown in this figure, the maximum hotspot temperature (73.6 °C) was less
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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Table 1 Material properties and thickness of different materials used in TE module. Part* Material
P-Legs** P-Bi2Te3
N-Legs** N-Bi2Te3
Electrical Conductors Copper
Electrical Insulators Ceramic
a r q
301 9.259E + 04 7700 154 1.2 48
301 9.259E + 04 7700 154 1.2 48
— 5.988E + 07 8960 385 400 46
— — 17,800 132 1.75 12.5
Cp k d
* a = Seebeck coefficient (mV/K), r = electrical conductivity (S/m), q = density (kg/m3), Cp = specific heat capacity (J/kg.K), k = thermal conductivity (W/m.K), d = Thickness (lm). ** Cross-section area = 198.21 lm 198.21 lm and spacing between the P- and N-legs, called pitch = 15 lm.
than 85.0 °C. As well, the average temperature on the entire chip surface was 61.7 °C (Fig. 9c). As such, the harvested electrical power by the TEGs was enough to power the TEC for cooling the hotspot and satisfying the constraint above at no additional electrical power requirement. It is important to point out that the temperature difference between the maximum hotspot temperature and the average hotspot temperature (70.6 °C) was only 3.0 °C. Consequently, using a self-cooling framework can result in reducing the non-uniformity in the chip temperature distribution. As indicated earlier, designing a cooling system that minimizes the non-uniformity of the temperature distribution in the computer chip can greatly contribute in reducing the anticipated thermal stresses inside the chip. To show the significance of using the maximum amount of the harvested electrical power by the 24 TEGs to power the TEC in the case ‘‘TEC-TEGs ON”, another numerical simulation was conducted for the case of open circuit condition for both the TEC and the 24 TEGs. This case is referred in this paper as ‘‘TEC-TEGs OFF”. In this case, Fig. 9d shows the temperature distribution of the entire chip surface. As shown in this figure, the highest value of the chip surface temperature was 158.0 °C. In this case, the average surface temperature of the hotspot was 142.9 °C, while the average surface temperature of the entire chip was 74.1 °C. Powering the TEC by the harvested power by the 24 TEGs (1.63 W), however, has resulted in: Reducing the highest chip surface temperature by 84.4 °C (from 158.0 °C in the case ‘‘TEC-TEGs OFF” to 73.6 °C in the case ‘‘TECTEGs ON”), and Reducing the average hotspot temperature by 72.3 °C (from 142.9 °C in the case ‘‘TEC-TEGs OFF” to 70.6 °C in the case ‘‘TEC-TEGs ON”). Last but not the least, as shown in Fig. 9c and d, unlike the case ‘‘TEC-TEGs OFF”, the hotspot location in the case ‘‘TEC-TEGs ON” was approximately disappeared from the chip surface. In summary, the novelty of the approach described above by using selfcooling framework for cooling computer chips has resulted in: (1) Reducing the non-uniformity of the temperature distribution on the chip surface, and hence help minimize the anticipated thermal stresses in the chip, and (2) Decreasing the power requirements for cooling computer chips using thermoelectric devices. No additional electrical power was needed in the demonstrated case above to maintain the hotspot temperature below 85 °C.
low-heat rate test and 12.1 W for the high-heat rate test) were conducted at steady-state condition in which an aluminum sheet was used to mimic the thermal spreader and heated by ceramic heater to create a hotspot, and polyimide flexible heater to provide the background heat rate. The two electrical heaters were used to mimic the microprocessor/chip. A commercial TE module attached to heat sink and mechanical fan was used to cool down the aluminum sheet at different thermoelectric electrical currents. The results of the low-heat rate test showed that the hotspot temperature at open circuit condition (111.4 °C) can be decreased to 57.4 °C at the optimum electrical current of 5.5 A, which represented a reduction in the hotspot temperature by 54.0 °C (or by 94%). For high-heat rate test, results showed that the hotspot temperature at open circuit condition (138.8 °C) can be decreased to 77.7 °C at the optimum electrical current of 6.0 A, which represented a reduction in the hotspot temperature by 61.1 °C (or by 79%). The optimum TE current for the high-heat rate test was greater than that for the low-heat rate test. This phenomenon is in agreement with other related studies. The work presented in this study is a part of a research project that consists of a number of phases including experimental testing, and 3D numerical modeling and optimizations of cascaded and non-cascaded thermoelectric coolers (TECs) and cascaded and non-cascaded thermoelectric generators (TEGs). The ultimate goal of this project is to develop a simple tool for designing self-cooling framework for cooling chip hotspots at different operating conditions with minimal increase in the overall power requirements. In this self-cooling framework, cascaded and non-cascaded TEGs are installed on the cooler chip areas in order to harvest electrical power from the chip-wasted heat. Whereas the chip hotspot areas are cooled using cascaded and non-cascaded TECs that are powered by the harvested electrical power from the TEGs. For a given chip operating condition, a case study was conducted in this paper to demonstrate whether or not the harvested electrical power by the TEGs is enough to power a TEC located on a hotpot. The results showed that the harvested electrical power by the TEGs was not only enough to power the TEC but also insuring the hotspot temperature remains below a certain temperature threshold (85 °C). As well, with the self-cooling framework, the location of the hotspot was approximately disappeared from the chip surface with no requirement for additional electrical power. More results about developing self-cooling framework for cooling chip hotspots at different operating conditions with cascaded and non-cascaded TEGs and TECs will be published later.
Acknowledgments 5. Summary and conclusions Experimental tests were conducted to investigate the potential capabilities of TE technology to cool down chip hotpots at different heat rates. In this study, two experimental tests (10.8 W for the
This research was funded by the Colleges and Institutes Sector (CIS) at the Royal Commission for Jubail & Yanbu, Kingdom of Saudi Arabia. The authors would like to thank Professor Wahid Maref from University of Quebec for his technical support.
Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009
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Please cite this article as: S. Al-Shehri and H. H. Saber, Experimental investigation of using thermoelectric cooling for computer chips, Journal of King Saud University – Engineering Sciences, https://doi.org/10.1016/j.jksues.2019.03.009