Extraction technique for characterization of electric field distribution and drain current in VDMOS power transistor

Microelectronics Journal 34 (2003) 77–83 www.elsevier.com/locate/mejo

Extraction technique for characterization of electric field distribution and drain current in VDMOS power transistor N. Kaushik, A. Kranti, M. Gupta, R.S. Gupta* Semiconductor Devices Research Laboratory, Department of Electronic Science, University of Delhi South Campus, Benito Juarez Road, New Delhi 110 021, India Received 5 August 2002; revised 9 September 2002; accepted 12 September 2002

Abstract This paper presents a methodology for modeling the electric field distribution in the vertical direction of VDMOS power transistors, considering the effects of cell spacing and drain voltage. An accurate and consistent extraction technique is developed to extract the values of various important parameters based on non-linear and multivariable regression techniques for the first time. The generalized form of electric field distribution enables the physical modeling of drain current at the onset of quasi-saturation considering the effect of non-uniform electron distribution in the n-epi region. Results so obtained are in good agreement with PISCES simulation over wide range of device parameters. The proposed model will be highly suitable for CAD (Computer Aided Design) tools in HVIC applications. q 2002 Elsevier Science Ltd. All rights reserved. Keywords: Silicon VDMOS; Power MOSFET; Electric field distribution; Drain current; Quasi-saturation; Cell spacing

1. Introduction Power MOSFETs have been extensively used in applications such as motor control, switch-mode power supplies and telecommunication electronics. MOSFET for power applications cannot be fabricated by merely scaling up low-power MOSFET to the described voltage and current. Further, the high-voltage blocking ability requires a large depletion area across the reverse-biased PN (body/ drift) junction. Thus, the power MOSFET structure comprises of a low doped epi-layer to support the blocking voltage and is usually fabricated by the double-diffusion technique, giving rise to the name DMOST [1,2]. In recent years, the double-diffusion MOS (DMOS) technology has attracted a great interest in power switching applications due to fast switching time and simple gate drive circuitry which is compatible with MOS technology [1 – 10]. Moreover, vertical DMOS transistors (VDMOST) have been merged with low-power CMOS and Bipolar circuitry to form high-voltage integrated circuits (HVIC’s) [5 – 10]. VDMOS transistors provide the ability to switch approximately 10 times faster than bipolar power transistors. In * Corresponding author. Tel.: þ 91-11-4105580; fax: þ 91-11-6886606. E-mail address: [email protected] (R.S. Gupta).

order to provide the best design efficiency and reliability of HVIC’s, efficient CAD (Computer Aided Design) oriented model of VDMOS is crucial and highly essential for technology development and performance prediction. Fig. 1(a) shows a typical vertical DMOS device in which the cell spacing (LD) is defined as the distance between the two sources areas. In high-power switched-mode circuits, the high-voltage VDMOS transistor exhibits a unique operating mode called ‘quasi-saturation’ for sufficiently high VGS. The performance of a VDMOS device is limited by the quasi-saturation effect. In quasi-saturation, the device is basically in the linear regime of operation, yet the drainto-source current IDS increases with increasing VDS at a much lower rate than in the linear region. The quasisaturation is strongly influenced by the cell spacing (LD) and drain-to-source voltage (VDS) [11 –14]. In the present paper, a model for electric field distribution in the vertical direction has been developed taking into account the effect of cell spacing (LD) and drain voltage (VDS). Analytical models based on detailed derivations incorporate device physics but usually cannot model complex devices for a wide range of device parameters because of certain ideal assumptions that have to be made in order to facilitate an analytical closed form solution. Moreover, in the absence of experimental

0026-2692/03/$ - see front matter q 2002 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 6 9 2 ( 0 2 ) 0 0 1 4 0 - 4

78

N. Kaushik et al. / Microelectronics Journal 34 (2003) 77–83

[13,14] analyzed the performance of VDMOS power transistor based on an analytic solution of Poisson’s and current transport equations leading to a cubic equation of the drain current. The model uses several assumptions and the accuracy of the model fails at higher drain voltages. Further, in all the above models the behavior of the electric field distribution in the vertical direction is not modeled. Previous results of PISCES simulation [13,14] of the device demonstrate a bell-shaped electric field distribution in the vertical direction. Thus the first step towards a compact CAD oriented model of VDMOS transistors is the modeling and characterization of electric field distribution along the vertical direction. This paper presents an accurate and consistent extraction technique to develop the electric field distribution model for the first time. The generalized form of the electric field distribution enables physical modeling of the drain current at the on set of quasisaturation considering the effect of non-uniform electron distribution in the n-epi region. In Section 2, the general technique of extraction and the cell spacing dependent drain current model are described which are in close proximity with simulation results.

2. Model formulation

Fig. 1. (a) Schematic diagram of a vertical DMOS device. (b) Cross-section of one half of vertical DMOS device.

data, idealized assumptions have to be made in order to obtain the model equations. Therefore, if a model developed covers a wide range of variables with reasonable accuracy and the model parameters can be correlated to process variables, which would then be extremely useful in aiding new technology development. Several physical models for quasi-saturation behavior of VDMOS power transistor have been proposed [11 –14]. The quasi-saturation model of Darwish [11] gives the drain current independent of the drain voltage, an assumption, which is valid in ideal device performance. However, in realistic devices the drain current increases with the applied drain bias even at the onset of the quasi-saturation. Kim and Fossum [12] proposed a semi-numerical model that required numerical solution using Newton – Raphson iterative method. Although VDMOS power transistor can be analyzed by numerical simulation, but it only provides discrete data points, which are difficult to use in device optimization and design. Thus a closed form solution is highly desirable for a CAD oriented model. Lou et al.

Fig. 1(b) shows the cross-section of a VDMOS device having an n-epi region of 5.8 mm (y3) with a doping concentration of 1 £ 1016 cm23, an nþ polysilicon gate with ˚ , a p-type double-diffused an oxide thickness of 500 A channel region with a junction depth of 1.8 mm (y1) and a length of 0.75 mm. In VDMOS devices, during forward operation, the electrons are concentrated in the channel region and scattered in the n-epi area. The electron current flows from the surface contacts via the surface channel region and the substrate drift region in the n-epi area. The total device area is divided in to the channel region and the drift region based on the path of the current flow. In the channel region, the current is concentrated in a surface channel beneath the gate oxide. However, in the substrate drift region, the electron current flows with a constant crosssection in Region 1 to a spreading cross-section in Region 2 and Region 3. In fact, the current flows at the left side of the drift region with an angle of 458 counter clockwise from the lateral buried layer direction [3] as shown in Fig. 1(b). The simulation results [13,14] for electric field distribution in vertical direction of the device at the onset of the quasi-saturation indicate that the electric field initially increases, attains a maximum value and then decreases. The results demonstrate a bell-shaped electric field distribution in the vertical directions for various values of drain voltages (VDS) and cell spacing (LD). In addition, the smaller LD case shows a higher electric field. The simulation results also indicate an accumulation of the electrons at the silicon surface. The electron density decreases on moving away from the surface and depletion of electrons takes place in

N. Kaushik et al. / Microelectronics Journal 34 (2003) 77–83

the region near the buried layer. This bell-shaped electric field distribution is observed due to the non-uniform electron distribution in the vertical direction, which can be explained by the Poisson’s equation (neglecting the hole terms) as 1s

dEy ¼ q½nðyÞ 2 ND  dy

ð1Þ

where 1s is the permitivity, Ey is the vertical direction electric field, nðyÞ is the electron concentration in the vertical direction and ND is the electron doping concentration of the drift region. From Eq. (1) it is clear that at a point yp away from the surface, free electron concentration nðyÞ is equal to the doping (ND) in the drift region of the VDMOS transistor, which corresponds to a peak in vertical electric field distribution. 2.1. The electric field distribution model The shape of the electric field distribution is governed by important technical parameters such as cell spacing (LD), drain-to-source voltage (VDS), junction depth of the doublediffused p-type layer (y1), vertical distance between source and drain (y ) and doping of the n-epi region (ND). The bellshape behavior of the vertical direction electric field can be expressed as ( 2aðy 2 yp Þ2 þ K if 0 # y # 1:9yp ; Ey ðyÞ ¼ ð2Þ Emin Otherwise where a, yp and K are the fitting parameters sensitive to the process parameters such as cell spacing, doping of n-epi region and drain-to-source voltage. yp represent the position in the vertical direction at which the electric field attains the maximum value whereas K and a are used to fit the modeled curve to the simulated results. 2.2. Parameter extraction This section present the general and consistent approach used to formulate the compact electric field distribution model for VDMOS transistor based on PISCES simulated data. An empirically based model will not be useful unless a consistent and simple parametric extraction procedure can be adopted, nor will it be of any interest if experimental data is needed to extract the parameters every time the model is used. Our compact electric field distribution model uses a simple and 3– 4 step extraction procedure, which requires simulated/experimental data once for a given device. The generalized extraction procedure is described as follows. Step 1 A simple non-linear regression of the fitting parameter with the simulated data based at different values of the device parameter give non-linear/linear relation with that

79

parameter, which show the same behavior as the simulated data with that device parameter. Step 2 Repeat step 1 with another device parameter on which the fitting parameter depends. Step 3 After obtaining the non-linear/linear relation of the fitting parameter with the device parameters a single relation of the fitting parameter in terms of the device parameters (used in the above steps) can be obtained by using multivariate polynomial regression technique. The result of step 3 gives the fitting parameters as a function of the device parameters on which the electric field distribution depends. As mentioned in Section 1, the essence of the proposed compact modeling approach is to predict the physical behavior by interpolation. By the above method, the fitting parameters sensitive to the process parameters can be extracted. Using the above extraction procedure the relation of yp as a function of VDS and LD is obtained as: Step 1 A simple non-linear regression of the fitting parameter yp with simulated data based at different values of VDS give a non-linear relation with VDS as: pffiffiffiffiffi ð3Þ yp ¼ 2k1 £ VDS þ k2 £ VDS 2 k3 Step 2 Repeating step 1 with LD as another device parameter, the relation of yp with LD is obtained as yp ¼ k4 £ LD þ k5

ð4Þ

where k1, k2, k3, k4 and k5 are constant co-efficient. Step 3 Using the relation of yp with VDS and LD as obtained in steps 1 and 2, a single relation of yp in terms of device parameters VDS and LD is obtained using multivariate polynomial regression technique as pffiffiffiffiffi yp ¼ 2A1 £ VDS þ A2 £ VDS þ A3 £ Ld 2 A4 ð5Þ where A1, A2, A3 and A4 are the constant co-efficient. The same procedure is used to obtain the relation of other fitting parameters a and K with the device parameters VDS and LD. The extraction steps give the relation as pffiffiffiffiffi a ¼ 2B1 £ VDS þ B2 £ VDS þ B3 £ L2D 2 B4 £ LD ð6Þ pffiffiffiffiffi K ¼ 2C1 £ VDS þ C2 £ VDS 2 C3 £ LD 2 C4 ð7Þ where B1, B2, B3, B4, C1, C2, C3 and C4 are the constant coefficient. Using Eqs. (5) – (7) with Eq. (2) the electric field distribution at the onset of quasi-saturation can be obtained for any value of drain voltage (VDS) and cell spacing (LD).

80

N. Kaushik et al. / Microelectronics Journal 34 (2003) 77–83

Table 1 Extracted values of constant co-efficient used in the present analysis

In Region 1, the effective area of cross-section of current flow is given as

Co-efficient

Value

AðyÞ ¼ W £ LD

A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4

2.271 £ 1028 m V21 5.794 £ 1027 m V21/2 0.236 10.406 £ 1027 m 1.325 £ 1017 m23 1.678 £ 1018 V1/2 m23 1.171 £ 1029 V m25 1.352 £ 1024 V m24 3.371 £ 104 m21 3.118 £ 106 V1/2 m21 1.200 £ 1012 V m22 2.974 £ 106 V m21

where W is width of the device in direction perpendicular to the cross-section and LD is the width of Region 1. The voltage drop across Region 1 is obtained by solving Eq. (10) with Eq. (11) as Vðy1 Þ 2 Vðy0 Þ ¼

ð11Þ

1 ½E ðy Þ2 2 2By1  2A y 1

ð12Þ

where A¼

IDS qND 2 1Si WLD mno Ec 1Si

Table 1 shows the extracted values of constant coefficient used in Eqs. (5) – (7).

B¼

IDS 1Si WLD mno

2.3. Drift region model

with y1 as the junction depth of the channel region. In Region 2, the effective area of cross-section of current flow at location y is given as

A physics based quasi-saturation model of drain current is now developed for VDMOS device using the compact electric field distribution model. The drift region is divided into a rectangular region and a trapezoidal region based on the cross-section along the electron current flow. In Region 1, the electron current is uniformly distributed in a rectangular area. In Region 2 and Region 3 the electron currents are scattered in trapezoidal areas. In the substrate drift region, the current is expressed as IDS ¼ AðyÞqnðyÞ

mno Ey ðyÞ Ey ðyÞ 1þ Ec

ð8Þ

where AðyÞ is the effective area of cross-section of current flow at location y, Ey ðyÞ is the vertical direction electric field at location y, mno is the low field mobility, nðyÞ is the electron concentration at location y, q is the electronic charge, Ec is the critical electric field determined by electron saturation velocity (vsat) and mno ðEc ¼ vsat =mno Þ: To consider the effect of non-uniform electron distribution in the drift region, the electron density at location y is derived from Eq. (8) as:   Ey ðyÞ IDS 1 þ Ec nðyÞ ¼ ð9Þ AðyÞqmno Ey ðyÞ Using Eq. (9) in Eq. (1), the Poisson’s equation is written as 0 1 Ey ðyÞ 1 þ B C dEy ðyÞ Ec 1Si 2 ND C ð10Þ ¼ qB IDS @ A AðyÞqmno Ey ðyÞ dy where 1Si is silicon permitivity.

AðyÞ ¼ W½LD þ ðy 2 y1 Þcot a

ð13aÞ

where a < 458: Therefore AðyÞ can also be written as: AðyÞ ¼ W½LD þ y 2 y1 

ð13bÞ

Due to variable cross-section area, the solution of Eq. (10) becomes complex. Therefore to expedite the analysis, the bottom boundary (y2) of Region 2 has been defined in such a manner that the length below the peak electric field is equal to that above it. The boundary conditions are defined as y2 2 yp ¼ yp 2 y1 ;

y2 # y3

ð14aÞ

or y2 ¼ 2yp 2 y1

ð14bÞ

Consequently, two triangles can be formed in the Region 2 (shown as DOAB and DODC in Fig. 1(b)), which are congruent. As nðyÞ ¼ ND at yp and the variation of nðyÞ at both sides of yp is symmetrical, therefore the voltage drop across the DODC above yp is equal to the voltage drop across DOAB below yp. Using this approximation, the trapezoidal area of Region 2 can be replaced by two rectangle one of width LD above yp and the other of width ðLD þ y2 2 y1 Þ below yp. Now the effective area of cross-section of current flow is given as AðyÞ ¼ W £ LD ;

ð15aÞ

above yp

and AðyÞ ¼ W½LD þ y2 2 y1 ;

below yp

ð15bÞ

N. Kaushik et al. / Microelectronics Journal 34 (2003) 77–83

81

The solution of Eq. (10) using Eq. (15) gives the voltage drop across Region 2 as

Substituting the values of A, B, C and D from Eqs. (12) and (16) in Eq. (19) and simplifying we obatin

Vðy2 Þ 2 Vðy1 Þ

2 þ QIDS þ R ¼ 0 PIDS

¼

1 ½E ðy Þ2 2 Ey ðy1 Þ2 2 2Bðyp 2 y1 Þ 2A y p 1 ½E ðy Þ2 2 Ey ðyp Þ2 2 2Dðy2 2 yp Þ þ 2C y 2

where ð16Þ

where C¼

IDS qND 2 1Si WðLD þ y2 2 y1 Þmno Ec 1Si

D¼

IDS 1Si WðLD þ y2 2 y1 Þmno

In Region 3 also, the electron current flow is through a trapezoidal area. However, as the drain-to-source voltage (VDS) increases, the value of yp also increases and hence y2 shifts towards y3, where the electric field is small. Therefore a linear approximation for the electric field can be used. Using the linear approximation, the voltage drop across Region 3 is given as: Vðy3 Þ 2 Vðy2 Þ ¼

Ey ðy3 Þ þ Ey ðy2 Þ ðy3 2 y2 Þ 2

ð17Þ

The voltage drop from the drain-to-source is the sum of the voltage drops in the Regions 1 –3 and drop across the channel (VCH) and is given as VCH þ ½Vðy1 Þ 2 Vðy0 Þ þ ½Vðy2 Þ 2 Vðy1 Þ þ ½Vðy3 Þ 2 Vðy2 Þ ¼ VDS

ð21Þ

ð18Þ

2y2 1 2 ðVDS 2 Vðy0 ÞÞ mnEc mnEc2 !! Ey ðy2 Þ þ Ey ðy3 Þ 2 ðy3 2 y2 Þ 2   Ey ðyp Þ2 y2 2 yp qND yp þ þ Q¼ 2nEc 1Si m n   2 2 Ey ðy2 Þ 2 Ey ðyp Þ qND 1 1 þ þ þ n 2mEc 1Si Ec m   Ey ðy2 Þ þ Ey ðy3 Þ ðy3 2 y2 Þ £ ðVDS 2 Vðy0 ÞÞ 2 2

P¼

R¼

2qND Ey ðyp Þ2 Ey ðy2 Þ2 2 Ey ðyp Þ2 þ 1Si 2 2  !! Ey ðy2 Þ þ Ey ðy3 Þ qND ðy3 2 y2 Þ þ ðVDS 2 Vðy0 ÞÞ 2 2 1Si

m ¼ 1Si WLD mno n ¼ 1Si WðLD þ y2 2 y1 Þmno Solving Eq. (21) we obtain pffiffiffiffiffiffiffiffiffiffiffiffi 2Q þ Q2 2 4PR IDS ¼ 2P

ð22Þ

From Eqs. (12), (16) – (18) we obtain 1 1 ½Ey ðyp Þ2 2 2Byp  þ ½E ðy Þ2 2 Ey ðyp Þ2 2 2Dðy2 2 yp Þ 2A 2C y 2 Ey ðy3 Þ þ Ey ðy2 Þ ðy3 2 y2 Þ ¼ ½VDS 2 Vðy0 Þ ð19Þ þ 2 Vðy0 Þ can be approximated by using the procedure described in Refs. [12,13] as pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 Vðy0 Þ ¼ 2 2 2q1Si NAO expð2hÞ: 4COX qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi2 2 þ 2q1Si NAO expð2hÞ þ 4ð4d þ 1ÞfB COX 2 fB þ h

kT q

ð20Þ

where COX is the gate oxide capacitance per unit area, fB is the channel Fermi potential ðfB ¼ kT=q lnðNAO =ni ÞÞ; NAO is the peak concentration in the channel region (NAO ¼ 3.3 £ 1017 cm23), ni is the intrinsic carrier concentration. d (d ¼ 2.5) is used to include the non-uniform potential distribution in the channel. h (h ¼ 3.4) is used to describe the channel profile NA ðxÞ¼NAOexp½2hðx2Ls Þ=L: Ls is the location of the source end of the channel.

Fig. 2. Variation of peak electric field position with drain voltage for various value of cell spacing. Inset: variation of peak electric field position with cell spacing for various value of applied drain bias.

82

N. Kaushik et al. / Microelectronics Journal 34 (2003) 77–83

From Eqs. (2) and (20) –(22), a closed form analytical model at quasi-saturation in terms of VDS and cell spacing (LD) for a vertical DMOS device has been obtained. Eq. (22) shows that present model’s drain current expression is simpler as compared to that proposed by Lou et al. [13,14]. Also, a generalized and consistent extraction procedure for the electric field distribution in the vertical direction is developed for the first time to facilitate a CAD oriented model.

Fig. 3. (a) Variation of vertical electric field distribution with depth along the device for various values of drain voltage at the onset of quasisaturation for cell spacing of 4 mm. (b) Variation of vertical electric field distribution with depth along the device for various values of cell spacing at the onset of quasi-saturation for drain voltage of 50 V.

3. Results and discussion Fig. 2 shows the variation of the peak electric field position (yp) in a VDMOS device biased at various values of drain-to-source voltages (VDS) at the onset of the quasisaturation with cell spacing (LD) using the value of yp extracted from Eq. (5). The figure shows that for a given cell spacing, yp initially increases sharply with increase in VDS and then increase is slow. Fig. 2 (inset) shows that for a given drain bias (VDS), the peak position (yp) increases linearly with increase in cell spacing (LD). Fig. 3 shows the VDS and LD dependent electric field distribution as a function of vertical distance between source and drain and are in good agreement with the PISCES simulation results [13,14] for which the model parameters are first extracted as outlined in Section 2.2. Fig. 3(a) shows the electric field distribution in vertical direction of a VDMOS with cell spacing (LD) of 4 mm for various values of VDS. Fig. 3(b) shows the electric field distribution for various values of cell spacing (LD) at VDS ¼ 50 V. Fig. 4 shows the variation of drain current at the onset of quasi-saturation for various VDS for cell spacing of 3, 4 and 5 mm. Results of Lou et al. [13,14], Darwish’s model [11] and PISCES results [13,14] are also shown for comparison. It is clear from the graph that at high drain-to-source voltages, the saturated drain current has been underestimated in Darwish’s model [11] and overestimated in Lou et al. [13,14]. As shown, the present model indicates a closer fit to the PISCES results [13,14]. This is attributed to the fact that the proposed model has incorporated the nonuniform distribution of electron density in the drift region to obtain the saturated drain current expression.

Fig. 4. Dependence of saturation drain current at the onset of quasisaturation with drain voltage for various values of cell spacing.

N. Kaushik et al. / Microelectronics Journal 34 (2003) 77–83

83

efficient and accurate CAD oriented model of VDMOS, suitable for High-Voltage Integrated Circuit (HVIC) applications.

Acknowledgements The authors are grateful to Defence Research and Development Organisation (DRDO), Ministry of Defence, Government of India for the necessary financial assistance to carry out the research work.

References

Fig. 5. Variation of saturation drain current at the onset of quasi-saturation with cell spacing for various value of drain voltage.

Fig. 5 shows the saturated drain current at the onset of quasi-saturation in a VDMOS device at various values of cell spacing (LD) for drain bias (VDS) of 20, 30, 40 and 50 V. As indicated in Figs. 4 and 5, the VDMOS device with wider cell spacing provides a higher saturated drain current. Results indicate that during quasi-saturation, the device is basically in the linear regime of operation, yet the drain-tosource current IDS increases with increasing VDS at a much lower rate than in the linear region.

4. Conclusions A general approach to formulate a physics based compact model for electric field distribution in vertical direction for a VDMOS power device has been proposed, incorporating the dependence of drain-to-source voltage and cell spacing. The present model provides a fairly accurate explanation of the cell spacing and drain-to-source voltage dependent quasi-saturation behavior in a VDMOS power device. As verified by the PISCES results, the present model provides an accurate formulation of the electric field distribution in the vertical direction, which combines analytic physics and realistic behavior to develop an

[1] B.J. Baliga, Modern Power Devices, Wiley, New York, 1987. [2] D.A. Grant, J. Gowar, Power MOSFETs: Theory and Applications, Wiley, New York, 1989. [3] K. Shenai, Optimally scaled low-voltage vertical power MOSFET’s for high frequency power conversion, IEEE Trans. Electron. Dev. 37 (4) (1990) 1141–1153. [4] Y.C. Liang, K.P. Gan, G.S. Samudra, Oxide-bypassed VDMOS (OBVDMOS): an alternative to superjunction high voltage MOS power devices, IEEE Electron. Dev. Lett. 22 (8) (2001) 407–409. [5] C. Hu, M.H. Chi, V.M. Patel, Optimum design of power MOSFET’s, IEEE Trans. Electron. Dev. 31 (12) (1984) 1693– 1700. [6] P. Habas, Z. Prijic, D. Pantic, N.D. Stojadinovic, Charge-pumping characterization of SiO2/Si interface in virgin and irradiated power VDMOSFET’s, IEEE Trans. Electron. Dev. 43 (12) (1996) 2197– 2209. [7] K.J. Fischer, K. Shenai, Effect of bipolar turn-on on the static current– voltage characteristics of scaled vertical power DMOSFET’s, IEEE Trans. Electron. Dev. 42 (3) (1995) 555–563. [8] K.J. Fischer, K. Shenai, Dynamics of power MOSFET switching under clamped inductive loading conditions, IEEE Trans. Electron. Dev. 43 (6) (1996) 1007–1015. [9] B.J. Baliga, Trends in power semiconductor devices, IEEE Trans. Electron. Dev. 43 (10) (1996) 1717–1731. [10] X.B. Chen, X. Wang, J.K.O. Sin, A novel high-voltage sustaining structure with buried oppositely doped regions, IEEE Trans. Electron. Dev. 47 (6) (2000) 1280–1285. [11] M.N. Darwish, Study of the quasi-saturation effect in VDMOS transistors, IEEE Trans. Electron. Dev. 33 (11) (1986) 1710– 1716. [12] Y.S. Kim, J.G. Fossum, Physical DMOST modeling for high-voltage IC CAD, IEEE Trans. Electron. Dev. 37 (3) (1990) 797 –803. [13] K.H. Lou, C.M. Liu, J.B. Kou, Analysis of the quasi-saturation behavior considering the drain-to-source voltage and cell-spacing effects for a vertical DMOS power transistor, Solid-State Electron. 36 (1) (1993) 85–91. [14] K.H. Lou, C.M. Liu, J.B. Kou, An analytical quasi-saturation model for vertical DMOS power transistors, IEEE Trans. Electron. Dev. 40 (3) (1993) 676–679.