- Email: [email protected]
Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes
MEE-10647; No of Pages 6 Microelectronic Engineering xxx (2017) xxx–xxx
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Research paper
Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes Hyungjin Kim a, Min-Chul Sun b, Sungmin Hwang a, Hyun-Min Kim a, Jong-Ho Lee a, Byung-Gook Park a,⁎ a b
Inter-university Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Republic of Korea System LSI, Semiconductor Business Group, Samsung Electronics Co. Ltd., Yongin 17114, Republic of Korea
a r t i c l e
i n f o
Article history: Received 6 September 2017 Received in revised form 1 October 2017 Accepted 22 October 2017 Available online xxxx Keywords: FinFET Asymmetric independent dual-gate Sidewall spacer patterning Chemical-mechanical polishing (CMP) process Multi-functional device
a b s t r a c t In this paper, we present the fabrication method of asymmetric independent dual-gate FinFETs with different gate stack using sidewall spacer patterning and two-step chemical-mechanical polishing (CMP) processes. The fin width is controlled as a result of sidewall spacer patterning. The two-step CMP processes are conducted to separate two gates and to make different gate stacks for each gate, respectively. The fabricated devices can be used for multiple applications by utilizing independent two gates. First of all, the independent two gates offer the flexible threshold voltage modulation properties by applying the second gate (G2) bias with little subthreshold swing degradation. Second, the device can be utilized as a charge trap flash memory cell by trapping electrons in the charge storage layer. These results provide a possible way to fabricate asymmetric independent dual-gate FinFETs having potential as a multi-functional single device. © 2017 Elsevier B.V. All rights reserved.
1. Introduction Metal-oxide-semiconductor field-effect transistors (MOSFETs) with independent dual-gate structure have been widely investigated with multiple applications including flexible threshold voltage (VT) controllability of logic devices, multi-functional memory, and sensor applications [1–12]. However, most of the approaches have been limited in their applications because of the lack of charge storage node and complicated fabrication method. Masahara et al. reported independent double-gate FinFETs with different equivalent oxide thickness (EOT) gate stacks for multi-VT logic devices by applying voltage to the 2nd gate (G2) [1]; however, it is hard to be utilized as a memory device because of the lack of charge storage layer. Park et al. reported double-gate 1T-DRAM cell with ONO buried oxide (BOX) for enhancing retention characteristics of volatile memory function by trapping electrons in the nitride layer [2]; however, it has several issues such as non-self aligned common back-gate structure and complicated fabrication method including sequential n+ polycrystalline Si/O/N/O strip processes with SF6 isotropic dry etch, H3PO4 wet etch, and HF wet etch, respectively. Previously, we reported the applications of asymmetric independent dual-gate FinFET as a multi-VT logic device [13], a volatile and nonvolatile memory device [14–16], and a synaptic device of neuromorphic system [17–20]. In this study, we present the nanofabrication method of asymmetric independent dual-gate FinFET using sidewall spacer
⁎ Corresponding author. E-mail address: [email protected] (B.-G. Park).
patterning and CMP processes. The channel width can be easily scaled by controlling a spacer thickness, and a self-aligned dual-gate with different gate stack is formed at the same time. Using SiN film as a stopping layer in chemical-mechanical polishing (CMP) process offers highly uniform CMP characteristics. For utilizing as a multi-functional memory device, G2 has ONO stack as a charge storage node and the device is based on floating-body structure. The detailed experimental conditions and issues of the key process steps are described and the electrical characteristics of the fabricated devices are analyzed. 2. Process design and fabrication flow In order to fabricate the asymmetric independent dual-gate FinFET with different gate stack, the fabrication sequence follows the process flow shown in Fig. 1. A process simulation tool of Silvaco Inc. (Athena ver. 5.20.0.R 2012) is used to estimate the experimental results more accurately [21]. First, a hard mask stack is deposited and the 1st active patterns are etched as shown in Fig. 1(a). Because two gates are formed in sequence, the active region which contacts G1 is formed first. The hard mask stack is comprised of silicon dioxide (SiO2) and silicon nitride (Si3N4) which is used for selective etching with poly-silicon and stopping layer of CMP process, respectively. Steep etch slope is required because SiO2 sidewall is formed at the region where the hard mask stack is removed. After forming G1 stack, CMP process is done to leave the poly-silicon layer only at the G1 region as shown in Fig. 1(b). The CMP slurry which has good selectivity between doped poly-silicon and Si3N4 is required to protect the height of the hard mask stack, which allows a margin for
https://doi.org/10.1016/j.mee.2017.10.014 0167-9317/© 2017 Elsevier B.V. All rights reserved.
Please cite this article as: H. Kim, et al., Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes, Microelectronic Engineering (2017), https://doi.org/10.1016/j.mee.2017.10.014
2
H. Kim et al. / Microelectronic Engineering xxx (2017) xxx–xxx
Top view
Sectional view Sidewall spacer (MTO) PR
Si3N4 BOX
poly-Si
SiO2
poly-Si PR
Silicon Si3N4
Silicon
BOX
Silicon
(a)
(e) S
n+ doped poly-Si
poly-Si
poly-Si
Gate 1
Fin witdh ~ 40nm
D
Si3N4
BOX
BOX
(b)
poly-Si
(f)
n+ doped poly-Si
n+ doped poly-Si (Gate 2)
Gate 1
Gate 1
Si3N4
(c)
(g)
Sidewall spacer (MTO)
Sidewall spacer (MTO)
poly-Si
G1
D
Sidewall spacer (MTO)
S
G2
Gate 1
Silicon
Gate 2
Gate 1 BOX
BOX
(d)
(h)
Fig. 1. Device fabrication flow. (a) Deposition of hard mask and patterning. (b) Formation of G1 through CMP. (c) Removal of hard mask. (d) MTO sidewall formation. (e) Sidewall cutting. (f) Fin channel formation. (g) G2 stack deposition and CMP. (h) Etchback for gate splitting and gate patterning.
gate splitting process later. And then, the Si3N4 layer is removed with dry etch process due to bad selectivity of phosphoric acid (H3PO4) wet etch process between doped poly-silicon and Si3N4, and the SiO2 layer is removed with hydrogen fluoride (HF) wet etch process having good selectivity between silicon and oxide (Fig. 1(c)). Thin sidewall is formed through deposition and dry etch process of medium temperature chemical vapor deposition oxide (MTO) which has slow deposition rate, hence forming the thin sidewall (Fig. 1(d)). The unnecessary sidewall is removed using HF wet etch process to suppress the parasitic capacitance around G1 region as illustrated in Fig. 1(e). Then, a silicon fin is formed using dry etch process (Fig. 1(f)). During this process, the surface of the 2nd active region is formed. The fin is achieved with little loss of oxide sidewall because hydrogen bromide (HBr) plasma etch process has good selectivity between silicon and SiO2 and the fin width is the same as the thickness of oxide sidewall. After the fin formation, G2 stack comprised of oxide/nitride/oxide/ doped poly-silicon is deposited over the fin and G1 using lowpressure chemical vapor deposition (LPCVD) as shown in Fig. 1(g). The CMP process makes a difference in the thickness of doped polysilicon and this difference separates two gates by dry etchback process (Fig. 1(h)). The gate length is defined at the same time by photolithography and dry etch process.
3. Experimental results 3.1. Deposition of hard mask and patterning First, BF2 + ions for body doping are implanted with a dose of 2 × 1011 and 2 × 1012 cm−2 over a silicon-on-insulator (SOI) wafer with 100 nm SOI layer and 375 nm buried oxide (BOX) layer fabricated by SIMOX technology [22]. A hard mask stack made up of 300 nm oxide and 100 nm nitride is deposited, and all the layers including SOI and the hard mask at G1 region are etched. The purpose of the oxide and nitride layers comprising the hard mask is selective etching with polysilicon layer using HF wet etch process and stopping layer of CMP process, respectively. The oxide layer is deposited by LPCVD using tetraethoxysilane (Si(OC2H5)4, TEOS) gas at 710 °C and 250 mTorr, and the nitride layer is deposited by LPCVD in an ambient of dichlorosilane (SiH2Cl2) of 30 sccm and ammonia (NH3) of 100 sccm at 785 °C and 200 mTorr. At the etch process after then, it is very important to obtain a steep etch slope because it is transmitted at the angle of the sidewall spacer for fin channel formation. If the hard mask is etched gradually, the width of a fin channel would be thicker than the spacer thickness, which means the channel width cannot be controlled finely. When SS03A9, which is based on phenol formaldehyde resin, is used as a
Please cite this article as: H. Kim, et al., Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes, Microelectronic Engineering (2017), https://doi.org/10.1016/j.mee.2017.10.014
H. Kim et al. / Microelectronic Engineering xxx (2017) xxx–xxx
photoresist (PR), the hard mask is etched with a slope of 80° as shown in Fig. 2(a). This is because of the interaction between nitrogen atoms in the Si3N4 layer and acid which is produced and diffused during exposure process as the by-product of SS03A9, called PR poisoning effects [23–25]. It leads to a tail located close to the edge of the exposed area, resulting in the gradual etch slope of 80°. In order to avoid these PR poisoning effects, TDMR-AR87 replaces SS03A9 as a PR. In addition, oxygen plasma treatment is performed to oxidize the Si3N4 layer slightly to minimize the PR poisoning effects. As a result, a pretty steep etch slope of 87°, nearly close to perpendicular, is achieved as shown in Fig. 2(b). After etching the hard mask and the active region, chemical dry etcher (CDE) process is carried out to remove plasma-damaged silicon active region during the previous etch step using tetrafluoromethane (CF4) gas of 50 sccm and oxygen (O2) gas of 30 sccm, suppressing the reduction of carrier lifetime due to the defects formed during the etch step.
3
(a) Tnitride Tpoly-Si n+ doped poly-Si (Gate1) CDE 300 nm
LP-TEOS
SOI BOX
71
3.2. Formation of G1 through CMP After 3.5 nm oxide and 587 nm doped poly-silicon fills that region, CMP process is done. The oxide layer is thermally grown through dry oxidation process at 800 °C for 30 s, and the in-situ phosphorus doped poly-silicon is deposited by LPCVD using silane (SiH4) gas and phosphine (PH3) gas. The CMP process is done for 190 s after that in order to remove G1 stack at the other regions, except G1 region as shown in Fig. 3(a). Here, the nitride layer is used as a stopping layer of CMP process since the slurry used in this study has an excellent selectivity between nitride and silicon (about 1:100). Fig. 3(b) shows the wafer maps representing the remaining thicknesses of the nitride layer and
82
81 67
81
83
406 384
398
Hard mask
411
390
420
80˚
Tnitride [nm]
409
417
PR (SS03A9)
89
83
385
(a)
(b)
86
Tpoly-Si [nm]
Fig. 3. (a) Cross-sectional SEM image after G1 formation. (b) Wafer maps of remaining thickness of nitride layer and poly-silicon layer.
SOI
(b)
PR (TDMR-AR87)
87˚
Hard mask SOI
Fig. 2. Cross-sectional SEM images after patterning depending on PR materials. (a) SS03A9. (b) TDMR-AR87.
poly-silicon depending on the location in a test wafer. They are measured by observing cross-sectional scanning electron microscope (SEM) images for each location. The remaining thickness of the nitride layer which was initially about 100 nm is 67 to 89 nm after the CMP process, and for the poly-silicon layer 384 to 420 nm. The uniformity of the remaining thickness of the nitride and poly-silicon layer is 8.1% and 3.1%, respectively, confirming that high uniformity of each layer even after the CMP process comes from the slurry having a good selectivity between those two layers. 3.3. Removal of hard mask During the removal process of the hard mask, the most import thing is to protect the poly-silicon layer located at G1 region as much as possible so that G1 can fully cover the side of the active region even after the etchback process step for splitting G1 and G2 electrically later. Fig. 4(a) shows an overall view of the removal process in a SEM image. Even though H3PO4 solution in a heated bath is commonly used to strip silicon nitride films, the nitride layer of the hard mask in this study is removed with dry etch process because H3PO4 solution has a relatively poor etch selectivity between silicon nitride and n+ doped polysilicon [26]. The target etching thickness is 130 nm which is over the nitride layer thickness, 100 nm, to remove the layer perfectly all over the
Please cite this article as: H. Kim, et al., Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes, Microelectronic Engineering (2017), https://doi.org/10.1016/j.mee.2017.10.014
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dry etch poly-Si ~ 20 nm
dry etch nitride ~ 100 nm BHF wet etch
poly-silicon active BOX
(a) 500 nm
BHF solution penetration poly-silicon active Fig. 5. (a) Cross-sectional SEM image after the removal of the hard mask. (b) Wafer maps of remaining thickness of poly-silicon layer after fin formation.
(b) 500 nm
Wet-etched Gate ox. & BOX
Fig. 4. Cross-sectional SEM image after hard mask removal step. (a) When successfully done. (b) When BHF solution penetrated into BOX layer.
wafers, leading to the fact that the top 20 nm of poly-silicon layer is etched at the same time during this dry etch process. Then, the lower TEOS layer is removed with buffered HF wet etch process (NH4F: HF = 7:1) which shows good selectivity between silicon and oxide. In fact, very thin oxide and nitride layers, 5 nm and 10 nm, respectively, are placed between the silicon active and the hard mask to prevent the penetration of BHF solution. The gate oxide and BOX layers can be wet-etched if those layers do not block the penetration as shown in Fig. 4(b).
3.5. Gate splitting through CMP and etchback processes After the fin formation, G2 stack comprised of 3.5 nm oxide/5.5 nm nitride/8.6 nm oxide/doped poly-silicon is formed over the fin and G1 region using dry oxidation and LPCVD processes at the same conditions described in previous sections. The CMP process makes a difference in the thickness of doped poly-silicon layer depending on the location, which means that the thickness of the poly-silicon layer deposited over G1 region becomes thinner than over G2 region because the layer is flattened by the CMP process. The later-deposited doped polysilicon acts as G2. Fig. 6, the cross-sectional high resolution transmission electron microscopy (HR-TEM) image, confirms that the two gates, G1
Sidewall (MTO)
3.4. Fin channel formation using sidewall spacer Thin MTO sidewall spacer of 53 nm is formed through the deposition and dry etch process as shown in Fig. 5(a). MTO film is deposited by LPCVD at 782 °C and 350 mTorr using SiH2Cl2 of 40 sccm and N2O of 160 sccm as the precursors. A silicon fin with almost the same width as the MTO sidewall spacer is formed through HBr plasma etch process using the sidewall spacer as a hard mask thanks to the steeply etched hard mask, 88°, as a result of the fine control in the etch slope at the previous step. Fig. 5(b) shows the wafer maps representing the remaining thicknesses of the poly-silicon layer, which would become G1, depending on the location in a test wafer. Because doped poly-silicon is etched at the same time when the fin is formed, a sufficient thickness is required to cover up the silicon active region after dry etch process for the fin formation. Although dry etch process is done, the active region is well surrounded by poly-silicon layer with the minimum thickness (174 nm), which is pretty thicker than the thickness of the active SOI region (100 nm). After that, CDE process is also carried out to remove damaged active region as described in Section 3.1.
Gate2 Gate1 O 3.5 nm
O/N/O 3.5/5.5/8.6 nm
Buried oxide
20 nm
Fig. 6. Cross-sectional TEM image after gate splitting process.
Please cite this article as: H. Kim, et al., Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes, Microelectronic Engineering (2017), https://doi.org/10.1016/j.mee.2017.10.014
H. Kim et al. / Microelectronic Engineering xxx (2017) xxx–xxx
and G2, are finally separated after the CMP and dry etchback process. During the etchback process, MTO sidewall is rarely etched out because of good selectivity of HBr plasma etch process between silicon and silicon oxide. The length of G1 and G2 (LG) is defined at the same time by photolithography and dry etch process with values ranging from 0.5 μm to 5 μm.
5
(a) VD = 1 V LG = 0.5 µm VT window= 4.24 V program (VG2 = 14 V, 200 µs)
erase (VG2 = -14 V, 10 ms)
4. Electrical characteristics Fig. 7(a) shows the transfer characteristics of the fabricated device with LG = 0.5 μm as a function of G2 voltage (VG2) at drain voltage (VD) = 0.1 and 1 V. The VT of the device, defined as VG1 when drain current is at 10−8 A, is increased as decreasing VG2 from 0.4 to −1.4 V (step = 0.2 V), and the amount of VT change (ΔVT) is summarized for 20 different single samples in Fig. 7(b), showing the flexible VT controllability of the devices. The VT modulation rate (dVT/dVG2) of the positive VG2 region (0.87) is pretty lager than that of the negative VG2 region (0.22) because of inverted back-channel by positive VG2 [3]. Similar VT-modulation effects could be obtained by trapping electrons in the nitride layer of G2 stack [13]. Moreover, subthreshold swing (SS) and drain-induced barrier lowering (DIBL) characteristics are calculated and summarized in Fig. 7(c) and (d), respectively. SS and DIBL characteristics are rarely degraded thanks to thick EOT of G2 stack and low G2 controllability. In addition, the non-volatile memory properties of the device as a charge trap flash (CTF) memory cell are investigated. Fig. 8(a) shows the transfer characteristics of G2 having 4.24 V of VT window between programmed and erased states. The program and erase operations are conducted by applying VG2 = 14 and −14 V for 200 μs and 10 ms, respectively. Fig. 8(b) shows the bake retention performance measured at 85 °C. 0.74 V of VT window degradation is obtained after 10,000 s baking measurement, and the expected VT window after 10 years is extracted as 2.33 V, indicating that the device has allowable nonvolatile data
(a)
4.24 V
3.5 V
2.33 V
@Temp. 85 C
Fig. 8. (a) Transfer characteristics of G2 after program and erase operations. (b) Bake retention properties at 85 °C.
(b)
VD = 1 V
EOT(G1/G2) = 3.5/14.8 nm
10 years
(b)
dVT/dVG2 = 0.87 (positive VG2)
VD = 0.1 V dVT/dVG2 = 0.22 (negative VG2) VG2 = 0.4 ~ -1.4 V (step = 0.2 V) LG = 0.5 µm
(c) V
D =1 V LG = 0.5 µm
little degradation
VD = 1 V LG = 0.5 µm
( d)
VD = 1 V LG = 0.5 µm
little degradation
Fig. 7. (a) Transfer characteristics of G1 as a function of VG2. Statistical data of (b) ΔVT, (b) SS, and (c) DIBL as a function of VG2.
Please cite this article as: H. Kim, et al., Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes, Microelectronic Engineering (2017), https://doi.org/10.1016/j.mee.2017.10.014
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retention requirements according to International Technology Roadmap for Semiconductors (ITRS) [27]. 5. Conclusion In summary, we have presented the fabrication method of the asymmetric independent dual-gate FinFETs with different gate stacks as a multi-functional single device. The fin width is controlled by modulating the thickness of sidewall spacer, and the separation of two gates with different gate stacks is achieved CMP processes. The characteristics of the fabricated devices with regard to flexible VT properties and nonvolatile memory functions are measured and analyzed using the asymmetric independent dual-gate structure. It is believed that these results provide the framework for future studies to obtain independent dualgate structured devices for multiple applications with compact fabrication method. Acknowledgements This work was supported by the Center for Integrated Smart Sensors funded by the Ministry of Science and ICT as a Global Frontier Project (CISS-2012M3A6A6054186). References [1] M. Masahara, R. Surdeanu, L. Witters, G. Doornbos, V. Nguyen, C. Vrancken, K. Devriendt, F. Neuilly, E. Kunnen, E. Suzuki, Microelectron. Eng. 84 (2007) 2097–2100. [2] K.-H. Park, S. Cristoloveanu, M. Bawedin, Y. Bae, K.-I. Na, J.-H. Lee, Solid State Electron. 59 (2011) 39–43. [3] M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T. Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, IEEE Trans. Electron Devices 52 (2005) 2046–2053.
[4] Y. Liu, T. Matsukawa, K. Endo, M. Masahara, K. Ishii, H. Yamauchi, J. Tsukada, Y. Ishikawa, E. Suzuki, IEEE Electron Device Lett. 28 (2007) 517–519. [5] M. Masahara, R. Surdeanu, L. Witters, G. Doornbos, V.H. Nguyen, C. Vrancken, K. Devriendt, F. Neuilly, E. Kunnen, M. Jurczak, IEEE Electron Device Lett. 28 (2007) 217–219. [6] C. Kuo, T.-J. King, C. Hu, IEEE Trans. Electron Devices 50 (2003) 2408–2416. [7] M.G. Ertosun, H. Cho, P. Kapur, K.C. Saraswat, IEEE Electron Device Lett. 29 (2008) 615–617. [8] I. Ban, U.E. Avci, U. Shah, C.E. Barns, D.L. Kencke, P. Chang, IEEE Int. Electron Devices Meet. (IEDM) (2006) 573–576. [9] S.-J. Chang, H. Zhou, N. Gong, D.-M. Kang, J.-W. Lim, M. Si, D.Y. Peide, T. Ma, IEEE Electron Device Lett. 38 (2017) 441–444. [10] W. Mizubayashi, K. Fukuda, T. Mori, K. Endo, Y. Liu, T. Matsukawa, S. O'uchi, Y. Ishikawa, S. Migita, Y. Morita, Solid State Electron. 111 (2015) 62–66. [11] T. Poiroux, O. Rozeau, S. Martinie, P. Scheer, S. Puget, M. Jaud, S. El Ghouli, J. Barbé, A. Juge, O. Faynot, IEEE Int. Electron Devices Meet. (IEDM) (2013) 324–327. [12] J.-H. Ahn, J.-Y. Kim, M.-L. Seol, D.J. Baek, Z. Guo, C.-H. Kim, S.-J. Choi, Y.-K. Choi, Appl. Phys. Lett. 102 (2013), 083701. . [13] H. Kim, J. Park, M.-W. Kwon, S. Hwang, B.-G. Park, Jpn. J. Appl. Phys. 55 (2016), 04ED01. . [14] H. Kim, J.-H. Lee, B.-G. Park, Appl. Phys. Express 9 (2016), 084201. . [15] H. Kim, M.-H. Baek, S. Hwang, J.-H. Lee, B.-G. Park, Appl. Phys. Express 10 (2017), 064201. . [16] H. Kim, S. Hwang, J.-H. Lee, B.-G. Park, Jpn. J. Appl. Phys. 56 (2017), 04CE06. . [17] H. Kim, J. Park, M.-W. Kwon, J.-H. Lee, B.-G. Park, IEEE Electron Device Lett. 37 (2016) 249–252. [18] H. Kim, S. Cho, M.-C. Sun, J. Park, S. Hwang, B.-G. Park, J. Semicond. Technol. Sci. 16 (2016) 657–663. [19] H. Kim, J.H. Lee, G. Kim, M.-C. Sun, B.-G. Park, Int. Conf. Solid State Devices Mater. (SSDM) (2012) 322–323. [20] H. Kim, S. Hwang, J. Park, B.-G. Park, Nanotechnology 28 (2017) 405202. [21] Athena User's Manual. , Silvaco Inc., 2012 [22] K. Izumi, M. Doken, H. Ariyoshi, Electron. Lett. 14 (1978) 593. [23] Y. Kawai, A. Otaka, A. Tanaka, T. Matsuda, Jpn. J. Appl. Phys. 33 (1994) 7023. [24] M. Fayolle, J. Torres, G. Passemard, F. Fusalba, G. Fanget, D. Louis, M. Assous, O. Louveau, M. Rivoire, K. Haxaire, Microelectron. Eng. 64 (2002) 35–42. [25] A.A. Lamola, C.R. Szmanda, J.W. Thackeray, Solid State Technol. 34 (1991) 53–61. [26] K.R. Williams, R.S. Muller, J. Microelectromech. Syst. 5 (1996) 256–269. [27] The International Technology Roadmap for Semiconductors (ITRS), Table PIDS7, 2013.
Please cite this article as: H. Kim, et al., Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes, Microelectronic Engineering (2017), https://doi.org/10.1016/j.mee.2017.10.014
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Research paper
Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes Hyungjin Kim a, Min-Chul Sun b, Sungmin Hwang a, Hyun-Min Kim a, Jong-Ho Lee a, Byung-Gook Park a,⁎ a b
Inter-university Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Republic of Korea System LSI, Semiconductor Business Group, Samsung Electronics Co. Ltd., Yongin 17114, Republic of Korea
a r t i c l e
i n f o
Article history: Received 6 September 2017 Received in revised form 1 October 2017 Accepted 22 October 2017 Available online xxxx Keywords: FinFET Asymmetric independent dual-gate Sidewall spacer patterning Chemical-mechanical polishing (CMP) process Multi-functional device
a b s t r a c t In this paper, we present the fabrication method of asymmetric independent dual-gate FinFETs with different gate stack using sidewall spacer patterning and two-step chemical-mechanical polishing (CMP) processes. The fin width is controlled as a result of sidewall spacer patterning. The two-step CMP processes are conducted to separate two gates and to make different gate stacks for each gate, respectively. The fabricated devices can be used for multiple applications by utilizing independent two gates. First of all, the independent two gates offer the flexible threshold voltage modulation properties by applying the second gate (G2) bias with little subthreshold swing degradation. Second, the device can be utilized as a charge trap flash memory cell by trapping electrons in the charge storage layer. These results provide a possible way to fabricate asymmetric independent dual-gate FinFETs having potential as a multi-functional single device. © 2017 Elsevier B.V. All rights reserved.
1. Introduction Metal-oxide-semiconductor field-effect transistors (MOSFETs) with independent dual-gate structure have been widely investigated with multiple applications including flexible threshold voltage (VT) controllability of logic devices, multi-functional memory, and sensor applications [1–12]. However, most of the approaches have been limited in their applications because of the lack of charge storage node and complicated fabrication method. Masahara et al. reported independent double-gate FinFETs with different equivalent oxide thickness (EOT) gate stacks for multi-VT logic devices by applying voltage to the 2nd gate (G2) [1]; however, it is hard to be utilized as a memory device because of the lack of charge storage layer. Park et al. reported double-gate 1T-DRAM cell with ONO buried oxide (BOX) for enhancing retention characteristics of volatile memory function by trapping electrons in the nitride layer [2]; however, it has several issues such as non-self aligned common back-gate structure and complicated fabrication method including sequential n+ polycrystalline Si/O/N/O strip processes with SF6 isotropic dry etch, H3PO4 wet etch, and HF wet etch, respectively. Previously, we reported the applications of asymmetric independent dual-gate FinFET as a multi-VT logic device [13], a volatile and nonvolatile memory device [14–16], and a synaptic device of neuromorphic system [17–20]. In this study, we present the nanofabrication method of asymmetric independent dual-gate FinFET using sidewall spacer
⁎ Corresponding author. E-mail address: [email protected] (B.-G. Park).
patterning and CMP processes. The channel width can be easily scaled by controlling a spacer thickness, and a self-aligned dual-gate with different gate stack is formed at the same time. Using SiN film as a stopping layer in chemical-mechanical polishing (CMP) process offers highly uniform CMP characteristics. For utilizing as a multi-functional memory device, G2 has ONO stack as a charge storage node and the device is based on floating-body structure. The detailed experimental conditions and issues of the key process steps are described and the electrical characteristics of the fabricated devices are analyzed. 2. Process design and fabrication flow In order to fabricate the asymmetric independent dual-gate FinFET with different gate stack, the fabrication sequence follows the process flow shown in Fig. 1. A process simulation tool of Silvaco Inc. (Athena ver. 5.20.0.R 2012) is used to estimate the experimental results more accurately [21]. First, a hard mask stack is deposited and the 1st active patterns are etched as shown in Fig. 1(a). Because two gates are formed in sequence, the active region which contacts G1 is formed first. The hard mask stack is comprised of silicon dioxide (SiO2) and silicon nitride (Si3N4) which is used for selective etching with poly-silicon and stopping layer of CMP process, respectively. Steep etch slope is required because SiO2 sidewall is formed at the region where the hard mask stack is removed. After forming G1 stack, CMP process is done to leave the poly-silicon layer only at the G1 region as shown in Fig. 1(b). The CMP slurry which has good selectivity between doped poly-silicon and Si3N4 is required to protect the height of the hard mask stack, which allows a margin for
https://doi.org/10.1016/j.mee.2017.10.014 0167-9317/© 2017 Elsevier B.V. All rights reserved.
Please cite this article as: H. Kim, et al., Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes, Microelectronic Engineering (2017), https://doi.org/10.1016/j.mee.2017.10.014
2
H. Kim et al. / Microelectronic Engineering xxx (2017) xxx–xxx
Top view
Sectional view Sidewall spacer (MTO) PR
Si3N4 BOX
poly-Si
SiO2
poly-Si PR
Silicon Si3N4
Silicon
BOX
Silicon
(a)
(e) S
n+ doped poly-Si
poly-Si
poly-Si
Gate 1
Fin witdh ~ 40nm
D
Si3N4
BOX
BOX
(b)
poly-Si
(f)
n+ doped poly-Si
n+ doped poly-Si (Gate 2)
Gate 1
Gate 1
Si3N4
(c)
(g)
Sidewall spacer (MTO)
Sidewall spacer (MTO)
poly-Si
G1
D
Sidewall spacer (MTO)
S
G2
Gate 1
Silicon
Gate 2
Gate 1 BOX
BOX
(d)
(h)
Fig. 1. Device fabrication flow. (a) Deposition of hard mask and patterning. (b) Formation of G1 through CMP. (c) Removal of hard mask. (d) MTO sidewall formation. (e) Sidewall cutting. (f) Fin channel formation. (g) G2 stack deposition and CMP. (h) Etchback for gate splitting and gate patterning.
gate splitting process later. And then, the Si3N4 layer is removed with dry etch process due to bad selectivity of phosphoric acid (H3PO4) wet etch process between doped poly-silicon and Si3N4, and the SiO2 layer is removed with hydrogen fluoride (HF) wet etch process having good selectivity between silicon and oxide (Fig. 1(c)). Thin sidewall is formed through deposition and dry etch process of medium temperature chemical vapor deposition oxide (MTO) which has slow deposition rate, hence forming the thin sidewall (Fig. 1(d)). The unnecessary sidewall is removed using HF wet etch process to suppress the parasitic capacitance around G1 region as illustrated in Fig. 1(e). Then, a silicon fin is formed using dry etch process (Fig. 1(f)). During this process, the surface of the 2nd active region is formed. The fin is achieved with little loss of oxide sidewall because hydrogen bromide (HBr) plasma etch process has good selectivity between silicon and SiO2 and the fin width is the same as the thickness of oxide sidewall. After the fin formation, G2 stack comprised of oxide/nitride/oxide/ doped poly-silicon is deposited over the fin and G1 using lowpressure chemical vapor deposition (LPCVD) as shown in Fig. 1(g). The CMP process makes a difference in the thickness of doped polysilicon and this difference separates two gates by dry etchback process (Fig. 1(h)). The gate length is defined at the same time by photolithography and dry etch process.
3. Experimental results 3.1. Deposition of hard mask and patterning First, BF2 + ions for body doping are implanted with a dose of 2 × 1011 and 2 × 1012 cm−2 over a silicon-on-insulator (SOI) wafer with 100 nm SOI layer and 375 nm buried oxide (BOX) layer fabricated by SIMOX technology [22]. A hard mask stack made up of 300 nm oxide and 100 nm nitride is deposited, and all the layers including SOI and the hard mask at G1 region are etched. The purpose of the oxide and nitride layers comprising the hard mask is selective etching with polysilicon layer using HF wet etch process and stopping layer of CMP process, respectively. The oxide layer is deposited by LPCVD using tetraethoxysilane (Si(OC2H5)4, TEOS) gas at 710 °C and 250 mTorr, and the nitride layer is deposited by LPCVD in an ambient of dichlorosilane (SiH2Cl2) of 30 sccm and ammonia (NH3) of 100 sccm at 785 °C and 200 mTorr. At the etch process after then, it is very important to obtain a steep etch slope because it is transmitted at the angle of the sidewall spacer for fin channel formation. If the hard mask is etched gradually, the width of a fin channel would be thicker than the spacer thickness, which means the channel width cannot be controlled finely. When SS03A9, which is based on phenol formaldehyde resin, is used as a
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H. Kim et al. / Microelectronic Engineering xxx (2017) xxx–xxx
photoresist (PR), the hard mask is etched with a slope of 80° as shown in Fig. 2(a). This is because of the interaction between nitrogen atoms in the Si3N4 layer and acid which is produced and diffused during exposure process as the by-product of SS03A9, called PR poisoning effects [23–25]. It leads to a tail located close to the edge of the exposed area, resulting in the gradual etch slope of 80°. In order to avoid these PR poisoning effects, TDMR-AR87 replaces SS03A9 as a PR. In addition, oxygen plasma treatment is performed to oxidize the Si3N4 layer slightly to minimize the PR poisoning effects. As a result, a pretty steep etch slope of 87°, nearly close to perpendicular, is achieved as shown in Fig. 2(b). After etching the hard mask and the active region, chemical dry etcher (CDE) process is carried out to remove plasma-damaged silicon active region during the previous etch step using tetrafluoromethane (CF4) gas of 50 sccm and oxygen (O2) gas of 30 sccm, suppressing the reduction of carrier lifetime due to the defects formed during the etch step.
3
(a) Tnitride Tpoly-Si n+ doped poly-Si (Gate1) CDE 300 nm
LP-TEOS
SOI BOX
71
3.2. Formation of G1 through CMP After 3.5 nm oxide and 587 nm doped poly-silicon fills that region, CMP process is done. The oxide layer is thermally grown through dry oxidation process at 800 °C for 30 s, and the in-situ phosphorus doped poly-silicon is deposited by LPCVD using silane (SiH4) gas and phosphine (PH3) gas. The CMP process is done for 190 s after that in order to remove G1 stack at the other regions, except G1 region as shown in Fig. 3(a). Here, the nitride layer is used as a stopping layer of CMP process since the slurry used in this study has an excellent selectivity between nitride and silicon (about 1:100). Fig. 3(b) shows the wafer maps representing the remaining thicknesses of the nitride layer and
82
81 67
81
83
406 384
398
Hard mask
411
390
420
80˚
Tnitride [nm]
409
417
PR (SS03A9)
89
83
385
(a)
(b)
86
Tpoly-Si [nm]
Fig. 3. (a) Cross-sectional SEM image after G1 formation. (b) Wafer maps of remaining thickness of nitride layer and poly-silicon layer.
SOI
(b)
PR (TDMR-AR87)
87˚
Hard mask SOI
Fig. 2. Cross-sectional SEM images after patterning depending on PR materials. (a) SS03A9. (b) TDMR-AR87.
poly-silicon depending on the location in a test wafer. They are measured by observing cross-sectional scanning electron microscope (SEM) images for each location. The remaining thickness of the nitride layer which was initially about 100 nm is 67 to 89 nm after the CMP process, and for the poly-silicon layer 384 to 420 nm. The uniformity of the remaining thickness of the nitride and poly-silicon layer is 8.1% and 3.1%, respectively, confirming that high uniformity of each layer even after the CMP process comes from the slurry having a good selectivity between those two layers. 3.3. Removal of hard mask During the removal process of the hard mask, the most import thing is to protect the poly-silicon layer located at G1 region as much as possible so that G1 can fully cover the side of the active region even after the etchback process step for splitting G1 and G2 electrically later. Fig. 4(a) shows an overall view of the removal process in a SEM image. Even though H3PO4 solution in a heated bath is commonly used to strip silicon nitride films, the nitride layer of the hard mask in this study is removed with dry etch process because H3PO4 solution has a relatively poor etch selectivity between silicon nitride and n+ doped polysilicon [26]. The target etching thickness is 130 nm which is over the nitride layer thickness, 100 nm, to remove the layer perfectly all over the
Please cite this article as: H. Kim, et al., Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes, Microelectronic Engineering (2017), https://doi.org/10.1016/j.mee.2017.10.014
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H. Kim et al. / Microelectronic Engineering xxx (2017) xxx–xxx
dry etch poly-Si ~ 20 nm
dry etch nitride ~ 100 nm BHF wet etch
poly-silicon active BOX
(a) 500 nm
BHF solution penetration poly-silicon active Fig. 5. (a) Cross-sectional SEM image after the removal of the hard mask. (b) Wafer maps of remaining thickness of poly-silicon layer after fin formation.
(b) 500 nm
Wet-etched Gate ox. & BOX
Fig. 4. Cross-sectional SEM image after hard mask removal step. (a) When successfully done. (b) When BHF solution penetrated into BOX layer.
wafers, leading to the fact that the top 20 nm of poly-silicon layer is etched at the same time during this dry etch process. Then, the lower TEOS layer is removed with buffered HF wet etch process (NH4F: HF = 7:1) which shows good selectivity between silicon and oxide. In fact, very thin oxide and nitride layers, 5 nm and 10 nm, respectively, are placed between the silicon active and the hard mask to prevent the penetration of BHF solution. The gate oxide and BOX layers can be wet-etched if those layers do not block the penetration as shown in Fig. 4(b).
3.5. Gate splitting through CMP and etchback processes After the fin formation, G2 stack comprised of 3.5 nm oxide/5.5 nm nitride/8.6 nm oxide/doped poly-silicon is formed over the fin and G1 region using dry oxidation and LPCVD processes at the same conditions described in previous sections. The CMP process makes a difference in the thickness of doped poly-silicon layer depending on the location, which means that the thickness of the poly-silicon layer deposited over G1 region becomes thinner than over G2 region because the layer is flattened by the CMP process. The later-deposited doped polysilicon acts as G2. Fig. 6, the cross-sectional high resolution transmission electron microscopy (HR-TEM) image, confirms that the two gates, G1
Sidewall (MTO)
3.4. Fin channel formation using sidewall spacer Thin MTO sidewall spacer of 53 nm is formed through the deposition and dry etch process as shown in Fig. 5(a). MTO film is deposited by LPCVD at 782 °C and 350 mTorr using SiH2Cl2 of 40 sccm and N2O of 160 sccm as the precursors. A silicon fin with almost the same width as the MTO sidewall spacer is formed through HBr plasma etch process using the sidewall spacer as a hard mask thanks to the steeply etched hard mask, 88°, as a result of the fine control in the etch slope at the previous step. Fig. 5(b) shows the wafer maps representing the remaining thicknesses of the poly-silicon layer, which would become G1, depending on the location in a test wafer. Because doped poly-silicon is etched at the same time when the fin is formed, a sufficient thickness is required to cover up the silicon active region after dry etch process for the fin formation. Although dry etch process is done, the active region is well surrounded by poly-silicon layer with the minimum thickness (174 nm), which is pretty thicker than the thickness of the active SOI region (100 nm). After that, CDE process is also carried out to remove damaged active region as described in Section 3.1.
Gate2 Gate1 O 3.5 nm
O/N/O 3.5/5.5/8.6 nm
Buried oxide
20 nm
Fig. 6. Cross-sectional TEM image after gate splitting process.
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H. Kim et al. / Microelectronic Engineering xxx (2017) xxx–xxx
and G2, are finally separated after the CMP and dry etchback process. During the etchback process, MTO sidewall is rarely etched out because of good selectivity of HBr plasma etch process between silicon and silicon oxide. The length of G1 and G2 (LG) is defined at the same time by photolithography and dry etch process with values ranging from 0.5 μm to 5 μm.
5
(a) VD = 1 V LG = 0.5 µm VT window= 4.24 V program (VG2 = 14 V, 200 µs)
erase (VG2 = -14 V, 10 ms)
4. Electrical characteristics Fig. 7(a) shows the transfer characteristics of the fabricated device with LG = 0.5 μm as a function of G2 voltage (VG2) at drain voltage (VD) = 0.1 and 1 V. The VT of the device, defined as VG1 when drain current is at 10−8 A, is increased as decreasing VG2 from 0.4 to −1.4 V (step = 0.2 V), and the amount of VT change (ΔVT) is summarized for 20 different single samples in Fig. 7(b), showing the flexible VT controllability of the devices. The VT modulation rate (dVT/dVG2) of the positive VG2 region (0.87) is pretty lager than that of the negative VG2 region (0.22) because of inverted back-channel by positive VG2 [3]. Similar VT-modulation effects could be obtained by trapping electrons in the nitride layer of G2 stack [13]. Moreover, subthreshold swing (SS) and drain-induced barrier lowering (DIBL) characteristics are calculated and summarized in Fig. 7(c) and (d), respectively. SS and DIBL characteristics are rarely degraded thanks to thick EOT of G2 stack and low G2 controllability. In addition, the non-volatile memory properties of the device as a charge trap flash (CTF) memory cell are investigated. Fig. 8(a) shows the transfer characteristics of G2 having 4.24 V of VT window between programmed and erased states. The program and erase operations are conducted by applying VG2 = 14 and −14 V for 200 μs and 10 ms, respectively. Fig. 8(b) shows the bake retention performance measured at 85 °C. 0.74 V of VT window degradation is obtained after 10,000 s baking measurement, and the expected VT window after 10 years is extracted as 2.33 V, indicating that the device has allowable nonvolatile data
(a)
4.24 V
3.5 V
2.33 V
@Temp. 85 C
Fig. 8. (a) Transfer characteristics of G2 after program and erase operations. (b) Bake retention properties at 85 °C.
(b)
VD = 1 V
EOT(G1/G2) = 3.5/14.8 nm
10 years
(b)
dVT/dVG2 = 0.87 (positive VG2)
VD = 0.1 V dVT/dVG2 = 0.22 (negative VG2) VG2 = 0.4 ~ -1.4 V (step = 0.2 V) LG = 0.5 µm
(c) V
D =1 V LG = 0.5 µm
little degradation
VD = 1 V LG = 0.5 µm
( d)
VD = 1 V LG = 0.5 µm
little degradation
Fig. 7. (a) Transfer characteristics of G1 as a function of VG2. Statistical data of (b) ΔVT, (b) SS, and (c) DIBL as a function of VG2.
Please cite this article as: H. Kim, et al., Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes, Microelectronic Engineering (2017), https://doi.org/10.1016/j.mee.2017.10.014
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retention requirements according to International Technology Roadmap for Semiconductors (ITRS) [27]. 5. Conclusion In summary, we have presented the fabrication method of the asymmetric independent dual-gate FinFETs with different gate stacks as a multi-functional single device. The fin width is controlled by modulating the thickness of sidewall spacer, and the separation of two gates with different gate stacks is achieved CMP processes. The characteristics of the fabricated devices with regard to flexible VT properties and nonvolatile memory functions are measured and analyzed using the asymmetric independent dual-gate structure. It is believed that these results provide the framework for future studies to obtain independent dualgate structured devices for multiple applications with compact fabrication method. Acknowledgements This work was supported by the Center for Integrated Smart Sensors funded by the Ministry of Science and ICT as a Global Frontier Project (CISS-2012M3A6A6054186). References [1] M. Masahara, R. Surdeanu, L. Witters, G. Doornbos, V. Nguyen, C. Vrancken, K. Devriendt, F. Neuilly, E. Kunnen, E. Suzuki, Microelectron. Eng. 84 (2007) 2097–2100. [2] K.-H. Park, S. Cristoloveanu, M. Bawedin, Y. Bae, K.-I. Na, J.-H. Lee, Solid State Electron. 59 (2011) 39–43. [3] M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T. Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, IEEE Trans. Electron Devices 52 (2005) 2046–2053.
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Please cite this article as: H. Kim, et al., Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes, Microelectronic Engineering (2017), https://doi.org/10.1016/j.mee.2017.10.014