Fabrication of halfmicron MOSFETs by means of x-ray lithography

Microelectronic Engineering 6 (1987) 215-220 North-Holland

215

Fabrication of halfmicron MOSFETs by means of X-Ray lithography

V. Lauer,

F.Bauer +, J. Korec ++, H.-L. Huber*,

P. Balk

I n s t i t u t e of S e m i c o n d u c t o r E l e c t r o n i c s Aachen Technical University D-5100 Aachen, FRG * Fraunhofer-lnstitut for Mikrostrukturtechnik D-1000 Berlin, FRG

M O S F E T s w i t h e f f e c t i v e channel lengths d o w n to 0.3 ~m have b e e n realized using x-ray lithography. To determine process parameters for device optimization two dimensional process and device modeling was employed. In addition, ring o s c i l l a t o r s w i t h d i f f e r e n t n u m b e r s of stages were f a b r i c a t e d to e v a l u a t e the p e r f o r m a n c e of this technology.

I.

INTRODUCTION

X-ray lithography using synchroton radiation provides both high resolution down to 0.3 #m line and space and process advantages for the application in circuit p r o d u c t i o n [i]. Most of the r e q u i r e m e n t s on m a s k t e c h n o l o g y are f u l f i l l e d including fine line patterning, mechanical stability and flatness, optical and x-ray transparency and pattern position accuracy [2,3]. Improvements in resist development lead to novolak-based systems, which meet all the requirements of a submicron-single-layer resist t e c h n o l o g y [4]. The aim of this p a p e r is to demonstrate the performance of x-ray lithography for fabrication of half-micron MOSFETs with minimum short channel behavior. This requires a specific modified process technology, using thin gate oxide and shallow junction depth, which was developed on the base of process simulation and device modeling. Final measurements of half-micron MOSFETs and ring oscillators show high speed and low power dissipation as an additional feature of the applied technology.

2.

LITHOGRAPHIC

PROCEDURE

For device f a b r i c a t i o n a mix and m a t c h l i t h o g r a p h y was used. Most of the l i t h o g r a p h y steps, i n c l u d i n g those for the LOCOS process, e n h a n c e m e n t and depletion threshold voltage adjust, contact hole opening and metallization were c a r r i e d out by deep UV c o n t a c t p r i n t i n g (Carl SOss, MJB 3 HP UV 300). X - r a y lithography was employed for the definition of the polysilicon gates, because only the gate level provides submicron feature sizes.

+ Now with Brown Boveri Corporation, Baden, Switzerland ++ Now with AEG Forschungslabor, Frankfurt, FRG This w o r k has b e e n s u p p o r t e d by the D e p a r t m e n t of R e s e a r c h and T e c h n o l o g y of the Federal R e p u b l i c of Germany. The authors alone are r e s p o n s i b l e for the contents•

0167-9317/87/$3.50 © 1987, ElsevierSciencePublishers B.V. (North-Holland)

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I~ Lauer et al. / Fabrication o f halfmicron MOSFETs

For both optical and X-ray lithography novolak resists were used to guarantee a sufficient technological stability. In case of UV-exposure different AZ 4000 resists and for X-ray patterning HPR 204 seemed to be good approaches for our application. Fig.l shows the performance of X-ray lithography for pattern definition. S u b h a l f m i c r o n r e s i s t lines (d = 1.5 #m) are r u n n i n g across s i l i c o n d i o x i d e steps w i t h a t h i c k n e s s of a b o u t 0.5 #m w i t h o u t any s i g n i f i c a n t linewidth variations.

FIGURE i M i c r o g r a p h of submicron resist features (HPR 204) across silicon d i o x i d e steps. The x - r a y lithography was performed under standard exposure conditions: BESSY 754 MeV Wavelength: 0.3 - 1.0 ~m Proximity: 50 #m

X - r a y m a s k s were f a b r i c a t e d by a t e c h n o l o g y b a s e d on s i l i c o n m e m b r a n e s and electroplated gold windows. The primary pattern definition is performed by an e l e c t r o n b e a m w r i t i n g s y s t e m f o l l o w e d b y s e v e r a l RIE steps and a final g o l d e l e c t r o p l a t i n g p r o c e d u r e . T h e s e m a s t e r m a s k s were d u p l i c a t e d by an X - r a y c o p y i n g p r o c e s s in a single l a y e r r e s i s t and f i l l i n g up the r e s i s t s t e n c i l again by gold electroplating. As s h o w n b y W i n d b r a k e et al. [2] m a s t e r m a s k f a b r i c a t i o n in c o m b i n a t i o n w i t h mask copying can achieve 0.3 #m critical dimension with a total error budget of ± 50 nm. The pattern placement accuracy during the entire mask fabrication is b e t t e r than 0.2 #m as a 3a v a l u e [3]. For f i n i s h i n g the w o r k mask, the r e s i s t pattern and the plating base have to be removed, in order to gain a sufficient optical transparency, which is needed for the optical alignment system of the X-ray stepper. The repeatability of mask recognition of the stepper alignment is b e t t e r than i0 nm and an o v e r l a y a c c u r a c y of a b o u t 50 nm is a c h i e v a b l e . A l t o g e t h e r the total o v e r l a y b u d g e t i n c l u d i n g m a s k d i s t o r t i o n and a l i g n m e n t a c c u r a c y of 0.5 #m for m a x i m u m d e v i a t i o n of two m a s k levels can be e a s i l y fulfilled [3].

V. Lauer et al. / Fabrication o f halfmicron MOSFETs

3.

217

DEVICE MODELING AND PROCESSING

P r o c e s s (SUPREM) and d e v i c e (MINIMOS) m o d e l i n g was e m p l o y e d to e x t e n d a l#m NMOS process to the submicron range. Two conflicting boundary conditions [5] had to be considered: minimum short channel effects and maximum device stability. Implantation profiles were optimized for inverters consisting of enhancement mode transistors with Leff= 0.5 ~m and depletion mode devices with Leff= 0.9 #m. The i n t e r n a l e l e c t r i c a l field, w h i c h is r e s p o n s i b l e for a v a l a n c h e b r e a k d o w n , c a r r i e r i n j e c t i o n in the gate o x i d e and for the d e g r a d a t i o n of threshold and transconductance in submicron devices, was reduced by fixing the power supply to 3V. In this manner it was possible to avoid specially tailored p r o f i l e s like l i g h t l y d o p e d (LDD)[6] or d o u b l e d i f f u s e d d r a i n ( D I - L D D ) [ 7 ] . Table I summarizes the essential process steps. The starting substrates are ptype (100)-oriented silicon wafers with a resistivity of 12-17 ~cm.

Table I Fabrication sequence 1. 2. 3. 4 5 6 7 8 9 I0 ii 12 13 14 15

Registration mark formation Device area definition Ion implant B Selective field oxidation Sacrificial oxide growth Channel implant B/As (enhancement/depletion) Gate oxidation (1000°C, dry 02) Amorphous silicon deposition Gate electrode definition Source/drain implant As CVD oxide deposition Crystallization and dopant activation (900°C) Contact hole definition Substrate hole definition and ion implant B Ti/AI metallization and PMA

Per chip six transistors of each type with channel lengths varying from 0.8 to 1.8 # m for d e p l e t i o n m o d e and 0.5 to 1.2 ~ m for e n h a n c e m e n t m o d e d e v i c e s w e r e realized. Channel width of all devices was i0 ~m. For comparison an additional set of devices was prepared using e-beam direct writing for this step.

4.

RESULTS

The a b i l i t y of the t e c h n o l o g y u s e d for m a n u f a c t u r i n g d e v i c e s t r u c t u r e s of predetermined dimensions is demonstrated in Fig.2. This figure shows the gate r e g i o n of a 0.5 ~m e n h a n c e m e n t mode MOSFET. The o p t i m i z e d d e v i c e s (Lef f- 0.5 #m) h a v e e x c e l l e n t e l e c t r i c a l c h a r a c t e r i s t i c s . Fig.3 shows the subthreshold current of an enhancement transistor with Leff= 0.5 ~m and W= I0 #m for different drain voltages. It may be seen that the curves are essentially insensitive to this parameter. This result indicates negligible short channel effects.

218

V. Lauer et al. 'Fabrication o f halfmicron MOSFETs

0.51Jm Gate region

FIGURE 2 of M O S F E T with Leff=

0.3#m

ID (A) IE-03 V0

decodQ /dlv

IE-13-~,-b.:..~_~.y_.__L -.5000 0

2.000 VO

,2500/d~v

(

V)

FIGURE 3 S u b t h r e s h o l d behavior of enhancement transistor with Leff= 0.5 #m, W= 10#m (0.I V < V D < 2.6 V, VSS = 0 V)

As m e n t i o n e d before, the shortest geometrical channel length used in this study w a s 0.5 ~m. T h e c o r r e s p o n d i n g IV-curves (fig.4) demonstrate that even these devices exhibit acceptable current voltage characteristics. Typical values for subdiffusion of A L = 0 . 1 9 #m a n d an o v e r a l l s e r i e s r e s i s t a n c e of 24 ~ w e r e d e t e r m i n e d u s i n g a m e t h o d a f t e r P e n g et a l . [ 8 ] . F o r t h i s r e a s o n the s h o r t e s t devices h a d an effective channel length of about 0.3 #m. Carrier mobility was m e a s u r e d w i t h an approach proposed by Hao et al.[9]. Values of #D= 530 cm2/Vs for the depletion mode (Leff= 0.9 #m) and #E = 425 cm2/Vs for enhancement mode ( L e f f = 0 . 5 ~m) t r a n s i s t o r s are c h a r a c t e r i s t i c for d e v i c e s in the s u b m i c r o n range [i0]. The somewhat higher value for the depletion MOSFET is probably due to the b u r i e d channel. Mobility degradation with d e c r e a s i n g channel length was not observed. Very similar results were obtained on devices structured by eb e a m direct writing.

V. Lauer et al. / Fabrication o f halfmicron MOSFETs

IO

219

(mA)

6.000

.6000 /dlv

JG

.OOO0 .0000

VO

ID-U D characteristic (Leff=

0.3#m,

.5500/div

FIGURE 4 of n-channel

( V)

5.500

enhancement

transistor

0 V < V G < 5 V, VSS = 0 V)

In o r d e r to g e t i n f o r m a t i o n a b o u t the d y n a m i c p o t e n t i a l of t h e d e s c r i b e d t e c h n o l o g y ring oscillators were designed with 0.5 #m effective channel length f o r the d r i v e r a n d 0.9 # m f o r the l o a d t r a n s i s t o r . B e c a u s e it is w e l l k n o w n that ring oscillators w i t h a l a r g e n u m b e r of s t a g e s t e n d to g e n e r a t e h i g h e r harmonics [ii] e a c h c h i p c o n t a i n e d 4 o s c i l l a t o r s w i t h d i f f e r e n t n u m b e r s of stages (101/51/25/13). A m i c r o p h o t o g r a p h of such a chip can be seen in fig. 5. The first results m e a s u r e d on oscillators w h i c h have b e e n f a b r i c a t e d using xray l i t h o g r a p h y i n d i c a t e d a p r o p a g a t i o n delay time of 135 ps. A s e c o n d set of devices was r e a l i z e d by means of e-beam direct w r i t i n g w i t h improved contact hole s t r u c t u r i n g and metallization. The output w a v e f o r m for the 51-stage oscillator fabricated in t h i s m a n n e r is s h o w n in Fig. 6. T h i s d e v i c e h a s a t y p i c a l inverter p r o p a g a t i o n delay time of 87 ps and a power delay p r o d u c t of 17.5 fJ.

Microphotograph

FIGURE 5 of ring oscillator chip

(101/51/25/13

stages)

V.. Lauer et al. I Fabrication o f halfmicron MOSFETs

220

A

& 1 !

/ t/ ,/

V

A

f V

i

A

/ f V

V

!~ ff i i

f

v

FIGURE 6 Output waveform of ring oscillator with 51 stages

5.

CONCLUSIONS

Submicrometer MOSFETs with Lef f ranging from 1.6 to 0.3 #m have been realized u s i n g x - r a y l i t h o g r a p h y for gate definition. Our results c l e a r l y show the ability of this technique for device fabrication. Excellent pattern definition and o v e r l a y a c c u r a c y are the two major features w h i c h have to be emphasized. The technology for the fabrication of these devices has been optimized employing n u m e r i c a l simulations. In addition, o s c i l l a t o r s f a b r i c a t e d using this technology exhibit very high speed and low power dissipation.

REFERENCES: [I]

A. Heuberger in Microcircuit Engineering, Ed. H.W. Lehmann, Ch. Bleiker (NorthHolland, Amsterdam,1986) [2] W. W i n d b r a c k e et al. in M i c r o c i r c u i t Engineering, Ed. H.W. Lehmann, Ch. Bleiker (NorthHolland, Amsterdam,1986) [3] H. Betz et al. in Microcircuit Engineering, Ed. H.W. Lehmann, Ch. Bleiker (NorthHolland, Amsterdam,1986) [4] K.-F. D6ssel in Microcircuit Engineering, Ed. H.W. Lehmann, Ch. Bleiker (NorthHolland, Amsterdam,1986) [5] F. Bauer and P. Balk, Solid-State Electronics, 29 (1986) 797 [6] S. Ogura, C.F. Codella, N. Rovedo, J.F. Sheppard, J. Riseman, IEDM Techn. Digest (1982) 781 [7] E. Takeda, H. Kume, Y. Nakagome, T. Makino, A. Shimizu, S. Asai, IEEE Trans. Electron Devices, ED-30 (1983) 652 [8] C. Hao, B. Cabon-Till, S. Cristoloveanu, G. Ghibaudo, Solid-St. Electronics, 28 (1985) 1025 [9] K.-L. Peng, S.-Y. Oh, M.A. Afromowitz, J.L. Moll, IEEE El. Device Letters, EDL-5 (1984) 473 [I0] L. Manchanda, IEEE Electron Dev. Lett., EDL-5 (1984) 470 [ii] N. Sasaki, IEEE Trans. Electron Devices, ED-29 (1982) 280