- Email: [email protected]
Fabrication of MOSFETs by 3D soft UV-nanoimprint
Microelectronic Engineering 97 (2012) 85–88
Contents lists available at SciVerse ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Fabrication of MOSFETs by 3D soft UV-nanoimprint Namil Koo ⇑, Mathias Schmidt, Thomas Mollenhauer, Christian Moormann, Florian Schlachter, Heinrich Kurz Advanced Microelectronic Center Aachen (AMICA), AMO GmbH, Otto-Blumenthal-Str. 25, 52074 Aachen, Germany
a r t i c l e
i n f o
Article history: Available online 31 May 2012 Keywords: Soft UV-NIL MOSFET 3D Imprint Self-alignment Flexible mold
a b s t r a c t So far, metal oxide semiconductor field-effect transistors (MOSFETs) have been fabricated using either optical lithography or imprint lithography with an alignment step between the different layers. Here, we report on the new process for the fabrication of top gate MOSFETs where the number of fabrication steps is reduced significantly. The 3D topography of a top gate MOSFET using as primary master is inversely replicated into a flexible mold that is subsequently transferred to the imprint resist layer. By reactive ion etching, this self aligned 3D pattern is transferred into the underlying semiconductor stack creating functional transistor structures. Preliminary electrical characterizations demonstrate fully operational transistor functions. Ó 2012 Elsevier B.V. All rights reserved.
1. Introduction The metal-oxide-semiconductor field-effect transistor (MOSFET) is the workhorse of the semiconductor industry. It is usually fabricated using one optical lithography step for the MESA layer and subsequent optical lithography step for the gate layer aligned to the MESA layer. The entry points for industrial applications are in all cases low cost and high throughput in fabrication. Therefore, UV-nanoimprint has been proposed as an alternative lithography method for LCD [1], photonics [2], and nano-electronics [3,4]. The fabrication of MOSFETs by imprint lithography has been already shown in Refs. [3,4]. Yet, using this method still requires a cost intensive alignment step between subsequent layers prohibiting the use of soft molds and high throughput for high volume production; thus it would be desirable to eliminate this alignment step. Soft UV-nanoimprint (soft UV-NIL) utilizes a flexible imprint mold for the pattern-replication [5,6]. Soft UV-NIL allows simple generation of a 3D topography into the imprint mold exhibiting all height information required for the replication of different layers. Similar concepts were introduced [7,8]. In this contribution a 3D UV-nanoimprint process using a flexible mold is presented that allows the fabrication of a top gate MOSFET in one lithography step. One imprint step is required for the definition of the MESA and gate layer; subsequently the resist topography is transferred into the substrate with only one reactive ion etching. Mold distortions caused by the imprint pressure [9] for multilevel imprinting are not an issue anymore using this novel 3D
⇑ Corresponding author. E-mail addresses: [email protected] (N. Koo), [email protected] (C. Moormann). 0167-9317/$ - see front matter Ó 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2012.05.015
imprint process. Challenging alignment step for the fabrication of a top gate MOSFET can be avoided by this method. 2. Experiment 2.1. Master fabrication A silicon on insulator (SOI) top gate N-MOSFET device serves as a master for the fabrication of a flexible 3D imprint mold. The master architecture, based on a gate first process device developed by AMO GmbH, that is described in detail in Ref. [10] and illustrated in Fig. 1a. The mesa of the fabricated N-MOSFET has a height of 90 nm. The thickness of the gate oxide and the gate is 10 and 120 nm, respectively (Fig. 1b). A thin anti-adhesion layer was deposited onto the master. The thickness of the layer is about 10 nm. The anti-adhesion layer allows an easy separation of the flexible mold from the surface of the master during the mold fabrication process, preventing damage of the imprint mold. 2.2. Fabrication of flexible molds Polydimethylsiloxane (PDMS, Sylgard 184, Dow Corning) was used for the fabrication of a flexible mold. The base material of PDMS was mixed with its curing agent in a ratio of 10:1. This liquid mixture was poured onto the surface of the master, and then degassed in a vacuum chamber for 60 min. This liquid mixture was thermally cured on a hotplate at 120 °C for 30 min, and finally separated from the master. Now this 3D profile was replicated inversely in a flexible PDMS mold that is illustrated in Fig. 1c. This is a prerequisite for the demonstration of a MOSFET without an alignment step by 3D soft UV-NIL.
86
N. Koo et al. / Microelectronic Engineering 97 (2012) 85–88
Fig. 1. Illustration of the used master and the prepared flexible imprint mold. 3D illustration of the master (a), cross-section view of the master (b), and cross-section view of the flexible imprint mold prepared with the master (c).
2.3. Preparation of a substrate for the fabrication of a top gate MOSFET by 3D soft UV-NIL
2.4. Process flow for the fabrication of a top gate MOSFET by 3D soft UV-NIL
For the direct fabrication of a top gate field-effect transistor by 3D soft UV-NIL, silicon dioxide (t = 10 nm) for the gate oxide was thermally grown on a SOI wafer with 100 nm buried oxide (BOX) and 50 nm top silicon (p-type Bor, NA = 1e16 cm 3) which was reduced to 45 nm during the oxidation process. Afterward, 100 nm polysilicon for the gate was deposited by thermal growth in a LPCVD furnace. The fabricated material stack is illustrated in Fig. 2a.
For the 3D imprint process, a low viscose UV curable imprint resist, AMONIL MMS4 (AMO GmbH, Germany), was used. The low viscosity (50 mPa s at RT) allows fast filling of mold cavities with resist at low imprint pressures. The curing dose of AMONIL is about 2 J/cm2. An optimized EVG 620 imprint tool was used. At first, the imprint resist was spun on the prepared substrate with a thickness of about 200 nm (Fig. 2a). The PDMS mold was pressed into the
Fig. 2. Process flow for the direct fabrication of a top gate field effect transistor by 3D soft UV-NIL. Stack substrate information for the demonstration of a FET (a), resist information for the FET on the stack after imprinting (b), pattern-transfer into the stack after RIE process (c), scattering oxide deposition after removal of the resist layer for the implantation (d), As ion-implantation (e), and removing the scattering oxide layer and rapid thermal annealing (f).
N. Koo et al. / Microelectronic Engineering 97 (2012) 85–88
87
liquid resist layer with an imprint pressure of 200 mbar, filling the 3D cavities of the mold with the liquid resist. After resist curing via UV exposure, the PDMS mold was separated from the cured resist layer. The resist layer on the substrate now exhibited the patterninformation from the primary master (Fig. 2b). Subsequently, this resist pattern was transferred to the material stack using a HBr based RIE process. During this process, the residual layer was removed firstly. Then, the 3D patterns were transferred to the substrate. This HBr based process etches polysilicon as well as silicon dioxide. Once the gate oxide had been completely etched, oxygen gas was added to the gas mixture to attain a high selectivity of the etch rate of silicon (r 160 nm/min) towards the etch rate of silicon dioxide (r 0 nm/min). This process is to finalize the remaining MESA silicon etching and to stop on the box oxide. In this step, the resist was consumed to transfer the complete 3D resist pattern into the underlying material stack of the prepared substrate (Fig. 2c). Resist remaining on the polysilicon gate was removed using acetone and a mixture of sulfuric acid and hydrogen peroxide with a ratio of 1:1. The 30 nm of scattering oxide was deposited on the patterned substrate by thermal evaporation (Fig. 2d) before As-implantation (dose 2e16 cm 2, 45 keV) process (Fig. 2e). Activation was carried out by rapid thermal annealing process at 950 °C for 15 s. Subsequently, the scattering oxide was removed using 5% diluted hydrofluoric acid (HF). Fig. 2f shows the fabricated top gate MOSFET. 3. Results and discussion A comparison of the process steps for the fabrication of a top gate MOSFET by conventional optical lithography and 3D soft UV-NIL is shown in Fig. 3. Conventional optical lithography requires 15 process steps while self-aligned 3D soft UV-NIL reduces the number of process steps to nine. The functionality of top gate MOSFETs fabricated by 3D soft UVNIL has been tested in preliminary experiments. The SEM image of the fabricated MOSFET is depicted in Fig. 4a. The output characteristic shown in Fig. 4b exhibits the well known transistor regimes; both linear- and saturation region are successfully developed even in this very preliminary state. Since the gate oxide might be damaged
Fig. 4. SEM micrograph of a fabricated top gate transistor (a), output characteristic of the fabricated MOSFET (b) and (c).
during HF process, the gate leakage current is too high (Fig. 4c). Therefore no perfect saturation region was displayed in Fig. 4b. By using a RIE for the removal of scattering oxide instead of HF process, the electrical performance of the devices could be improved. 4. Conclusion
Fig. 3. Comparison of process flow for the fabrication of a top gate MOSFET by conventional optical lithography and 3D soft UV-NIL.
Fully functional top gate MOSFETs were fabricated using 3D UVNIL where all the necessary architecture of 3D transistor is replicated with only one lithographic step. This 3D UV-NIL approach reduces the process steps required for the fabrication of a MOSFET from 15 to 9. The 3D lithography concept presented here in the case of MOSFETS exploits specific strengths of soft UV-NIL. By integrating the alignment into the imprint mold a 3D transistor
88
N. Koo et al. / Microelectronic Engineering 97 (2012) 85–88
geometry was created in a single lithography step, replacing complicated alignment technology by self-alignment. Thus, this approach bears a high potential for low cost fabrication of 3D electronic components in displays and organic electronics where more than one layer has to be structured. Acknowledgement This work was funded as part of the FP7 IP Project ‘‘NapaNIL’’ Grant Agreement No. 214249. References [1] J.H. Jeong, K.D. Kim, D.G. Choi, J.H. Choi, E.S. Lee, Proc. SPIE 6517 (2007) 651716. [2] U. Plachetka, N. Koo, T. Wahlbrink, J. Bolten, M. Waldow, T. Plötzing, M. Först, H. Kurz, IEEE Photonics Technol. Lett. 20 (2006) 490.
[3] W. Zhang, S.Y. Chou, Appl. Phys. Lett. 79 (2001) 845. [4] A. Fuchs, M. Bender, U. Plachetka, L. Kock, T. Wahlbrink, H.D.B. Gottlob, J.K. Efavi, M. Moeller, M. Schmidt, T. Mollenhauer, C. Moormann, M.C. Lemme, H. Kurz, J. Vac. Sci. Technol., B. 24 (2006) 2964. [5] N.I. Koo et al., Microelectron. Eng. 84 (2007) 904–907. [6] Namil Koo, Ulrich Plachetka, Martin Otto, Jens Bolten, Jun Ho Jeong, Enung Suk Lee, Heinrich Kurz, Nanotechnology 19 (2008) 225304. [7] P. Mei, W.B. Jackson, C.P. Taussig, A. Jeans, U.S. Patent No. 7056834 B2, June 6, 2006. [8] M.D. Dickey, K.J. Russell, D.J. Lipomi, V. Narayanamurti, G.M. Whitesides, Small 6 (2010) 2050–2057. [9] N. Koo, M. Otto, J.W. Kim, J.H. Jeong, H. Kurz, Microelectron. Eng. 88 (2011) 1033–1036. [10] H.D.B. Gottlob, T. Mollenhauer, T. Wahlbrink, M. Schmidt, T. Echtermeyer, J.K. Efavi, M.C. Lemme, H. Kurz, J. Vax, J. Vac. Sci. Technol., B. 24 (2006) 710.
Contents lists available at SciVerse ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Fabrication of MOSFETs by 3D soft UV-nanoimprint Namil Koo ⇑, Mathias Schmidt, Thomas Mollenhauer, Christian Moormann, Florian Schlachter, Heinrich Kurz Advanced Microelectronic Center Aachen (AMICA), AMO GmbH, Otto-Blumenthal-Str. 25, 52074 Aachen, Germany
a r t i c l e
i n f o
Article history: Available online 31 May 2012 Keywords: Soft UV-NIL MOSFET 3D Imprint Self-alignment Flexible mold
a b s t r a c t So far, metal oxide semiconductor field-effect transistors (MOSFETs) have been fabricated using either optical lithography or imprint lithography with an alignment step between the different layers. Here, we report on the new process for the fabrication of top gate MOSFETs where the number of fabrication steps is reduced significantly. The 3D topography of a top gate MOSFET using as primary master is inversely replicated into a flexible mold that is subsequently transferred to the imprint resist layer. By reactive ion etching, this self aligned 3D pattern is transferred into the underlying semiconductor stack creating functional transistor structures. Preliminary electrical characterizations demonstrate fully operational transistor functions. Ó 2012 Elsevier B.V. All rights reserved.
1. Introduction The metal-oxide-semiconductor field-effect transistor (MOSFET) is the workhorse of the semiconductor industry. It is usually fabricated using one optical lithography step for the MESA layer and subsequent optical lithography step for the gate layer aligned to the MESA layer. The entry points for industrial applications are in all cases low cost and high throughput in fabrication. Therefore, UV-nanoimprint has been proposed as an alternative lithography method for LCD [1], photonics [2], and nano-electronics [3,4]. The fabrication of MOSFETs by imprint lithography has been already shown in Refs. [3,4]. Yet, using this method still requires a cost intensive alignment step between subsequent layers prohibiting the use of soft molds and high throughput for high volume production; thus it would be desirable to eliminate this alignment step. Soft UV-nanoimprint (soft UV-NIL) utilizes a flexible imprint mold for the pattern-replication [5,6]. Soft UV-NIL allows simple generation of a 3D topography into the imprint mold exhibiting all height information required for the replication of different layers. Similar concepts were introduced [7,8]. In this contribution a 3D UV-nanoimprint process using a flexible mold is presented that allows the fabrication of a top gate MOSFET in one lithography step. One imprint step is required for the definition of the MESA and gate layer; subsequently the resist topography is transferred into the substrate with only one reactive ion etching. Mold distortions caused by the imprint pressure [9] for multilevel imprinting are not an issue anymore using this novel 3D
⇑ Corresponding author. E-mail addresses: [email protected] (N. Koo), [email protected] (C. Moormann). 0167-9317/$ - see front matter Ó 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2012.05.015
imprint process. Challenging alignment step for the fabrication of a top gate MOSFET can be avoided by this method. 2. Experiment 2.1. Master fabrication A silicon on insulator (SOI) top gate N-MOSFET device serves as a master for the fabrication of a flexible 3D imprint mold. The master architecture, based on a gate first process device developed by AMO GmbH, that is described in detail in Ref. [10] and illustrated in Fig. 1a. The mesa of the fabricated N-MOSFET has a height of 90 nm. The thickness of the gate oxide and the gate is 10 and 120 nm, respectively (Fig. 1b). A thin anti-adhesion layer was deposited onto the master. The thickness of the layer is about 10 nm. The anti-adhesion layer allows an easy separation of the flexible mold from the surface of the master during the mold fabrication process, preventing damage of the imprint mold. 2.2. Fabrication of flexible molds Polydimethylsiloxane (PDMS, Sylgard 184, Dow Corning) was used for the fabrication of a flexible mold. The base material of PDMS was mixed with its curing agent in a ratio of 10:1. This liquid mixture was poured onto the surface of the master, and then degassed in a vacuum chamber for 60 min. This liquid mixture was thermally cured on a hotplate at 120 °C for 30 min, and finally separated from the master. Now this 3D profile was replicated inversely in a flexible PDMS mold that is illustrated in Fig. 1c. This is a prerequisite for the demonstration of a MOSFET without an alignment step by 3D soft UV-NIL.
86
N. Koo et al. / Microelectronic Engineering 97 (2012) 85–88
Fig. 1. Illustration of the used master and the prepared flexible imprint mold. 3D illustration of the master (a), cross-section view of the master (b), and cross-section view of the flexible imprint mold prepared with the master (c).
2.3. Preparation of a substrate for the fabrication of a top gate MOSFET by 3D soft UV-NIL
2.4. Process flow for the fabrication of a top gate MOSFET by 3D soft UV-NIL
For the direct fabrication of a top gate field-effect transistor by 3D soft UV-NIL, silicon dioxide (t = 10 nm) for the gate oxide was thermally grown on a SOI wafer with 100 nm buried oxide (BOX) and 50 nm top silicon (p-type Bor, NA = 1e16 cm 3) which was reduced to 45 nm during the oxidation process. Afterward, 100 nm polysilicon for the gate was deposited by thermal growth in a LPCVD furnace. The fabricated material stack is illustrated in Fig. 2a.
For the 3D imprint process, a low viscose UV curable imprint resist, AMONIL MMS4 (AMO GmbH, Germany), was used. The low viscosity (50 mPa s at RT) allows fast filling of mold cavities with resist at low imprint pressures. The curing dose of AMONIL is about 2 J/cm2. An optimized EVG 620 imprint tool was used. At first, the imprint resist was spun on the prepared substrate with a thickness of about 200 nm (Fig. 2a). The PDMS mold was pressed into the
Fig. 2. Process flow for the direct fabrication of a top gate field effect transistor by 3D soft UV-NIL. Stack substrate information for the demonstration of a FET (a), resist information for the FET on the stack after imprinting (b), pattern-transfer into the stack after RIE process (c), scattering oxide deposition after removal of the resist layer for the implantation (d), As ion-implantation (e), and removing the scattering oxide layer and rapid thermal annealing (f).
N. Koo et al. / Microelectronic Engineering 97 (2012) 85–88
87
liquid resist layer with an imprint pressure of 200 mbar, filling the 3D cavities of the mold with the liquid resist. After resist curing via UV exposure, the PDMS mold was separated from the cured resist layer. The resist layer on the substrate now exhibited the patterninformation from the primary master (Fig. 2b). Subsequently, this resist pattern was transferred to the material stack using a HBr based RIE process. During this process, the residual layer was removed firstly. Then, the 3D patterns were transferred to the substrate. This HBr based process etches polysilicon as well as silicon dioxide. Once the gate oxide had been completely etched, oxygen gas was added to the gas mixture to attain a high selectivity of the etch rate of silicon (r 160 nm/min) towards the etch rate of silicon dioxide (r 0 nm/min). This process is to finalize the remaining MESA silicon etching and to stop on the box oxide. In this step, the resist was consumed to transfer the complete 3D resist pattern into the underlying material stack of the prepared substrate (Fig. 2c). Resist remaining on the polysilicon gate was removed using acetone and a mixture of sulfuric acid and hydrogen peroxide with a ratio of 1:1. The 30 nm of scattering oxide was deposited on the patterned substrate by thermal evaporation (Fig. 2d) before As-implantation (dose 2e16 cm 2, 45 keV) process (Fig. 2e). Activation was carried out by rapid thermal annealing process at 950 °C for 15 s. Subsequently, the scattering oxide was removed using 5% diluted hydrofluoric acid (HF). Fig. 2f shows the fabricated top gate MOSFET. 3. Results and discussion A comparison of the process steps for the fabrication of a top gate MOSFET by conventional optical lithography and 3D soft UV-NIL is shown in Fig. 3. Conventional optical lithography requires 15 process steps while self-aligned 3D soft UV-NIL reduces the number of process steps to nine. The functionality of top gate MOSFETs fabricated by 3D soft UVNIL has been tested in preliminary experiments. The SEM image of the fabricated MOSFET is depicted in Fig. 4a. The output characteristic shown in Fig. 4b exhibits the well known transistor regimes; both linear- and saturation region are successfully developed even in this very preliminary state. Since the gate oxide might be damaged
Fig. 4. SEM micrograph of a fabricated top gate transistor (a), output characteristic of the fabricated MOSFET (b) and (c).
during HF process, the gate leakage current is too high (Fig. 4c). Therefore no perfect saturation region was displayed in Fig. 4b. By using a RIE for the removal of scattering oxide instead of HF process, the electrical performance of the devices could be improved. 4. Conclusion
Fig. 3. Comparison of process flow for the fabrication of a top gate MOSFET by conventional optical lithography and 3D soft UV-NIL.
Fully functional top gate MOSFETs were fabricated using 3D UVNIL where all the necessary architecture of 3D transistor is replicated with only one lithographic step. This 3D UV-NIL approach reduces the process steps required for the fabrication of a MOSFET from 15 to 9. The 3D lithography concept presented here in the case of MOSFETS exploits specific strengths of soft UV-NIL. By integrating the alignment into the imprint mold a 3D transistor
88
N. Koo et al. / Microelectronic Engineering 97 (2012) 85–88
geometry was created in a single lithography step, replacing complicated alignment technology by self-alignment. Thus, this approach bears a high potential for low cost fabrication of 3D electronic components in displays and organic electronics where more than one layer has to be structured. Acknowledgement This work was funded as part of the FP7 IP Project ‘‘NapaNIL’’ Grant Agreement No. 214249. References [1] J.H. Jeong, K.D. Kim, D.G. Choi, J.H. Choi, E.S. Lee, Proc. SPIE 6517 (2007) 651716. [2] U. Plachetka, N. Koo, T. Wahlbrink, J. Bolten, M. Waldow, T. Plötzing, M. Först, H. Kurz, IEEE Photonics Technol. Lett. 20 (2006) 490.
[3] W. Zhang, S.Y. Chou, Appl. Phys. Lett. 79 (2001) 845. [4] A. Fuchs, M. Bender, U. Plachetka, L. Kock, T. Wahlbrink, H.D.B. Gottlob, J.K. Efavi, M. Moeller, M. Schmidt, T. Mollenhauer, C. Moormann, M.C. Lemme, H. Kurz, J. Vac. Sci. Technol., B. 24 (2006) 2964. [5] N.I. Koo et al., Microelectron. Eng. 84 (2007) 904–907. [6] Namil Koo, Ulrich Plachetka, Martin Otto, Jens Bolten, Jun Ho Jeong, Enung Suk Lee, Heinrich Kurz, Nanotechnology 19 (2008) 225304. [7] P. Mei, W.B. Jackson, C.P. Taussig, A. Jeans, U.S. Patent No. 7056834 B2, June 6, 2006. [8] M.D. Dickey, K.J. Russell, D.J. Lipomi, V. Narayanamurti, G.M. Whitesides, Small 6 (2010) 2050–2057. [9] N. Koo, M. Otto, J.W. Kim, J.H. Jeong, H. Kurz, Microelectron. Eng. 88 (2011) 1033–1036. [10] H.D.B. Gottlob, T. Mollenhauer, T. Wahlbrink, M. Schmidt, T. Echtermeyer, J.K. Efavi, M.C. Lemme, H. Kurz, J. Vax, J. Vac. Sci. Technol., B. 24 (2006) 710.