First Vertical Hall Device in standard 0.35 μm CMOS technology

Sensors and Actuators A 147 (2008) 41–46

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Sensors and Actuators A: Physical journal homepage: www.elsevier.com/locate/sna

First Vertical Hall Device in standard 0.35 ␮m CMOS technology ´ Joris Pascal ∗ , Luc Hebrard, Jean-Baptiste Kammerer, Vincent Frick, Jean-Philippe Blonde´ ´ lectronique du Solide et des Syst`emes (InESS), ULP Strasbourg, CNRS-UMR7163, BP20, 23 rue du Loess, 67037 Strasbourg Cedex, France Institut d’E

a r t i c l e

i n f o

Article history: Received 23 October 2007 Received in revised form 9 January 2008 Accepted 3 March 2008 Available online 18 March 2008 Keywords: Hall effect Vertical Hall Device (VHD) Standard CMOS technology

a b s t r a c t In order to lower the short-circuit effect due to the measurement contacts, Vertical Hall Devices (VHDs) are generally designed either in bulky N-type silicon or in the deep N-well of high-voltage CMOS technologies. In this last case, VHD can benefit from on chip circuitry for offset and 1/f noise reduction, but HVCMOS remains a costly technology. Using spinning-current, HVCMOS compatible VHDs with a resolution of 76 ␮T rms over a 1.6-kHz bandwidth have been demonstrated. The VHD presented here is designed in the shallow N-well of a low-cost 0.35 ␮m standard CMOS technology. Unlike conventional VHD, its measurement contacts are located outside the sensor active area. FEM simulations and experimental results show that the new geometry suppresses the short-circuit effect and strongly reduces the intrinsic offset and noise. Thus, without any noise and offset reduction method, this new small VHD (63 ␮m2 ) reaches a resolution of 79 ␮T rms over a (5 Hz–1.6 kHz) bandwidth, and opens the way to the integration of 3D Hall sensors in low-cost standard CMOS technologies. © 2008 Elsevier B.V. All rights reserved.

1. Introduction The Vertical Hall Device (VHD), which is sensitive to a magnetic field in the plane of the chip, was devised more than 20 years ago [1,2]. Such a device is also named parallel-field Hall microsensor [3–5]. Until now, it has been manufactured as a discrete component [6] because its biasing current has to flow in the depth of the device, preventing its integration since no current can be injected in the substrate of a CMOS circuit. Recently, a VHD designed with the deep N-well (dw = 7 ␮m) of a high-voltage CMOS technology has been successfully demonstrated [7]. It has the advantage to be co-integratable with electronics to use spinning-current for offset, 1/f noise [8] as well as planar Hall effect [9] reduction. Combined with a conventional Horizontal Hall Device, it is at the origin of the first monolithic 3D Hall probe [10], which is now commercially available [11]. Nevertheless, such a VHD cannot be integrated in the thin Nwell (depth dw = 2 ␮m) of a standard CMOS technology because in that case a part of the biasing current flows through the sensing contacts instead of flowing through the low-doped N-well area beneath these contacts. The new vertical Hall effect sensor proposed in this paper addresses this issue. It is based on a structure similar to the one presented in [12,13], where the measuring contacts are located outside the sensor active area. Nevertheless, unlike

∗ Corresponding author. Tel.: +33 3 88 10 62 05. E-mail addresses: [email protected], [email protected] (J. Pascal). 0924-4247/$ – see front matter © 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.sna.2008.03.011

the device presented in [12] which is realized as a discrete component, our sensor is integrated in a low-cost 0.35 ␮m CMOS process. Section 2 describes the working principle of our VHD and studies through F.E.M. simulations the limits in terms of sensitivity of Vertical Hall devices integrated in CMOS technologies. The advantage of using Hall contacts outside the sensor active area for device integration is also discussed. Section 3 compares the experimental results obtained with the conventional 5-contact VHD structure and with the new one proposed here. Finally, Section 4 concludes on this work and exposes the perspectives associated with these new results. 2. New vertical Hall effect device 2.1. The Hall effect The working principle of a Hall effect device is depicted in Fig. 1. When a magnetic field Bx is applied orthogonally to a semiconducting plate biased with a current Ip , a Hall voltage settles between the two lateral sides of the plate (Fig. 1) [6]. This voltage stems from the Hall electric field, which is given by: −rH   E H = ·j×B q·n Such a plate is called a Horizontal Hall Device, since it is sensitive to the magnetic field Bx orthogonally oriented to the plane of the chip. rH is the electron scattering factor (in silicon rH ≈ 1.15), − → q the elemental electric charge, n the doping level of the plate, j − → the current density, and B the magnetic field. By integrating the previous equation, the sensitivity of the Horizontal Hall Device is

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Fig. 1. Horizontal Hall plate.

obtained as [6] S=

VH G · rH = · IP = SI · IP B n·q·t

where t is the plate thickness and Ip the biasing current. G is the geometrical factor (G < 1) which models the reduction of VH due to the part of the current which flows through the sensing contacts TA and TC as well as the short-circuit effect induced by the biasing contacts T0 and T1 . SI is the current-related sensitivity. We define SImax = SI when G = 1: SImax =

rH n·q·t

SImax only depends on the plate doping level n and on the thickness t. Thus, whatever the plate geometry is, the theoretical maximum sensitivity remains the same as long as G = 1. In particular, this is the case if biasing and sensing contacts are point like [6]. 2.2. Conformal mapping and VHD structures In the previous section, we mentioned that a horizontal Hall effect device is sensitive to the magnetic field orthogonally oriented to the plane of the chip. In addition, the current lines and the electric field lines form a constant angle  H = n B, where n is the carrier mobility and B the magnetic field component orthogonal to the current lines. Therefore, when performing a conformal

mapping, which is a geometrical transformation that preserves the angles, we obtain an equivalent plate with a different geometry. Fig. 2 illustrates the bilinear transformation which transforms the unit circle in the complex t plane into the upper half plane in the complex z plane. As stated in the previous section, with point-like contacts, the unit circle is equivalent to a traditional Hall plate with a geometrical factor G = 1. Assume now that such a circle is placed vertically in the wafer. This structure is not practically feasible in a planar technology since contact T1 would be then located in the depth of the substrate. On the contrary, the equivalent structure in the upper half plane of the complex z plane can be carried out in a CMOS planar process since all the contacts are located on the same side that is the top side of the wafer. Practically, the Vertical Hall Device is implemented in the N-well of the CMOS technology and exhibits finite dimensions. In particular, the VHD depth is limited to roughly 2 ␮m in a low-cost standard 0.35 ␮m CMOS process. As a matter of fact, each structure is sensitive to the magnetic field orthogonally oriented to the current lines. Current lines flow from T0 to T1 in the t plane and from Z0 to Z1,1 in the z plane. Note that after transformation, Z1 and Z1 become infinitely long. In the t plane, the Hall voltage is measured between TA and TC , VH = VTA −TB + VTB −TC where TB is the center of the circle (Fig. 2). Due to the central symmetry, the VTB potential does not change whatever the value of the magnetic field applied to the circular device is. On the contrary, for its counterpart in the non-infinitely deep z plane, this is not the case (see Section 2.3), and to measure the same sum of voltages in the z plane, we need an access to the rear side of the N-well, that means to points ZB and ZB (which are not located at the infinite in the N-well deepness as they should be theoretically). In that configuration, we could have the same Hall voltage as in the t plane VH = VZA −ZB + VZB −ZC = VTA −TC . Of course, that is not possible in planar technology since we have no access to ZB and ZB . Hence, measuring the Hall voltage in the z plane does not permit to obtain 100% of the theoretical sensitivity SImax . It is important to note that even if the VHD is deep enough for the Hall voltage to vanish at the rear side, a Hall voltage will then settle at the lateral sides, whatever the distance between these lateral sides is. In other words, using planar technologies with all the contacts on the same side, the sensitivity measured between two sensing contacts of any VHD will be only a fraction of SImax , whatever the relative location of the sensing and biasing contacts is, these contacts being point-like or not.

Fig. 2. Bilinear transformation. The top side of the wafer corresponds to the bottom side of the figure.

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Fig. 3. The bilinear transformation applied to the new sensor.

The conventional VHD is similar to the one in the z plane of Fig. 2, with sensing contacts ZA and ZC located between the biasing contacts Z1 /Z0 and Z0 /Z1 , respectively [14,15]. Nevertheless, such a VHD suffers from short-circuit effect due to the sensing contacts (see Section 2.3). That is one of the reason why it has been fabricated as a discrete component or integrated recently in the deep N-well of a high-voltage CMOS technology [7]. In addition, it exhibits a high offset and 1/f noise, and requires spinning-current to become efficient [8]. Short-circuit effect due to a contact is especially marked if a high current density has to flow in the vicinity of this contact. This is the case for the sensing contacts in the conventional VHD. In bulky silicon, 1/f noise can be attributed to mobility fluctuation [16]. Its effect is thus proportional to the current density, as for the offset (see Section 2.4). As a consequence, offset and 1/f noise are very marked in a conventional VHD since a high current flows between the biasing contacts Z1 /Z0 and Z0 /Z1 , i.e. in the area where are located the sensing contacts. This reasoning lead us to shift the sensing contacts outside the “active area” of the VHD which is define as the zone between the external biasing contacts Z1 and Z1 . To design our new structure, we modified the original structure in the t plane by duplicating one of the two biasing contacts. This contact is divided into two new contacts: T1 and T1 (Fig. 3) as in the split-current resistor [17]. Since these contacts are symmetrically located in the structure, they make it possible to measure a Hall voltage with no systematic offset. After conformal mapping, all the contacts located on the unit circle in the t plane are located on the real axis in the z plane. By this mean we obtain a Vertical Hall Device with measurement contacts ZD and ZE located outside the sensor active area. A similar 5-contact VHD has been recently proposed as a discrete component [10,11] as well as a simplified 3-contact version [18]. Nevertheless, the authors do not point out clearly all the advantages of such a structure, especially for its integration in the shallow N-well of a low-cost CMOS technology.

Fig. 4. Structure of the Vertical Hall Device used for FEM simulation.

its length is named lw . Its doping level was set to 6.2 × 1016 cm−3 . All these dimensions, except lw which will be varied for simulations purposes, correspond to minimal sizes of a typical 0.35 ␮m CMOS technology. Fig. 5 shows the static voltage along the top side and the rear side of the VHD. Contact Z0 is biased with 2.5 V and contact Z1 and Z1 are biased with −2.5 V. Note that at the extremities of the sensor (points ZD and ZE ), the potential is the same on top and rear sides. This potential is not equal to −2.5 V because a small amount of current flows close to Z1 , between ZD and Z1 , as well as close to Z1 between Z1 and ZE (see Fig. 4). The rear and lateral sides are in a high impedance state, allowing the Hall voltage to settle also on these sides. In order to compare the sensitivities of the two VHD

2.3. Sensitivity limits of VHDs We used an in house 2D FEM galvanomagnetic simulator to calculate the distribution of the magnetic field induced potential variation along the top side of the VHD depicted in Fig. 4. For the first set of simulations, the sensing contacts ZA and ZC (conventional VHD) as well as ZD and ZE (new VHD) are point-like and do not contribute to any short-circuit effect. The biasing contacts Z0 , Z1 and Z1 are identical with dimensions tc = tw = 3 ␮m, lc = 700 nm, and dc = 150 nm (see Fig. 4). The doping level was set to 1018 cm−3 . The thickness of the vertical Hall plate is tw = 3 ␮m, its depth 2 ␮m, and

Fig. 5. The potential distribution at the top side and at the rear side of the VHD. Z points located on the top side are displayed.

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Fig. 6. (a) FEM simulation of SI normalized to SImax along the top side of the VHD, lw = 85 ␮m. Contacts size: tc = 3 ␮m, lc = 700 nm, dc = 150 nm. (b) FEM simulation of SI normalized to SImax along both top side and rear side of the VHD, lw = 85 ␮m. Contacts size: tc = 3 ␮M, lc = 700 nm, dc = 150 nm. (c) FEM simulation of SI normalized to SImax along the top side of the smallest VHD (lw = 21 ␮m) which exhibits maximum sensitivity at points ZA and ZC . (d) FEM simulation of SI normalized to SImax along the top side of the smallest VHD (lw = 21 ␮m) with finite size measurement contacts at points ZD , ZA , ZC and ZE .

types, the conventional and the new one, all the simulated currentrelated sensitivities have been plotted normalized to SImax . Fig. 6a, which represents the sensitivity along the top side of the VHD with lw = 85 ␮m, shows that 0.70·SImax is the maximum sensitivity we can reach with such a vertical plate when points of measurements are on the top side of the device. When measuring VH between ZD and ZE , we only reach 0.30·SImax . Note that if the VHD is deeper, it also exhibit the same maximum current-related sensitivities, that is 70% of SImax for contacts ZA and ZC , and 30% of SImax for contacts ZD and ZE . In Fig. 6b, we plotted simulation results obtained both for top and rear side of the VHD. We notice that the two plots are equal at the extremities (points ZD and ZE ) since the top side is electrically connected to the rear side through the lateral sides. Exactly as the static voltage, the Hall voltage is continuous along all the sides of the structure. As explained in Section 2.2, the maximum sensitivity remains the same whatever the plate geometry is, as long as the geometrical factor G = 1. Indeed, top side can provide 0.70·SImax , between ZA and ZC and 0.30·SImax between ZD and ZE . Summing both sensitivities allows obtaining 100% of SImax . In Fig. 6a and b, the size of the biasing contacts is small enough compared to the device length lw = 85 ␮m so that the theoretical sensitivity of 0.70·SImax is almost obtained at points ZA and ZC . Thus, we carried out simulations to determine the smallest lw which corresponds to G = 1 and SI = 0.70·SImax , keeping lc = 700 nm which is the minimum size allowed by the technology. We obtained lw = 21 ␮m. For lw < 21 ␮m,

the distance between biasing contacts Z1 , Z0 , and Z1 becomes too small and a short-circuit effect occurs. Then measuring VH = VZAZC in such a configuration provides SI < 0.70·SImax corresponding to G < 1. Fig. 6c shows the simulation results for the smallest device (lw = 21 ␮m) with non-reduced sensitivity at points ZA and ZC . Until now, we only took into account the influence of the biasing contacts placed at Z0 , Z1 and Z1 . However, to design a sensor, we must add finite size sensing contacts to sense the Hall voltage. So, we simulated the influence of these sensing contacts placed at the points ZD , ZA , ZC and ZE (Fig. 6d). These contacts are of the same dimensions as the biasing contacts, that is the minimal size allowed by the technology. We clearly notice that the sensing contacts short circuit the Hall voltage VH when measuring VH = VZA −ZC , reducing SI from 70 to 50% of SImax . On the contrary, SI remains the same between ZD and ZE , equal to 30% of SImax , since almost no current flows in the region beneath these contacts. 2.4. Conventional versus new VHD structures Offset is mainly induced by piezoresistive effects or masks misalignment. Piezoresistive effects induce a variation of silicon resistivity. The distance between contacts ZD and Z1 is equal to the distance between ZA and Z1 . But the current that flows between contacts ZD and Z1 is smaller than the one that flows between ZA and Z1 (Fig. 5). Therefore, the piezoresistive effect induces a higher

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Fig. 7. (a) Measured sensitivity between ZA and ZC (conventional VHD) or between ZD and ZE (new VHD). (b) Output noise between ZA and ZC (conventional VHD) and between ZD and ZE (new VHD). Table 1 Comparison of the main performances of the conventional VHD and the new VHD proposed in this paper

Conventional VHD New VHD

SImes (V/A T)

Ip (mA)

Resolution (␮T)

SImax = rH /(n·q·t) (V/A T)

SIFEM /SImax

SImes /SIFEM

Measured offset (mT)

8.75 6.40

1.12 1.12

716 79

21.33 21.33

0.70 0.30

0.59 1

197 40

voltage variation at point ZA than at point ZD . Masks misalignment shifts the contacts away from their ideal location. Fig. 5 shows that a slight shift of point ZC will induce a higher voltage variation at this point, than if the same shift is applied to point ZE . The two phenomenon’s listed above: piezoresistivity and mask misalignment explain why the offset is smaller for the new VHD than for the conventional one. The conventional VHD has a better theoretical current-related sensitivity than the new one, i.e. 50% versus 30% of SImax . Nevertheless, it is well known to exhibit a high 1/f noise. On the contrary, since almost no current flows under the sensing contacts ZD and ZE , we can expect a low 1/f noise at the output of the new structure, leading to a good resolution in spite of the low value of 30% of SImax for the sensitivity. This is actually verified by the experiments. 3. Experimental results The seven contacts VHD given in Fig. 4 with lw = 21 ␮m has been fabricated in a 0.35 ␮m standard CMOS technology. It has been biased with 2.7 V between Z0 /Z1 ,Z1 , leading to a biasing current of 1.12 mA. Fig. 7a shows that measuring VH between ZA and ZC or between ZD and ZE leads roughly to the same current-related sensitivity SI . When measuring between ZD and ZE , we can assume that there is no short-circuit effect. As a consequence, the measured current-related sensitivity corresponds to 0.30·SImax . We can thus deduce SImax = 21.33 V/A T. Simulation of the current-related sensitivities for both new and conventional structures shows a sensitivity for the new VHD which is 0.6 times smaller than for the conventional VHD. Measurements results give a better ratio of 0.73. It comes most probably from the N-well Gaussian doping profile. This kind of profile concentrates the current lines in the shallowness of the Hall plate increasing the short-circuit effect in the conventional VHD. For the simulation we considered the doping level constant. In this way, the short-circuit effect is underestimated. Fig. 7b shows, as expected, that the 1/f noise is drastically

reduced when measuring between ZD and ZE . As a consequence, our new VHD exhibits a 79 ␮T resolution, while the conventional VHD exhibits a resolution of only 710 ␮T over a (5 Hz, 1.6 kHz) bandwidth. Table 1 gathers the main performances for both structures. Note that the resolution of 79 ␮T is comparable to the one exhibited by the VHD presented in [8] over a 1.6 kHz bandwidth. 4. Conclusion This paper has shown that the current-related sensitivity SI of a VHD, whatever the position of its sensing and biasing contacts is, cannot reach the maximal current-related sensitivity SImax of the well known Horizontal Hall Device. In practice, using the shallow N-well of standard CMOS technologies to implement a VHD limits its SI to 30% or 40% of SImax , depending on the location of the sensing contacts, outside or inside the sensor active area. However, when the sensing contacts are located outside the active area, the short-circuit effect is suppressed, and the offset and 1/f noise are drastically reduced. This is in contrast to what happens with the conventional VHD where sensing contacts are inside the active area. Therefore, despite its low intrinsic sensitivity, the new VHD proposed here exhibits a good resolution and opens the way to the integration of a 3D magnetic microsensor in low-cost standard CMOS technologies. References [1] Ch. Roumenin, P. Kostov, Planar Hall-effect device, Bulgarian Patent No. 37,208 (December 26, 1983). [2] R.S. Popovic, The vertical Hall-effect device, IEEE Electron Device Lett. 5 (September) (1984) 357–358. [3] Ch. Roumenin, Parallel-field Hall microsensors: an overview, Sens. Actuators A A30 (1992) 77–87. [4] Ch. Roumenin, Magnetic sensors continue to advance towards perfection, Sens. Actuators A 46/47 (1995) 273–279. [5] Ch. Roumenin, Microsensors for magnetic fields, MEMS: A Practical Guide to Design, Analysis, and Applications, in: J.G. Korvin, O. Paul (Eds.), William Andrew Publisher & Springer, 2006, pp. 453–531 (Chapter 9).

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[6] R.S. Popovic, Hall Effect Devices, Second ed., Institute of Physics Publishing, 2004. [7] E. Schurig, Demierre F., C. Schott, R.S. Popovic, A Vertical Hall Device in CMOS high-voltage technology, Sens. Actuators A 97/98 (2002) 47–53. [8] E. Schurig, C. Schott, P.-A. Besse, M. Demierre, R.S. Popovic, 0.2 mT residual offset of CMOS integrated vertical Hall sensors, Sens. Actuators A 110 (2004) 98–104. [9] D.R. Popovic, S. Dimitrijevic, M. Blagojevic, P. Kejik, E. Schurig, R.S. Popovic, Three-axis teslameter with integrated hall probe free from the planar hall effect, in: Proceedings of the IMTC 2006, April 24–27, Sorrento, Italy, 2006, pp. 1812–1815. [10] P. Kejik, E. Schurig, F. Bergsma, R.S. Popovic, First fully CMOS-integrated 3D Hall probe, in: Transducers’05, June 5–9, 2005, pp. 317–320. [11] D.R. Popovic, S. Dimitrijevic, M. Blagojevic, P. Kejik, E. Schurig, R.S. Popovic, Three-axis teslameter with integrated hall probe, IEEE Trans. Instrum. Meas. 56 (August (4)) (2007) 1396–1402. [12] Ch. Roumenin, D. Nikolov, A. Ivanov, A novel parallel-field Hall microsensor, Digest of Technical Papers of Eurosensors XVI, September 15–18, Prague, Czech Republic, 2002, pp. 545–548. [13] Ch. Roumenin, D. Nikolov, A. Ivanov, 3-D silicon vector sensor based on a novel parallel-field Hall microdevice, Sens. Actuators A 10 (2004) 219–227. [14] A.M.J. Huiser, H.P. Baltes, Numerical modelling of vertical Hall-effect devices, IEEE Electron Device Lett. EDL-5 (November (11)) (1984) 482–484. [15] G.-M. Sung, Interaction between magnetoresistor and magnetotransistor in the longitudinal and folded Vertical Hall Devices, IEEE Sens. J. 4 (December (6)) (2004) 749–758. [16] F. Hooge, 1/f noise sources, IEEE Trans. Electron Devices 41 (November) (1994) 1926–1935. [17] J.W.A. von Kluge, Analysis of split-current magnetic field sensitive resistors, Sens. Actuators A 93 (2001) 103–108. [18] Ch.S. Roumenin, S.V. Lozanova, Three-contacts parallel-field hall device—the sensors with minimal design complexity, in: Proceedings of the 20th Eurosen¨ sors Conference, September 17–20, Goteborg, Sweden, 2006, pp. 212–213.

respectively, and the “Habilitation à Diriger des Recherches” degree from the University Louis Pasteur (ULP), Strasbourg, France, in 2005. From 1994 to 1995, he was a Researcher with the Centro Nacional de Microelectrónica, Barcelona, Spain, working on the design and compact modelling of MEMS. In 1995, he was appointed Associate Professor with ULP. Since 2006, he has been Professor with the same University. From 1994 to 2004, he was with the Laboratoire d’Electronique et de Physique des Systèmes Instrumentaux (LEPSI), ULP, and now he is with the Institut d’Electronique du Solide et des Systèmes (InESS), ULP-CNRS, working in the field of integrated instrumentation. During 2004–2005, he was a Visiting Researcher with the Electronic Instrumentation Laboratory, Technical University of Delft, Delft, The Netherlands. His main research interests include the design of low-power, low-noise analog and mixed-signal ICs, and the design and compact modelling of integrated sensors.

Biographies

Jean-Philippe Blondé received the Ph.D. degree from the Institut National Polytechnique de Lorraine in 1988. He joined the University Louis Pasteur of Strasbourg in 1989 as an associate Professor. From 1989 to 1997 his research interests deal with mixed signal integrated systems for high energy physics experiments at CERN. Since 1997, his research focuses on CMOS digital architecture, VLSI analog and digital signal processing for instrumentation and biomedical engineering. Currently he leads the ECG project for the InESS laboratory (Institut d’Electronique des Solides et des Systèmes Strasbourg, France).

Joris Pascal received his Engineer and M.S. degrees from the École Supérieure d’Électricité (Supélec), France, in 2005. Currently, he is a Ph.D. student at the University Louis Pasteur of Strasbourg doing his research at the InESS (Institut d’Électronique du Solide et des Systèmes, Strasbourg, France) on integrated instrumental chains featuring silicon magnetic sensors for biomedical applications. Luc Hébrard was born in 1967. He received the Engineer degree and the Ph.D. degree in microelectronics from Ecole Centrale de Lyon, Lyon, France, in 1990 and 1993,

Jean-Baptiste Kammerer was born in 1977. He received the M.S. and Ph.D. degrees in Microelectronics from the University Louis Pasteur (ULP), Strasbourg, France, in 2001 and 2004, respectively. From 2001 to 2004, he was with the Laboratoire d’Electronique et de Physique des Systèmes Instrumentaux (LEPSI), ULP, where he prepared a Ph.D. Thesis. He is currently with the Institut d’Electronique du Solide et des Systèmes (InESS), ULP, as a professor associate. His research interests include integrated sensors, devices modeling and low-noise analog and mixed-signal circuit design. Vincent Frick was born in 1969. He received the Ph.D. degree in Microelectronics and Instrumentation from the University Louis Pasteur of Strasbourg, France, in 2002. Until July 2003, he was with SOCOMEC SA, Benfeld, France, working as a Research Engineer on energy metering dedicated systems-on-chip. He currently works as an Associate Professor at the University Louis Pasteur of Strasbourg, France. His research topics at InESS (Institut d’Electronique du Solide et des Systèmes, Strasbourg, France) include the design of integrated sensors, smart-power, low-noise analog and mixedsignal systems on chip for industrial and biomedical applications.