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Silicon photomultiplier detector with multipurpose in-pixel electronics in standard CMOS technology
Nuclear Inst. and Methods in Physics Research, A (
)
–
Contents lists available at ScienceDirect
Nuclear Inst. and Methods in Physics Research, A journal homepage: www.elsevier.com/locate/nima
Silicon photomultiplier detector with multipurpose in-pixel electronics in standard CMOS technology R. Blanco ∗, C. Kraemer, I. Perić Institute for Data Processing and Electronics (IPE), KIT-ADL (ASIC and Detector Laboratory), Karlsruhe, Germany
ARTICLE Keywords: Solid state detectors Photo detectors SPAD SiPM
INFO
ABSTRACT This paper presents a monolithic avalanche diode array designed in a commercial AMS 350 nm high-voltage CMOS (HV-CMOS) process. This monolithic detector comprises a single photon avalanche diode (SPAD), active quenching circuit and readout electronics. The SPAD consists of a p+ diffusion/n-well junction surrounded by a shallow p-well acting as a guard ring to prevent edge breakdown. The monolithic detector has a matrix of 20 × 15 pixels. The size of one SPAD pixel is 38 × 92 μm2 . One pixel defined as SPAD and readout electronics has a total size of 115 × 111 μm2 with a fill factor = 24.3% and a chip size of about 2.8 × 2.6 mm2 .
Contents 1. 2. 3. 4. 5.
Introduction ....................................................................................................................................................................................................... Sensor architecture.............................................................................................................................................................................................. Front-end electronics ........................................................................................................................................................................................... Measurement results............................................................................................................................................................................................ Conclusion ......................................................................................................................................................................................................... Acknowledgments ............................................................................................................................................................................................... References..........................................................................................................................................................................................................
1. Introduction A growing interest in single photon detection and imaging can be observed in various scientific and industrial applications such as astroparticle physics (e.g. Cherenkov light detection), meteorology, medicine (e.g. positron emissions tomography), biology (e.g. bioluminescence). Light detection at the single-photon level was invented more than 80 years ago. The photo-multiplier tube (PMT) was the first device used for single-photon detection. PMTs have several disadvantages such as limited detection efficiency, especially for longer wavelengths and are unsuitable for compact design of integrated systems. Semiconductor detectors are a valuable alternative to PMTs due to the well-known advantages of solid state detectors such as small size, low power dissipation, low supply voltage, low cost. A Single-Photon Avalanche Diode (SPAD) is a semiconductor photon sensor operated in the so-called Geiger-mode. When a photon hits an SPAD, the generated charge carriers trigger an avalanche multiplication. The avalanche can produce 105 –106 carriers. The SPAD is sufficiently biased above the diode breakdown voltage. Since the avalanche in Geigermode is self sustained, a quenching circuit [1] must be used to prevent
1 1 2 2 2 2 2
overheating and the destruction of the diode. The purpose of the quenching circuit is to stop the avalanche current by lowering the bias voltage. There are three conditions in which the SPAD operates: reset (where the diode is ‘‘armed’’ with a bias voltage higher than breakdown), avalanche and quenching. A silicon photomultiplier (SiPM) in its simplest form consists of SPADs defining a microcell. In other words, the SiPM is equivalent to an array of SPAD microcells with a quenching circuit. 2. Sensor architecture The HV-CMOS SPAD structure implemented in a deep n-well (DN) forms the cathode and insulates the photosensitive area of the SPAD. The deep n-well is biased at positive 𝑉𝐻𝑉 = 𝑉𝐵𝐷 + 𝑉𝑂𝑉 , 𝑉𝐵𝐷 being the breakdown voltage and 𝑉𝑂𝑉 the overvoltage to operate in Geiger-mode. A p+ implant, acting as the anode, and a shallow n-well (SN) define the high-field region in the active area. The junction is surrounded by a shallow p-well (SP) implantation acting as a guard ring to prevent edge breakdown of the sensor (Fig. 1). The p-substrate is shared with readout electronics. The SPAD signal is DC coupled to the front-end. Since the
∗ Corresponding author. E-mail address: [email protected] (R. Blanco).
https://doi.org/10.1016/j.nima.2018.09.107 Received 29 June 2018; Received in revised form 5 September 2018; Accepted 24 September 2018 Available online xxxx 0168-9002/© 2018 Elsevier B.V. All rights reserved.
Please cite this article in press as: R. Blanco, et al., Silicon photomultiplier detector with multipurpose in-pixel electronics in standard CMOS technology, Nuclear Inst. and Methods in Physics Research, A (2018), https://doi.org/10.1016/j.nima.2018.09.107.
R. Blanco et al.
Nuclear Inst. and Methods in Physics Research, A (
)
–
The external electronics consist of active inhibition and reset switches, fast comparator, edge detection, monostable circuit, 1-bit hit flag, analog time stamp memory, hit-OR bus and data output. If a photon hits the SPAD (set in Geiger-mode) the SPAD signal will rise above the threshold (𝑉𝑡ℎ𝑟 ). The threshold is generated in a bias DAC block implemented on the periphery of the ASIC. This threshold is also used to suppress the dark counts during photon signal generation. As soon as the signal exceeds the threshold, the signal is pulled to 3.3 V level (inhibition switch). At this point the hold time starts. The hold time (delLoHold) can be adjusted with a delay circuit that is connected to the reset input of the RS-flipflop. The output (q signal) of the RS-flipflop controls the inhibition switch and the input of the edge detector. This edge detector triggers the reset switch with a defined edge time (delHiEdge, delLoEdge). The edge time is also applied to the edge detector after the comparator circuit. The relaxation speed (return to base line speed) is dependent on the edge time setting and the VNBias can be stored. Short relaxation time means low VNbias and low edge time setting. When a photon signal (hit signal) is detected, the hit flag stores analog time stamp (ramp signal) and the hit is stored in the 1-bit hit flag, ready for read out. A row can be selected and read out by the data bus. The hit-OR is connected to the monoflop output. Upon receiving monoflop out, the external circuit can generate a store signal that puts the hit latch into store mode. A hit-OR is provided for self-trigger mode. Single pixel, full matrix and self triggered readout is possible.
Fig. 1. Sensor design, full ASIC and pixel layout.
Fig. 2. Simplified schematic diagram of the monolithic detector.
4. Measurement results We present the initial experimental result for the breakdown voltage and the dark count rate (DCR). The breakdown voltage values have been determined from the current–voltage (I–V) characteristics, using a precision source measure unit (Keysight B2901A). A breakdown voltage of 11.7 V was measured at 24.0 ◦ C for an SPAD pixel size of 3496 μm2 . The DCR of one pixel was measured in darkness. At 12.0 V (𝑉𝑂𝑉 ≈ 300 mV) a dark count rate of 610 kHz corresponding to 174 Hz∕μm2 was measured. This DCR is acceptable [2]. Improvements are possible when a lower doped junction is chosen. Furthermore, it was also observed that the DCR is weakly dependent on temperature (Fig. 3). The trap-assisted band-to-band tunneling is responsible for the generation of free charge carriers. We measured a temperature sensitivity for breakdown voltage of ≈ 9 mV ◦ C−1 . 5. Conclusion
Fig. 3. Dark count rate versus temperature.
We presented a monolithic detector including active quenching and readout electronics. This monolithic detector was designed in a commercial 350 nm HV-CMOS process. The measurement results show an acceptable breakdown voltage and DCR. The DCR is weakly dependent on temperature due to trap-assisted band-to-band tunneling.
SPAD n-well is at high-voltage and the n-well for the readout electronics at 3.3 V, a minimum spacing of 15 μm must be allowed between these wells. The corners of the SPAD are round to avoid high electric field peaks. We designed a large SPAD with an active area of 38 × 92 μm2 to increase the fill factor. A fill factor of 24.3% was achieved. The layout design of an SPAD pixel, front-end electronics and the ASIC is shown in Fig. 1.
Acknowledgments This work was supported by the KIT Karlsruhe School of Elementary Particle and Astroparticle Physics (KSETA), Germany.
3. Front-end electronics References Our design is presented in an active quenching circuitry. A simplified schematic diagram of the electronics is shown in Fig. 2. We chose an active quenching circuit in order to achieve a better pixel integration and adjustable quench timing and to avoid a fixed quench timing by an internal RC circuitry (passive quenching).
[1] S. Cova, M. Ghioni, A. Lacaita, C. Samori, F. Zappa, Avalanche photodiodes and quenching circuits for single-photon detection, OSA A386 (1996) 1956–1976. [2] N. D’Ascenzo, X. Zhang, Q. Xie, Application of CMOS technology to silicon photomultiplier sensors, PMC Web (2017) 2204.
2 Please cite this article in press as: R. Blanco, et al., Silicon photomultiplier detector with multipurpose in-pixel electronics in standard CMOS technology, Nuclear Inst. and Methods in Physics Research, A (2018), https://doi.org/10.1016/j.nima.2018.09.107.
)
–
Contents lists available at ScienceDirect
Nuclear Inst. and Methods in Physics Research, A journal homepage: www.elsevier.com/locate/nima
Silicon photomultiplier detector with multipurpose in-pixel electronics in standard CMOS technology R. Blanco ∗, C. Kraemer, I. Perić Institute for Data Processing and Electronics (IPE), KIT-ADL (ASIC and Detector Laboratory), Karlsruhe, Germany
ARTICLE Keywords: Solid state detectors Photo detectors SPAD SiPM
INFO
ABSTRACT This paper presents a monolithic avalanche diode array designed in a commercial AMS 350 nm high-voltage CMOS (HV-CMOS) process. This monolithic detector comprises a single photon avalanche diode (SPAD), active quenching circuit and readout electronics. The SPAD consists of a p+ diffusion/n-well junction surrounded by a shallow p-well acting as a guard ring to prevent edge breakdown. The monolithic detector has a matrix of 20 × 15 pixels. The size of one SPAD pixel is 38 × 92 μm2 . One pixel defined as SPAD and readout electronics has a total size of 115 × 111 μm2 with a fill factor = 24.3% and a chip size of about 2.8 × 2.6 mm2 .
Contents 1. 2. 3. 4. 5.
Introduction ....................................................................................................................................................................................................... Sensor architecture.............................................................................................................................................................................................. Front-end electronics ........................................................................................................................................................................................... Measurement results............................................................................................................................................................................................ Conclusion ......................................................................................................................................................................................................... Acknowledgments ............................................................................................................................................................................................... References..........................................................................................................................................................................................................
1. Introduction A growing interest in single photon detection and imaging can be observed in various scientific and industrial applications such as astroparticle physics (e.g. Cherenkov light detection), meteorology, medicine (e.g. positron emissions tomography), biology (e.g. bioluminescence). Light detection at the single-photon level was invented more than 80 years ago. The photo-multiplier tube (PMT) was the first device used for single-photon detection. PMTs have several disadvantages such as limited detection efficiency, especially for longer wavelengths and are unsuitable for compact design of integrated systems. Semiconductor detectors are a valuable alternative to PMTs due to the well-known advantages of solid state detectors such as small size, low power dissipation, low supply voltage, low cost. A Single-Photon Avalanche Diode (SPAD) is a semiconductor photon sensor operated in the so-called Geiger-mode. When a photon hits an SPAD, the generated charge carriers trigger an avalanche multiplication. The avalanche can produce 105 –106 carriers. The SPAD is sufficiently biased above the diode breakdown voltage. Since the avalanche in Geigermode is self sustained, a quenching circuit [1] must be used to prevent
1 1 2 2 2 2 2
overheating and the destruction of the diode. The purpose of the quenching circuit is to stop the avalanche current by lowering the bias voltage. There are three conditions in which the SPAD operates: reset (where the diode is ‘‘armed’’ with a bias voltage higher than breakdown), avalanche and quenching. A silicon photomultiplier (SiPM) in its simplest form consists of SPADs defining a microcell. In other words, the SiPM is equivalent to an array of SPAD microcells with a quenching circuit. 2. Sensor architecture The HV-CMOS SPAD structure implemented in a deep n-well (DN) forms the cathode and insulates the photosensitive area of the SPAD. The deep n-well is biased at positive 𝑉𝐻𝑉 = 𝑉𝐵𝐷 + 𝑉𝑂𝑉 , 𝑉𝐵𝐷 being the breakdown voltage and 𝑉𝑂𝑉 the overvoltage to operate in Geiger-mode. A p+ implant, acting as the anode, and a shallow n-well (SN) define the high-field region in the active area. The junction is surrounded by a shallow p-well (SP) implantation acting as a guard ring to prevent edge breakdown of the sensor (Fig. 1). The p-substrate is shared with readout electronics. The SPAD signal is DC coupled to the front-end. Since the
∗ Corresponding author. E-mail address: [email protected] (R. Blanco).
https://doi.org/10.1016/j.nima.2018.09.107 Received 29 June 2018; Received in revised form 5 September 2018; Accepted 24 September 2018 Available online xxxx 0168-9002/© 2018 Elsevier B.V. All rights reserved.
Please cite this article in press as: R. Blanco, et al., Silicon photomultiplier detector with multipurpose in-pixel electronics in standard CMOS technology, Nuclear Inst. and Methods in Physics Research, A (2018), https://doi.org/10.1016/j.nima.2018.09.107.
R. Blanco et al.
Nuclear Inst. and Methods in Physics Research, A (
)
–
The external electronics consist of active inhibition and reset switches, fast comparator, edge detection, monostable circuit, 1-bit hit flag, analog time stamp memory, hit-OR bus and data output. If a photon hits the SPAD (set in Geiger-mode) the SPAD signal will rise above the threshold (𝑉𝑡ℎ𝑟 ). The threshold is generated in a bias DAC block implemented on the periphery of the ASIC. This threshold is also used to suppress the dark counts during photon signal generation. As soon as the signal exceeds the threshold, the signal is pulled to 3.3 V level (inhibition switch). At this point the hold time starts. The hold time (delLoHold) can be adjusted with a delay circuit that is connected to the reset input of the RS-flipflop. The output (q signal) of the RS-flipflop controls the inhibition switch and the input of the edge detector. This edge detector triggers the reset switch with a defined edge time (delHiEdge, delLoEdge). The edge time is also applied to the edge detector after the comparator circuit. The relaxation speed (return to base line speed) is dependent on the edge time setting and the VNBias can be stored. Short relaxation time means low VNbias and low edge time setting. When a photon signal (hit signal) is detected, the hit flag stores analog time stamp (ramp signal) and the hit is stored in the 1-bit hit flag, ready for read out. A row can be selected and read out by the data bus. The hit-OR is connected to the monoflop output. Upon receiving monoflop out, the external circuit can generate a store signal that puts the hit latch into store mode. A hit-OR is provided for self-trigger mode. Single pixel, full matrix and self triggered readout is possible.
Fig. 1. Sensor design, full ASIC and pixel layout.
Fig. 2. Simplified schematic diagram of the monolithic detector.
4. Measurement results We present the initial experimental result for the breakdown voltage and the dark count rate (DCR). The breakdown voltage values have been determined from the current–voltage (I–V) characteristics, using a precision source measure unit (Keysight B2901A). A breakdown voltage of 11.7 V was measured at 24.0 ◦ C for an SPAD pixel size of 3496 μm2 . The DCR of one pixel was measured in darkness. At 12.0 V (𝑉𝑂𝑉 ≈ 300 mV) a dark count rate of 610 kHz corresponding to 174 Hz∕μm2 was measured. This DCR is acceptable [2]. Improvements are possible when a lower doped junction is chosen. Furthermore, it was also observed that the DCR is weakly dependent on temperature (Fig. 3). The trap-assisted band-to-band tunneling is responsible for the generation of free charge carriers. We measured a temperature sensitivity for breakdown voltage of ≈ 9 mV ◦ C−1 . 5. Conclusion
Fig. 3. Dark count rate versus temperature.
We presented a monolithic detector including active quenching and readout electronics. This monolithic detector was designed in a commercial 350 nm HV-CMOS process. The measurement results show an acceptable breakdown voltage and DCR. The DCR is weakly dependent on temperature due to trap-assisted band-to-band tunneling.
SPAD n-well is at high-voltage and the n-well for the readout electronics at 3.3 V, a minimum spacing of 15 μm must be allowed between these wells. The corners of the SPAD are round to avoid high electric field peaks. We designed a large SPAD with an active area of 38 × 92 μm2 to increase the fill factor. A fill factor of 24.3% was achieved. The layout design of an SPAD pixel, front-end electronics and the ASIC is shown in Fig. 1.
Acknowledgments This work was supported by the KIT Karlsruhe School of Elementary Particle and Astroparticle Physics (KSETA), Germany.
3. Front-end electronics References Our design is presented in an active quenching circuitry. A simplified schematic diagram of the electronics is shown in Fig. 2. We chose an active quenching circuit in order to achieve a better pixel integration and adjustable quench timing and to avoid a fixed quench timing by an internal RC circuitry (passive quenching).
[1] S. Cova, M. Ghioni, A. Lacaita, C. Samori, F. Zappa, Avalanche photodiodes and quenching circuits for single-photon detection, OSA A386 (1996) 1956–1976. [2] N. D’Ascenzo, X. Zhang, Q. Xie, Application of CMOS technology to silicon photomultiplier sensors, PMC Web (2017) 2204.
2 Please cite this article in press as: R. Blanco, et al., Silicon photomultiplier detector with multipurpose in-pixel electronics in standard CMOS technology, Nuclear Inst. and Methods in Physics Research, A (2018), https://doi.org/10.1016/j.nima.2018.09.107.