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SOI circuits
Microelectronics Journal 34 (2003) 889–895 www.elsevier.com/locate/mejo
Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits D. De Venutoa,*, M.J. Ohletzb a
Dipartimento di Elettrotecnica ed Elettronica—Politecnico di Bari, via Orabona 4, 70125 Bari, Italy b Alcatel Microelectronics, Excelsiorlaan 44-46, 1930 Zaventem, Belgium Received 12 November 2002; accepted 16 April 2003
Abstract The possibility to perform realistic fault simulations for Silicon-On-Insulator circuits is investigated. A simple but complete fault simulation model (fsm) for a technology specific effect is described. The effect considered known as kink effect is typical for partially depleted devices but can occur in the presence of a floating body or in the sub-threshold region even in fully depleted devices causing wrong performances. The model proposed here comprises of only a single additional transistor with a controlled body current. It is not a real physical transistor but just one to describe the electrical behaviour of the device when the critical kink-effect situation occurs and for this reason does not increase the simulation time. From the comparison with device characterization measurements on a 1 mm technology device a good matching with the fsm was found. q 2003 Elsevier Ltd. All rights reserved. Keywords: Silicon-On-Insulator device; Kink-effect; Fault simulation model; Test; Iddq ; Iccq
1. Introduction Silicon-On-Insulator (SOI) is becoming an emerging cost competitive mainstream technology provided by most semiconductor manufacturers. Typical technologies are today 0,13 mm SOI CMOS with 200– 300 mm wafers. SOI thin-film in particular is used for high-speed applications, for low power consumer, medical or communication circuits e.g. multi-Gbit DRAM, 1-GHz mP, pace makers. SOI thick-film is more frequently encountered in high voltage and temperature applications (. 150 8C ambient) for industrial, automotive, aerospace applications and MEMS. Both kinds of SOI circuits, partially depleted (PD) and fully depleted (FD), benefit from the dielectric insulation of the devices, which drastically reduces the diode areas and hence the leakage currents. Full depletion of the channel is also beneficial for the temperature behaviour of the threshold voltage VTO : FD SOI exhibits an absolute VTO decrease lower than 1 mV/8K. On the other hand, PD * Corresponding author. E-mail addresses: [email protected] (D. De Venuto), michael_ohletz@ amis.com (M.J. Ohletz). 0026-2692/03/$ - see front matter q 2003 Elsevier Ltd. All rights reserved. doi:10.1016/S0026-2692(03)00157-5
devices behave like normal bulk devices and the average decrease of VTO in some processes is about 2.3 mV/8K. The paper deals with modelling typical effects related to the floating body condition, known as kink effects. The model is intended for the electrical fault simulation. These effects are normally not present in bulk devices operated at room temperature when substrate or well contacts are provided, which is usually the case. In PD devices the kink effects are present due to an additional current generated by impact ionisation between the drain and the body (left floating) and then collected trough the body-source diode. FD SOI n-channel transistor should be free from these effects. However, if the negative back-gate bias is used to induce an accumulation layer at the back interface the device behaves as a PD device, and the kink effects appear. The device model used in standard circuit simulators comes from the standard bulk device equations describing the behaviour and neglecting the parasitic mechanisms typical for SOI devices. A correct fault simulation cannot neglect those parasitic effects, which can have a drastic impact in the result of the fault simulation as has been described in Ref. [1]. It is important to identify a suitable way to electrically taking into account the parasitic effect during the fault simulation without increasing
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the simulation time by a too complex fault simulation model (fsm) [2,3] which describes the effect to be fault simulated by an electrical equivalent circuit. The model is compliant with level 5 of SPICE making use of the EKV model [4] for both bulk CMOS and for FD SOI CMOS transistors. Results from simulations using the model are shown and discussed here. The comparison with the measurements on a 1 mm technology and the results from simulation show a reasonable matching of the results. The impact in using such a realistic model in the fault simulation is investigated and results for an example are reported.
2. SOI specific effect: the kink effect Several parasitic phenomena appearing in SOI MOSFETs are related to the impact ionisation in the high electric field region near the drain. Some of them, such as the reduced drain breakdown voltage, are related to the parasitic NPN bipolar transistor found in the n-channel SOI MOSFET. Others are induced by injection of charges (holes or electrons) due to the high potential or temperature reached or due to the short channel effect. Some of them at the same time impacting and limiting the SOI analogue and mixed-signal design are the kink effects. These effects are characterized by the appearance of a so-called ‘kink’ in the output characteristics of an SOI MOSFET resulting in an increase of the current, as illustrated in Fig. 1. Since here just a slight increase is visible in the ID 2 VDS measurements (for a 1 mm FD SOI technology) depicted in Fig. 1(a) (right hand of the vertical bar), the derivative of the current with respect to the drain source voltage is evaluated. Fig. 1(b) depicts the result of this evaluation in form of the output transconductance versus VDS : As indicated by the arrows, after a voltage range where the behaviour of the device in the saturation region is comparable to a bulk device (the transconductance decreases as the drain voltage increases), its drain current suddenly rises with a discontinuity in the drain current as soon as the drain voltage exceeds a certain value, which here is 1.5 V. It can be concluded that in strong inversion, with a smaller gate voltage, the drain current needed to trigger the kink effects is smaller and that as shown in Fig. 1(b) kink effects worsen the differential conductance of the device. This may have a serious impact on the performance if the device is used for analogue circuits.
Fig. 1. (a) Measured Id-Vds characteristic of a FD SOI nMOS transistor with kink-effect above 1.5 V. (b) Output conductance for the above SOI nMOS transistor versus Vds for measured characteristic from Fig. 1(a). The kink-effect occurs above 1.5 V.
Thus, the frequency-dependency of the kink effects affects the stability of the circuit. Kink effects are caused by impact ionisation of the PD SOIMOS devices and the parasitic BJT effect. As shown in Fig. 2, for a large drain voltage, the impact ionisation caused by the travelling electrons with high energy in the high electric field region near the drain results in a large amount of electron/hole pairs. The electrons move towards the drain and the holes towards the floating body and thus accumulate at the buried oxide (BOX) boundary near the source. Thus, the local body potential increases and the local threshold decreases, which triggers the sudden rise in the drain current. When the accumulation of holes and the related
2.1. Kink effects: physical mechanism The kink effects of a SOI device are strongly dependent on its operating speed. At lower operating frequencies, kink effects are more serious, which occurs at a smaller drain voltage. On the other hand, at high operating frequencies, kink effects become less significant and tend to disappear.
Fig. 2. Occurrence of the kink effects in a PD NMOS device.
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potential reach a certain extent, the source/body diode turns on. As a result, the body potential does not rise further. Instead, it maintains at 0.6 – 0.7 V, which is the internal mechanism causing the kink effects. From the analysis above, kink effects of PD SOI NMOS devices are related to the accumulation of holes in the body. Kink effects are strongly correlated to the operating frequency of the device. Since impact ionisation of holes is much smaller than of electrons SOI PMOS devices show much smaller kink effects compared to NMOS devices. Kink effects are also determined by the structure of a PD SOI device, i.e. the thin-film doping density, the oxide thickness and the channel length. Also the back gate bias determines kink effects of a PD SOI NMOS. With a more negative back gate bias, it is easier to have hole accumulation in the thin film, and thus the kink effects are more serious. The back gate bias effects on the kink effects are especially visible for SOI devices, which are defined at the boundary between FD and PD. As long as the back gate bias is sufficiently negative, even in an FD SOI device, hole accumulation in the thin film can still trigger kink effects, as shown in Fig. 1.
3. Avoidance of the kink effects in SOI To avoid the kink effects in a straightforward way is to connect the body contact of the thin film to source or to ground. Once the body of the thin film is tied to source or ground, the holes are evacuated via the contact instead of being accumulated in the thin film. However, the body contact approach also has its own limitations. When the channel length of the device is small, due to the very narrow neutral region from the body contact to the internal body, its equivalent body resistance can be very large. Moreover, the adoption of the body contact approach may result in an increase of area in the layout and hence increased complexity in interconnects. To decrease the kink effects, Schottky body contacts have been used. To realise such contacts, after the source/drain implant, silicide is formed on p-type and nþ source regions simultaneously. In the region with silicide in contact with the p-type region, the Schottky diode is formed to provide a way to remove the holes from the body to the source. Usually, Schottky diodes are also formed at the drain side for the PD SOI devices used as pass transistors and in the circuits for devices without a fixed source/drain configuration. Unfortunately with such an approach, the reverse biased current is larger, which results in a larger leakage current in the source/drain region. The above techniques cannot effectively resolve the problems with the large-body contact resistance due to a large channel width. A technological solution, which seems to be more suitable, is to implant germanium dopants to form SiGe in the source/drain region. As result, the potential barrier for the holes between the source and the body is reduced. Thus, the accumulated holes at the bottom of
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the thin film can be easily expelled to the source and the kink effects are reduced. In addition the function of the parasitic bipolar is weakened. Therefore, the breakdown voltage of the device is improved. Since the whole source region can be used to remove holes, no body contact resistance problems exist. The Ge-implanted source/drain techniques to reduce kink effects and to improve the breakdown voltage of the PD SOI NMOS devices can be further visualized by studying the lateral parasitic bipolar device, which uses the source/body/drain as the emitter/ base/collector. With the implanted-Ge source (emitter), bandgap narrowing occurs. The base current increases and the current gain of the parasitic bipolar falls [5,6]. There are also other technological ways to reduce the kink effects in PD SOI device, but normally they increase the cost of the device production and for this reason they are not adopted when a FD device is realised, usually kink effects free. In FD circuits the kink effects are unlikely and are simply avoided by cascading NMOS devices when a high source drain voltage occurs. In this way the voltage drop on each device is reduced avoiding that the drainsource voltage overcomes the value, which induces the occurrence of kink effects. In the presence of a manufacturing defect however, this cascode transistor may be affected in such a way that the voltage drop on the transistor below the cascode transistor is increased. This gives rise to the kink effects on the device to be protected by this cascode transistor. For this reason within the process of a correct fault simulation the possibility that the cascode device is affected should be taken into account.
4. Modelling of the kink effect within the fault simulation For a high outgoing quality it is important to discriminate good from defective devices with a high degree of confidence. To achieve this goal, fault simulators are necessary for the fault simulation of the impact of possible defects described as faults in the schematics. Various studies have been carried out assuming defects likely to occur in CMOS bulk process lines. Those defects are then mapped onto faults at schematic level, e.g. a short circuit between two nodes. Within the fault simulator, however, it may be necessary to model those faults by specific simulation models referred to as fsm [2,3]. A fsm has to be as accurately as necessary to model the impact of a defect, in order to predict the faulty behaviour of the circuit while on the other hand the fsm model should be as simple as possible to limit the computational cost. The effectiveness of the tests derived from the fault simulation in turn later impact the production test time [4], which for economical reasons has to be as low as possible. Circuit level fault simulations can be carried out using electrical simulators, like SPICE or ELDO. Based on those programs fault simulation tools like AnaFAULT [7] have been developed which allow the simple extension of
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existing fsm. Those tools provide fsm in the schematic description of the circuit but they don’t take in account the possible consequence of second order effect on the device due to the spot defect, assuming this aspect already as being included in the SPICE model. This is normally true for bulk CMOS devices, but in SOI it is only true for PD devices. 4.1. SOI models As shown in Fig. 3, the PD SOI technology SPICE models are composed of the surface MOS device and the parasitic bipolar device BJT connected in parallel, considering the neutral region in the thin film region [6]. The emitter of the parasitic BJT and the source of the surface MOS device are connected together (S in Fig. 3). In addition, the collector of the parasitic BJT and the drain of the surface MOS device share the same terminal (D). The base of the BJT, which is connected to the substrate of the surface MOS device, becomes a floating body node (B). A capacitor (Cburied) has been adopted to account for the effect of the BOX. In PD SOI-technology SPICE models, conventional drain currents and capacitance models for the surface MOS part and the Gummel-Poon model for the parasitic BJT part have been used. Moreover, one key component analysed by the model, is the impact ionisation current generated by the surface MOS device, which becomes the triggering base current of the parasitic BJT to reflect the floating body effects of the PD SOI MOS device. By the inclusion of the body node, PD SOI SPICE model can accurately predict the discontinuity transition in the drain current curves and the sudden increase in the bodysource voltage curve at the onset of the kink effects. Also for FD several models already exist, even more complex as for PD i.e. BSIMSOI, SOISPICE, LETISOI [8]. The first two models were developed by universities and are available in the public domain. BSIMSOI and SOISPICE both address fully and PD devices. Circuit designers must evaluate the different models to fit them to their needs [8].
LETISOI developed at LETI (Laboratoire d’Electronique de Technologie de l’Information, Grenoble France) is dedicated to PD devices. SOISPICE-5.0 (an enhanced version of Spice2) contains the latest upgrades in the physical, process-based UFSOI (developed at the University of Florida) MOSFET models (enhancement-mode). The models are charge-based with five terminals, and have a floating-body option. The model for the FD device properly accounts for the charge coupling between the front and back gates, and includes a twodimensional analysis of the electrostatic potential in the SOI film and underlying BOX for sub-threshold region operation. The model assumes that the film is strongly FD, except in and near the accumulation region where it accounts for the majority-carrier charge, and hence dynamic floating-body effects. The non-fully depleted (NFD) device model properly accounts for DC as well as for dynamic floating-body effects defined by capacitive coupling and carrier recombination/generation. Both models include an optional quasi-2D model accounting for the (coupled) parasitic BJT (current and charge), which can be driven in the floating-body mode by a transient body charging current and/or generation current, including the current due to impact ionisation. This current is characterized by a nonlocal, carrier temperature-dependent model for the ionisation rate integrated across the channel (S), (optional) LDD, and drain. The charge modelling has been recently upgraded [9]. All terminal charges (including MOS and bipolar components) and their derivatives are continuous for all bias conditions. Substrate depletion charges under the source and drain regions, which become important when the BOX is scaled, is included as components of the source, drain, and back-gate charge. The temperature dependence for both models is also implemented, without the need for any additional parameters. Also physics-based noise modelling for AC simulation can be performed, which accounts for the thermal noise from the channel and parasitic series resistances, shot noise at the source and drain junctions,
Fig. 3. PD NMOS SOI cross-section and BiCMOS SPICE model based of the kink effects [6].
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as well as flicker noise in the channel. The temperaturedependence modelling is the basis for a self-heating simulation option, which uses special iteration control for the local device temperature node that yields good convergence even for large circuits. Of course the use of such model requires the knowledge of the complete process parameters to describe the model with the required precision. However, these parameters are not always available from the foundries. In particular for FD devices the behaviour is so close to the bulk device that it does not justify the use of such complex models. Normally, an existing bulk model can be adapted for FD devices, by modifying the threshold voltage and the charge equations to account for the relationship of the depletion charge to silicon thickness, e.g. level 5 considering the EKV model, in which the fourth contact, normally considered as bulk, in this case is the back gate. This is not correct with respect to the physical meaning of the equations. However, looking at to the Eq. (1) of the channel potential VP in bulk MOS, this potential is controlled by the substrate (node B, Fig. 3) through the factor g0 ; which is the bias and the geometry dependent body effect factor and the front gate VG through V 0G : 8 0sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 0 2 > 0 > y y > 0 < V G 2 PHI 2 g0 @ V 0G þ 2 A for V 0G . 0 2 2 VP ¼ > > > : 2PHI for V 0G , 0 ð1Þ being: pffiffiffiffiffi V 0G ¼ VG 2 VTO 2 DVRSCE þ PHI þ GAMMAa PHI
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The relation between VP and the bulk potential VB is non-linear. In FD SOI this potential is controlled by the back gate and the front gate. Therefore, it makes sense to use the node B for the back gate. In FD SOI, the relation VB and VP is linear, and the SPICE parameters GAMMA and PHI lose their physical meaning and become simple fitting parameters for the function VP : In this model there is no space for parasitic mechanisms typical for SOI devices, such as the self-heating and the kink effect. Therefore to perform a fault simulation without considering those phenomena can lead to wrong conclusions. 4.2. Fault simulation model for FD SOI In order to allow for the evaluation of the kink effect in FD SOI devices without employing complex equations to just electrically simulate the physical phenomena, the fsm shown in Fig. 4 has been developed. The consequence of the impact ionisation is a current of holes flowing between the drain and the body (Fig. 2). To simulate the diode between the drain and the forward biased body, a bulk PMOS device (M3) is inserted on the drain of the SOI NMOS device. To realistically describe the area where the diode is created, this NMOS device for which the kink effect is considered is split into two devices M1 and M2. Those two devices having the same input and being in series represent the original NMOS SOI device with a channel length (L) equal to the sum of the channel lengths of M1 and M2. In this way the diode can be positioned in the middle if the body position or the carriers accumulated should be exactly between the source and the drain. By assigning a different L to M1 and M2 the position can be moved e.g. closer to the drain. The voltage source V8 (Vdc ¼ 0) is just used to separate the current contributions of the devices. The output current is measured at the drain of
Fig. 4. Kink effect fault simulation model.
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Fig. 7. DC transfer function in the presence of a drain-source short on M13 and the fault-free transfer function.
5. Impact of the modelling of the parasitic effect during the fault simulation
Fig. 5. (a) Simulated Id-Vds characteristic of a SOI nMOS transistor with kink-effect above 1.5 V using the chosen electrical model. (b) Simulated output conductance for the above SOI nMOS versus VDS.
transistor M1 as indicated by the small probe in Fig. 4. The PMOS M3 is a bulk device and the fourth terminal is the body terminal. The diode is created between the source (pþ) and the bulk (n) when the drain voltage of the device M1 is high enough to switch on the junction. The simulated output characteristics of the SOI NMOS including the kink model are shown in Fig. 5(a). In Fig. 5(b) the derivative of the current, i.e. the output transconductance is shown. Both plots are in a good agreement with the measured curves shown in Fig. 1(a) and (b).
Fig. 6. Op-amp output stage and fault simulation models for short and Kink effect (pMOS and voltage source).
This paragraph shows the impact of the parasitic effect during the fault simulation. Fig. 6 depicts an example of an output stage of a SOI operational amplifier [10]. The NMOS transistors (M12) are cascoded in order to avoid the kink effect occurrence for VDS beyond 1.5 V. It has been proven that the normal variation of the technological parameters does not impact the supply current and also not significantly the output voltage. The impact of the parasitic kink effect has been investigated assuming that it occurs due to a defect in the circuit. As fault assumptions the defect and layout oriented L2RFM [11] scheme was applied for the subsequent investigations. Besides the focus on the layout-realistic fault assumption the technology specific defect conditions, i.e. those of the SOI technology have to be investigated. In general, SOI appears to be less sensitive to defects than bulk MOS due to the dielectric isolation of the devices. On the other side, however, due to the structure of the abovedescribed SOI technology, specific defects and failure mechanisms have to be assumed and modelled in a respective defect-oriented manner by respective fsm. As mentioned before, a special fsm-model for the kink effect was used. To create the undesired path for the holes current from drain to source, a pMOS transistor was used. This transistor is operated as a diode by which the respective holes current M12 can be simulated, when a short on
Fig. 8. Supply currents for the two simulated situations with and without drain-source short.
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Fig. 9. Supply current Iccq in the presence of the Kink effect due to local imperfection of the thin film layer affecting M12.
the transistor M13 is induced. The simplified model is depicted in Fig. 6 for the kink effect simulation on transistor M12. In the first simulation a drain-source short on M13 was assumed without considering the kink effect. Here as fsm for the short fault a simple resistor of 10 mV was used connected between drain and source of M13 in order to model this drainsource short. For the sake of comparison also a simulation with a resistor value of 10 GV was performed, to implement the faultfree case with no short or high ohmic short. Both the DC output transfer function (Fig. 7) and the supply current Iccq (Fig. 8) have been plotted. As it can be seen in both plots, the drain-source short can only bedetectedifthe evaluation isdone at theright DC input voltage, which is in this case 1.1 V. This however, is not a feasible condition due to the presence of parameters variation. Also the resistance of the actual short fault impacts the detectability. In SOI however, the short alone in this cascode configuration is not present, but accompanied by the kink-effect on the transistor M12. Due to this normal parasitic effect the detectability is improved as described in the last simulation. In this last simulation the supply current Iccq condition is shown in the presence of the kink effect using the above described fsm for the kink effect. Again the DC transfer function was simulated and it turned out to be the same as the one shown in Fig. 7. As already shown in this figure it was not possible to detect this defect in the voltage of the output signal of the operational amplifier. In the supply current Iccq ; however, a significant deviation can be identified. Thus, a clear detection of the defect over a wide input voltage range is possible. The detection due to the kink effect ranges between 0 and 1.1 V. In the fault-free case the supply current decreases from about 425– 350 mA at 1.1 V. Due to the kink effect, however, the decrease starts at 750 mA and linearly reaches 690 mA at 1.1 V (Fig. 9). Note, that from about 1.3– 2.0 V no detection of this effect is visible in the Iccq as the current enters the same range as in case of the fault-free circuit. 6. Conclusion The paper deals with the modelling of one of the main parasitic effects which affecting SOI devices: the kink
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effects. It is explained that FD SOI n-channel transistors is normally free of this effect. However, if the negative back-gate bias is used, to induce an accumulation layer at the back interface the device behaves as a PD device, and the kink appears. The device models used in standard circuit simulators do not always take into account such phenomena. In order to insert those parasitic effects in the course of fault simulations a simple electrical model, referred to as fsm of the kink effects has been presented. This model comprises of a single additional pMOS transistor where the body current is controlled by the drain-source voltage of the transistor affected by the impact ionisation. Results from fault simulations employing the kink effect fsm have been shown and discussed. From those simulations is demonstrated, that specific defects in the cascode of circuits can render a circuit into the kink effect region. Due to this effect the detectability of the respective defects is enhanced. Without such a model of the kink effect however, those defects appear as invisible in the simulation, thought in reality they become visible in the supply current. In consequence the fault coverage as resulting from a fault simulation without modelling the kink effect is not comprehensive, i.e. too low. Due to the simplicity of the fsm the additional cost of simulation time is negligible.
References [1] D. De Venuto, M. Kayal, M.J. Ohletz, Fault detection in CMOS/SOI mixed-signal circuit using the quiescent current test, Microelectronic Journal 33/5–6 (2002) 387–397. Elsevier Science. [2] M.J. Ohletz, Fault modelling and simulation for the test of integrated analog and mixed-signal circuits, in: A.S. Gerson, Machado (Eds.), Low-Power HF Microelectronics—a unified approach, Eighth ed., 1996, pp. 475–510, Chapter 13. [3] M.J. Ohletz, Hybrid Built-In Self-Test (HBIST) for mixed analogue/ digital integrated circuits, Proceedings of Second European Test Conference April 10–12 (1991) 307–316. [4] M. Bucher, C. Enz, C. Lallement, Accurate MOS modelling for EKV MOST Model, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS’96), Trento, Italy 9 (1996) 145–150. [5] J.P. Colinge, Silicon-On-Insulator Technology: Materials to VLSI, Second ed., Kluwer Academic Publishers, Dordrecht, 1997. [6] J.B. Kuo, S.C. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits, Wiley, New York, 2001. [7] M.J. Ohletz, Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits, Proceedings of ITC (1996) 776–785. [8] J.-L. Pelloie, A. Auberton-Herve´, Low-power, high-performance SOI CMOS, Solid State Technol. 44 (11) (2001) 63 –68. [9] www.soi.tec.ufl.edu [10] D. De Venuto, Int. Rep. EUREKA proj. HERO, EPFL-Lausanne, 2000 [11] M.B. Santos, F.M. Gonc¸alves, M.J. Ohletz, J.P. Texeira, et al., Defected oriented testing of analogue and mixed-signal ICs, Proceedings of fifth International Conference On Electronic Circuits and Systems (ICECS) 2 (1998) 419–424.
Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits D. De Venutoa,*, M.J. Ohletzb a
Dipartimento di Elettrotecnica ed Elettronica—Politecnico di Bari, via Orabona 4, 70125 Bari, Italy b Alcatel Microelectronics, Excelsiorlaan 44-46, 1930 Zaventem, Belgium Received 12 November 2002; accepted 16 April 2003
Abstract The possibility to perform realistic fault simulations for Silicon-On-Insulator circuits is investigated. A simple but complete fault simulation model (fsm) for a technology specific effect is described. The effect considered known as kink effect is typical for partially depleted devices but can occur in the presence of a floating body or in the sub-threshold region even in fully depleted devices causing wrong performances. The model proposed here comprises of only a single additional transistor with a controlled body current. It is not a real physical transistor but just one to describe the electrical behaviour of the device when the critical kink-effect situation occurs and for this reason does not increase the simulation time. From the comparison with device characterization measurements on a 1 mm technology device a good matching with the fsm was found. q 2003 Elsevier Ltd. All rights reserved. Keywords: Silicon-On-Insulator device; Kink-effect; Fault simulation model; Test; Iddq ; Iccq
1. Introduction Silicon-On-Insulator (SOI) is becoming an emerging cost competitive mainstream technology provided by most semiconductor manufacturers. Typical technologies are today 0,13 mm SOI CMOS with 200– 300 mm wafers. SOI thin-film in particular is used for high-speed applications, for low power consumer, medical or communication circuits e.g. multi-Gbit DRAM, 1-GHz mP, pace makers. SOI thick-film is more frequently encountered in high voltage and temperature applications (. 150 8C ambient) for industrial, automotive, aerospace applications and MEMS. Both kinds of SOI circuits, partially depleted (PD) and fully depleted (FD), benefit from the dielectric insulation of the devices, which drastically reduces the diode areas and hence the leakage currents. Full depletion of the channel is also beneficial for the temperature behaviour of the threshold voltage VTO : FD SOI exhibits an absolute VTO decrease lower than 1 mV/8K. On the other hand, PD * Corresponding author. E-mail addresses: [email protected] (D. De Venuto), michael_ohletz@ amis.com (M.J. Ohletz). 0026-2692/03/$ - see front matter q 2003 Elsevier Ltd. All rights reserved. doi:10.1016/S0026-2692(03)00157-5
devices behave like normal bulk devices and the average decrease of VTO in some processes is about 2.3 mV/8K. The paper deals with modelling typical effects related to the floating body condition, known as kink effects. The model is intended for the electrical fault simulation. These effects are normally not present in bulk devices operated at room temperature when substrate or well contacts are provided, which is usually the case. In PD devices the kink effects are present due to an additional current generated by impact ionisation between the drain and the body (left floating) and then collected trough the body-source diode. FD SOI n-channel transistor should be free from these effects. However, if the negative back-gate bias is used to induce an accumulation layer at the back interface the device behaves as a PD device, and the kink effects appear. The device model used in standard circuit simulators comes from the standard bulk device equations describing the behaviour and neglecting the parasitic mechanisms typical for SOI devices. A correct fault simulation cannot neglect those parasitic effects, which can have a drastic impact in the result of the fault simulation as has been described in Ref. [1]. It is important to identify a suitable way to electrically taking into account the parasitic effect during the fault simulation without increasing
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the simulation time by a too complex fault simulation model (fsm) [2,3] which describes the effect to be fault simulated by an electrical equivalent circuit. The model is compliant with level 5 of SPICE making use of the EKV model [4] for both bulk CMOS and for FD SOI CMOS transistors. Results from simulations using the model are shown and discussed here. The comparison with the measurements on a 1 mm technology and the results from simulation show a reasonable matching of the results. The impact in using such a realistic model in the fault simulation is investigated and results for an example are reported.
2. SOI specific effect: the kink effect Several parasitic phenomena appearing in SOI MOSFETs are related to the impact ionisation in the high electric field region near the drain. Some of them, such as the reduced drain breakdown voltage, are related to the parasitic NPN bipolar transistor found in the n-channel SOI MOSFET. Others are induced by injection of charges (holes or electrons) due to the high potential or temperature reached or due to the short channel effect. Some of them at the same time impacting and limiting the SOI analogue and mixed-signal design are the kink effects. These effects are characterized by the appearance of a so-called ‘kink’ in the output characteristics of an SOI MOSFET resulting in an increase of the current, as illustrated in Fig. 1. Since here just a slight increase is visible in the ID 2 VDS measurements (for a 1 mm FD SOI technology) depicted in Fig. 1(a) (right hand of the vertical bar), the derivative of the current with respect to the drain source voltage is evaluated. Fig. 1(b) depicts the result of this evaluation in form of the output transconductance versus VDS : As indicated by the arrows, after a voltage range where the behaviour of the device in the saturation region is comparable to a bulk device (the transconductance decreases as the drain voltage increases), its drain current suddenly rises with a discontinuity in the drain current as soon as the drain voltage exceeds a certain value, which here is 1.5 V. It can be concluded that in strong inversion, with a smaller gate voltage, the drain current needed to trigger the kink effects is smaller and that as shown in Fig. 1(b) kink effects worsen the differential conductance of the device. This may have a serious impact on the performance if the device is used for analogue circuits.
Fig. 1. (a) Measured Id-Vds characteristic of a FD SOI nMOS transistor with kink-effect above 1.5 V. (b) Output conductance for the above SOI nMOS transistor versus Vds for measured characteristic from Fig. 1(a). The kink-effect occurs above 1.5 V.
Thus, the frequency-dependency of the kink effects affects the stability of the circuit. Kink effects are caused by impact ionisation of the PD SOIMOS devices and the parasitic BJT effect. As shown in Fig. 2, for a large drain voltage, the impact ionisation caused by the travelling electrons with high energy in the high electric field region near the drain results in a large amount of electron/hole pairs. The electrons move towards the drain and the holes towards the floating body and thus accumulate at the buried oxide (BOX) boundary near the source. Thus, the local body potential increases and the local threshold decreases, which triggers the sudden rise in the drain current. When the accumulation of holes and the related
2.1. Kink effects: physical mechanism The kink effects of a SOI device are strongly dependent on its operating speed. At lower operating frequencies, kink effects are more serious, which occurs at a smaller drain voltage. On the other hand, at high operating frequencies, kink effects become less significant and tend to disappear.
Fig. 2. Occurrence of the kink effects in a PD NMOS device.
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potential reach a certain extent, the source/body diode turns on. As a result, the body potential does not rise further. Instead, it maintains at 0.6 – 0.7 V, which is the internal mechanism causing the kink effects. From the analysis above, kink effects of PD SOI NMOS devices are related to the accumulation of holes in the body. Kink effects are strongly correlated to the operating frequency of the device. Since impact ionisation of holes is much smaller than of electrons SOI PMOS devices show much smaller kink effects compared to NMOS devices. Kink effects are also determined by the structure of a PD SOI device, i.e. the thin-film doping density, the oxide thickness and the channel length. Also the back gate bias determines kink effects of a PD SOI NMOS. With a more negative back gate bias, it is easier to have hole accumulation in the thin film, and thus the kink effects are more serious. The back gate bias effects on the kink effects are especially visible for SOI devices, which are defined at the boundary between FD and PD. As long as the back gate bias is sufficiently negative, even in an FD SOI device, hole accumulation in the thin film can still trigger kink effects, as shown in Fig. 1.
3. Avoidance of the kink effects in SOI To avoid the kink effects in a straightforward way is to connect the body contact of the thin film to source or to ground. Once the body of the thin film is tied to source or ground, the holes are evacuated via the contact instead of being accumulated in the thin film. However, the body contact approach also has its own limitations. When the channel length of the device is small, due to the very narrow neutral region from the body contact to the internal body, its equivalent body resistance can be very large. Moreover, the adoption of the body contact approach may result in an increase of area in the layout and hence increased complexity in interconnects. To decrease the kink effects, Schottky body contacts have been used. To realise such contacts, after the source/drain implant, silicide is formed on p-type and nþ source regions simultaneously. In the region with silicide in contact with the p-type region, the Schottky diode is formed to provide a way to remove the holes from the body to the source. Usually, Schottky diodes are also formed at the drain side for the PD SOI devices used as pass transistors and in the circuits for devices without a fixed source/drain configuration. Unfortunately with such an approach, the reverse biased current is larger, which results in a larger leakage current in the source/drain region. The above techniques cannot effectively resolve the problems with the large-body contact resistance due to a large channel width. A technological solution, which seems to be more suitable, is to implant germanium dopants to form SiGe in the source/drain region. As result, the potential barrier for the holes between the source and the body is reduced. Thus, the accumulated holes at the bottom of
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the thin film can be easily expelled to the source and the kink effects are reduced. In addition the function of the parasitic bipolar is weakened. Therefore, the breakdown voltage of the device is improved. Since the whole source region can be used to remove holes, no body contact resistance problems exist. The Ge-implanted source/drain techniques to reduce kink effects and to improve the breakdown voltage of the PD SOI NMOS devices can be further visualized by studying the lateral parasitic bipolar device, which uses the source/body/drain as the emitter/ base/collector. With the implanted-Ge source (emitter), bandgap narrowing occurs. The base current increases and the current gain of the parasitic bipolar falls [5,6]. There are also other technological ways to reduce the kink effects in PD SOI device, but normally they increase the cost of the device production and for this reason they are not adopted when a FD device is realised, usually kink effects free. In FD circuits the kink effects are unlikely and are simply avoided by cascading NMOS devices when a high source drain voltage occurs. In this way the voltage drop on each device is reduced avoiding that the drainsource voltage overcomes the value, which induces the occurrence of kink effects. In the presence of a manufacturing defect however, this cascode transistor may be affected in such a way that the voltage drop on the transistor below the cascode transistor is increased. This gives rise to the kink effects on the device to be protected by this cascode transistor. For this reason within the process of a correct fault simulation the possibility that the cascode device is affected should be taken into account.
4. Modelling of the kink effect within the fault simulation For a high outgoing quality it is important to discriminate good from defective devices with a high degree of confidence. To achieve this goal, fault simulators are necessary for the fault simulation of the impact of possible defects described as faults in the schematics. Various studies have been carried out assuming defects likely to occur in CMOS bulk process lines. Those defects are then mapped onto faults at schematic level, e.g. a short circuit between two nodes. Within the fault simulator, however, it may be necessary to model those faults by specific simulation models referred to as fsm [2,3]. A fsm has to be as accurately as necessary to model the impact of a defect, in order to predict the faulty behaviour of the circuit while on the other hand the fsm model should be as simple as possible to limit the computational cost. The effectiveness of the tests derived from the fault simulation in turn later impact the production test time [4], which for economical reasons has to be as low as possible. Circuit level fault simulations can be carried out using electrical simulators, like SPICE or ELDO. Based on those programs fault simulation tools like AnaFAULT [7] have been developed which allow the simple extension of
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existing fsm. Those tools provide fsm in the schematic description of the circuit but they don’t take in account the possible consequence of second order effect on the device due to the spot defect, assuming this aspect already as being included in the SPICE model. This is normally true for bulk CMOS devices, but in SOI it is only true for PD devices. 4.1. SOI models As shown in Fig. 3, the PD SOI technology SPICE models are composed of the surface MOS device and the parasitic bipolar device BJT connected in parallel, considering the neutral region in the thin film region [6]. The emitter of the parasitic BJT and the source of the surface MOS device are connected together (S in Fig. 3). In addition, the collector of the parasitic BJT and the drain of the surface MOS device share the same terminal (D). The base of the BJT, which is connected to the substrate of the surface MOS device, becomes a floating body node (B). A capacitor (Cburied) has been adopted to account for the effect of the BOX. In PD SOI-technology SPICE models, conventional drain currents and capacitance models for the surface MOS part and the Gummel-Poon model for the parasitic BJT part have been used. Moreover, one key component analysed by the model, is the impact ionisation current generated by the surface MOS device, which becomes the triggering base current of the parasitic BJT to reflect the floating body effects of the PD SOI MOS device. By the inclusion of the body node, PD SOI SPICE model can accurately predict the discontinuity transition in the drain current curves and the sudden increase in the bodysource voltage curve at the onset of the kink effects. Also for FD several models already exist, even more complex as for PD i.e. BSIMSOI, SOISPICE, LETISOI [8]. The first two models were developed by universities and are available in the public domain. BSIMSOI and SOISPICE both address fully and PD devices. Circuit designers must evaluate the different models to fit them to their needs [8].
LETISOI developed at LETI (Laboratoire d’Electronique de Technologie de l’Information, Grenoble France) is dedicated to PD devices. SOISPICE-5.0 (an enhanced version of Spice2) contains the latest upgrades in the physical, process-based UFSOI (developed at the University of Florida) MOSFET models (enhancement-mode). The models are charge-based with five terminals, and have a floating-body option. The model for the FD device properly accounts for the charge coupling between the front and back gates, and includes a twodimensional analysis of the electrostatic potential in the SOI film and underlying BOX for sub-threshold region operation. The model assumes that the film is strongly FD, except in and near the accumulation region where it accounts for the majority-carrier charge, and hence dynamic floating-body effects. The non-fully depleted (NFD) device model properly accounts for DC as well as for dynamic floating-body effects defined by capacitive coupling and carrier recombination/generation. Both models include an optional quasi-2D model accounting for the (coupled) parasitic BJT (current and charge), which can be driven in the floating-body mode by a transient body charging current and/or generation current, including the current due to impact ionisation. This current is characterized by a nonlocal, carrier temperature-dependent model for the ionisation rate integrated across the channel (S), (optional) LDD, and drain. The charge modelling has been recently upgraded [9]. All terminal charges (including MOS and bipolar components) and their derivatives are continuous for all bias conditions. Substrate depletion charges under the source and drain regions, which become important when the BOX is scaled, is included as components of the source, drain, and back-gate charge. The temperature dependence for both models is also implemented, without the need for any additional parameters. Also physics-based noise modelling for AC simulation can be performed, which accounts for the thermal noise from the channel and parasitic series resistances, shot noise at the source and drain junctions,
Fig. 3. PD NMOS SOI cross-section and BiCMOS SPICE model based of the kink effects [6].
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as well as flicker noise in the channel. The temperaturedependence modelling is the basis for a self-heating simulation option, which uses special iteration control for the local device temperature node that yields good convergence even for large circuits. Of course the use of such model requires the knowledge of the complete process parameters to describe the model with the required precision. However, these parameters are not always available from the foundries. In particular for FD devices the behaviour is so close to the bulk device that it does not justify the use of such complex models. Normally, an existing bulk model can be adapted for FD devices, by modifying the threshold voltage and the charge equations to account for the relationship of the depletion charge to silicon thickness, e.g. level 5 considering the EKV model, in which the fourth contact, normally considered as bulk, in this case is the back gate. This is not correct with respect to the physical meaning of the equations. However, looking at to the Eq. (1) of the channel potential VP in bulk MOS, this potential is controlled by the substrate (node B, Fig. 3) through the factor g0 ; which is the bias and the geometry dependent body effect factor and the front gate VG through V 0G : 8 0sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 0 2 > 0 > y y > 0 < V G 2 PHI 2 g0 @ V 0G þ 2 A for V 0G . 0 2 2 VP ¼ > > > : 2PHI for V 0G , 0 ð1Þ being: pffiffiffiffiffi V 0G ¼ VG 2 VTO 2 DVRSCE þ PHI þ GAMMAa PHI
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The relation between VP and the bulk potential VB is non-linear. In FD SOI this potential is controlled by the back gate and the front gate. Therefore, it makes sense to use the node B for the back gate. In FD SOI, the relation VB and VP is linear, and the SPICE parameters GAMMA and PHI lose their physical meaning and become simple fitting parameters for the function VP : In this model there is no space for parasitic mechanisms typical for SOI devices, such as the self-heating and the kink effect. Therefore to perform a fault simulation without considering those phenomena can lead to wrong conclusions. 4.2. Fault simulation model for FD SOI In order to allow for the evaluation of the kink effect in FD SOI devices without employing complex equations to just electrically simulate the physical phenomena, the fsm shown in Fig. 4 has been developed. The consequence of the impact ionisation is a current of holes flowing between the drain and the body (Fig. 2). To simulate the diode between the drain and the forward biased body, a bulk PMOS device (M3) is inserted on the drain of the SOI NMOS device. To realistically describe the area where the diode is created, this NMOS device for which the kink effect is considered is split into two devices M1 and M2. Those two devices having the same input and being in series represent the original NMOS SOI device with a channel length (L) equal to the sum of the channel lengths of M1 and M2. In this way the diode can be positioned in the middle if the body position or the carriers accumulated should be exactly between the source and the drain. By assigning a different L to M1 and M2 the position can be moved e.g. closer to the drain. The voltage source V8 (Vdc ¼ 0) is just used to separate the current contributions of the devices. The output current is measured at the drain of
Fig. 4. Kink effect fault simulation model.
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Fig. 7. DC transfer function in the presence of a drain-source short on M13 and the fault-free transfer function.
5. Impact of the modelling of the parasitic effect during the fault simulation
Fig. 5. (a) Simulated Id-Vds characteristic of a SOI nMOS transistor with kink-effect above 1.5 V using the chosen electrical model. (b) Simulated output conductance for the above SOI nMOS versus VDS.
transistor M1 as indicated by the small probe in Fig. 4. The PMOS M3 is a bulk device and the fourth terminal is the body terminal. The diode is created between the source (pþ) and the bulk (n) when the drain voltage of the device M1 is high enough to switch on the junction. The simulated output characteristics of the SOI NMOS including the kink model are shown in Fig. 5(a). In Fig. 5(b) the derivative of the current, i.e. the output transconductance is shown. Both plots are in a good agreement with the measured curves shown in Fig. 1(a) and (b).
Fig. 6. Op-amp output stage and fault simulation models for short and Kink effect (pMOS and voltage source).
This paragraph shows the impact of the parasitic effect during the fault simulation. Fig. 6 depicts an example of an output stage of a SOI operational amplifier [10]. The NMOS transistors (M12) are cascoded in order to avoid the kink effect occurrence for VDS beyond 1.5 V. It has been proven that the normal variation of the technological parameters does not impact the supply current and also not significantly the output voltage. The impact of the parasitic kink effect has been investigated assuming that it occurs due to a defect in the circuit. As fault assumptions the defect and layout oriented L2RFM [11] scheme was applied for the subsequent investigations. Besides the focus on the layout-realistic fault assumption the technology specific defect conditions, i.e. those of the SOI technology have to be investigated. In general, SOI appears to be less sensitive to defects than bulk MOS due to the dielectric isolation of the devices. On the other side, however, due to the structure of the abovedescribed SOI technology, specific defects and failure mechanisms have to be assumed and modelled in a respective defect-oriented manner by respective fsm. As mentioned before, a special fsm-model for the kink effect was used. To create the undesired path for the holes current from drain to source, a pMOS transistor was used. This transistor is operated as a diode by which the respective holes current M12 can be simulated, when a short on
Fig. 8. Supply currents for the two simulated situations with and without drain-source short.
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Fig. 9. Supply current Iccq in the presence of the Kink effect due to local imperfection of the thin film layer affecting M12.
the transistor M13 is induced. The simplified model is depicted in Fig. 6 for the kink effect simulation on transistor M12. In the first simulation a drain-source short on M13 was assumed without considering the kink effect. Here as fsm for the short fault a simple resistor of 10 mV was used connected between drain and source of M13 in order to model this drainsource short. For the sake of comparison also a simulation with a resistor value of 10 GV was performed, to implement the faultfree case with no short or high ohmic short. Both the DC output transfer function (Fig. 7) and the supply current Iccq (Fig. 8) have been plotted. As it can be seen in both plots, the drain-source short can only bedetectedifthe evaluation isdone at theright DC input voltage, which is in this case 1.1 V. This however, is not a feasible condition due to the presence of parameters variation. Also the resistance of the actual short fault impacts the detectability. In SOI however, the short alone in this cascode configuration is not present, but accompanied by the kink-effect on the transistor M12. Due to this normal parasitic effect the detectability is improved as described in the last simulation. In this last simulation the supply current Iccq condition is shown in the presence of the kink effect using the above described fsm for the kink effect. Again the DC transfer function was simulated and it turned out to be the same as the one shown in Fig. 7. As already shown in this figure it was not possible to detect this defect in the voltage of the output signal of the operational amplifier. In the supply current Iccq ; however, a significant deviation can be identified. Thus, a clear detection of the defect over a wide input voltage range is possible. The detection due to the kink effect ranges between 0 and 1.1 V. In the fault-free case the supply current decreases from about 425– 350 mA at 1.1 V. Due to the kink effect, however, the decrease starts at 750 mA and linearly reaches 690 mA at 1.1 V (Fig. 9). Note, that from about 1.3– 2.0 V no detection of this effect is visible in the Iccq as the current enters the same range as in case of the fault-free circuit. 6. Conclusion The paper deals with the modelling of one of the main parasitic effects which affecting SOI devices: the kink
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effects. It is explained that FD SOI n-channel transistors is normally free of this effect. However, if the negative back-gate bias is used, to induce an accumulation layer at the back interface the device behaves as a PD device, and the kink appears. The device models used in standard circuit simulators do not always take into account such phenomena. In order to insert those parasitic effects in the course of fault simulations a simple electrical model, referred to as fsm of the kink effects has been presented. This model comprises of a single additional pMOS transistor where the body current is controlled by the drain-source voltage of the transistor affected by the impact ionisation. Results from fault simulations employing the kink effect fsm have been shown and discussed. From those simulations is demonstrated, that specific defects in the cascode of circuits can render a circuit into the kink effect region. Due to this effect the detectability of the respective defects is enhanced. Without such a model of the kink effect however, those defects appear as invisible in the simulation, thought in reality they become visible in the supply current. In consequence the fault coverage as resulting from a fault simulation without modelling the kink effect is not comprehensive, i.e. too low. Due to the simplicity of the fsm the additional cost of simulation time is negligible.
References [1] D. De Venuto, M. Kayal, M.J. Ohletz, Fault detection in CMOS/SOI mixed-signal circuit using the quiescent current test, Microelectronic Journal 33/5–6 (2002) 387–397. Elsevier Science. [2] M.J. Ohletz, Fault modelling and simulation for the test of integrated analog and mixed-signal circuits, in: A.S. Gerson, Machado (Eds.), Low-Power HF Microelectronics—a unified approach, Eighth ed., 1996, pp. 475–510, Chapter 13. [3] M.J. Ohletz, Hybrid Built-In Self-Test (HBIST) for mixed analogue/ digital integrated circuits, Proceedings of Second European Test Conference April 10–12 (1991) 307–316. [4] M. Bucher, C. Enz, C. Lallement, Accurate MOS modelling for EKV MOST Model, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS’96), Trento, Italy 9 (1996) 145–150. [5] J.P. Colinge, Silicon-On-Insulator Technology: Materials to VLSI, Second ed., Kluwer Academic Publishers, Dordrecht, 1997. [6] J.B. Kuo, S.C. Lin, Low-Voltage SOI CMOS VLSI Devices and Circuits, Wiley, New York, 2001. [7] M.J. Ohletz, Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits, Proceedings of ITC (1996) 776–785. [8] J.-L. Pelloie, A. Auberton-Herve´, Low-power, high-performance SOI CMOS, Solid State Technol. 44 (11) (2001) 63 –68. [9] www.soi.tec.ufl.edu [10] D. De Venuto, Int. Rep. EUREKA proj. HERO, EPFL-Lausanne, 2000 [11] M.B. Santos, F.M. Gonc¸alves, M.J. Ohletz, J.P. Texeira, et al., Defected oriented testing of analogue and mixed-signal ICs, Proceedings of fifth International Conference On Electronic Circuits and Systems (ICECS) 2 (1998) 419–424.