Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC)

Microelectronics Journal 44 (2013) 1336–1347

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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC) Sounak Roy a,n, Hiranmoy Basak a, Swapna Banerjee a a

Department of Electronics and Electrical Communication Engineering, IIT Kharagpur, India

art ic l e i nf o

a b s t r a c t

Article history: Received 3 April 2013 Received in revised form 4 September 2013 Accepted 19 September 2013 Available online 4 November 2013

A foreground calibration technique of a pipeline analog-to-digital converter (ADC) has been presented in this paper. This work puts an emphasis on erroneous ADC output occurring due to device mismatch, which, in any standard CMOS process boils down to capacitor mismatch. Deviation of gain of a multiplying digital-to-analog converter (MDAC), also known as the radix of a pipeline ADC stage, from its ideal values adds to the non-linearity of the ADC output. Capacitor mismatch is a major contributor for such an error. The proposed foreground calibration technique makes use of a simple arithmetic unit to extract the radix value from the ADC output for calibration. It uses a sinusoidal signal at the input for calibration purposes. The input sinusoidal signal can be sampled by the ADC clock at any rate for the calibration algorithm to be successful. Behavioral simulation of a pipeline ADC with 5% capacitor mismatch supports the established technique. To verify the calibration algorithm further, pipeline ADCs of different resolutions have been designed and simulated in a 0.18 μm CMOS process. & 2013 Elsevier Ltd. All rights reserved.

Keywords: Pipeline ADC Foreground calibration Flip-around MDAC Non-flip-around MDAC Radix extraction

1. Introduction Analog-to-Digital Converters (ADCs) are integral parts of modern day digital electronics, be it for day-to-day commercial application or for high end electronics warfare. Among many ADC topologies found in the literature, pipeline ADCs are the most popular architecture when it comes to moderately high resolution and sampling speed. Pipeline ADCs contain identical stages connected in cascade to resolve the input signal one stage after the other. Each identical stage contains one sub-ADC which resolves the input signal into smaller resolutions and one Multiplying Digital-to-Analog Converter (MDAC) which amplifies the resulting residue signal. Sub-ADCs are a combination of comparators whereas MDACs are popularly implemented using switched-capacitor (SC) or switched current (SI) circuits which are driven by op-amps or operational transconductance amplifiers (OTAs). Linearity of a pipeline ADC depends upon the performances of the building blocks of sub-ADC and MDAC. Comparator offsets, op amp gain, capacitor mismatch and parasitic capacitances are the factors which determine the linearity of the pipeline ADC. The concept of digital redundancy [1,2] removes the error generated due to the comparator offset. Other three factors contribute to the gain error at the ADC output and cause missing codes and non-monotonicity [3]. Several correction techniques have been developed in the recent years to counteract such gain errors,

n

Corresponding author. Tel.: þ 91 9831775244. E-mail address: [email protected] (S. Roy).

0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2013.09.004

most of them in the digital domain and a few in the analog domain. Calibrating the output of the ADC to achieve a higher linearity is one such technique. Analog calibration techniques [4] require hardware modifications and in scaled technologies these modifications do have their limitations. Digital calibrations [5–7], on the other hand, require minimal hardware change at the analog front end and calibration algorithm can be completely implemented in a digital domain which uses less die area and reduces power consumption. Digital domain calibration techniques can be sub-divided into two parts: (a) background digital calibration [5,11] and (b) foreground digital calibration [8]. In a background technique, calibration occurs on the fly, i.e., data conversion and calibration happen simultaneously. In foreground calibration, however, ADC output data are post-processed for the removal of non-linearity. In [8], a data conversion process is stalled during calibration. A special set of input signal is given to the ADC input and the corresponding ADC output is post-processed for radix extraction and calibration. In this paper, a new foreground calibration technique of a pipeline ADC has been proposed where instead of providing a special input signal to the ADC, sinusoid signals are used for calibration. A non-linear stage of a pipeline ADC is calibrated using the data retrieved from the remaining stages of the ADC, which is treated as the back end ADC (BE-ADC) output. The paper demonstrates the performance of the calibration algorithm using different resolutions of BE-ADC. Non-linearity in the pipeline ADC is originated from the random mismatch between sampling and feedback capacitors of the front end MDAC. The gain error introduced by this capacitor mismatch is approximated by very

S. Roy et al. / Microelectronics Journal 44 (2013) 1336–1347

high op-amp open loop gain. However, an estimate of the range of op-amp open loop gain has been calculated, within which the approximation becomes valid in the proposed calibration algorithm. It is an obvious fact that as resolution of the BE-ADC increases, it helps to extract the radix of the desired stage more precisely. BE-ADCs of 8-bit and 10-bit resolution are used in this paper to linearize one front end pipeline stage. Behavioral simulations and circuit simulations have been performed for both the cases and their results have been compared. Section 2 briefly describes a typical pipeline ADC functionality and calibration method. Section 3 elaborates the proposed calibration algorithm. The hardware modifications at the analog front end are also described in this section. The proposed method can be used for two types of switched capacitor (SC) MDAC circuits: fliparound MDAC and non-flip-around MDAC. System level simulation of 9-bit and 11-bit pipeline ADCs is done to verify the calibration technique for both types of switched-capacitor (SC) MDACs. Results of the behavioral simulations are detailed in Section 4. Circuit level implementation of a pipeline ADC using 0.18 μm CMOS technology along with the building blocks of the ADC is described in Section 5. Circuit simulation results and the improvements found using the calibration technique are documented in Section 6.

2. Theoretical background of pipeline ADC Before presenting the proposed calibration algorithm, it is necessary to have a review on a typical pipeline ADC. How the performance of a pipeline ADC changes with device mismatch, comparator offsets, finite op-amp gain and parasitic effects is discussed in the following sections. A pipeline ADC has been modeled to understand its functionalities. The requirement of a calibration algorithm has also been shown from the derivation of a pipeline ADC output.

2.1. Modeling the pipeline ADC Fig. 1 shows the block diagram of a typical pipeline ADC with ðN  1Þ 1.5-bit pipeline stages followed by an M-bit flash stage.

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Each of the ðN  1Þ identical stages contains a sub-ADC and an MDAC. In order to understand the behavior of each stage, transfer curves of the internal nodes of the first stage are plotted in Fig. 2 (a) and (b). Fig. 2(a) shows the transfer curve of the sub-DAC, which is a part of the MDAC. This sub-DAC converts the sub-ADC digital output into its equivalent analog values. Considering the signals to be differential in nature, Fig. 2(a) shows before subtraction operation, V DAC ¼

V REF V REF  DO ð1Þ  L1 L1

ð1Þ

where the decimal equivalents of the sub-ADC output DO ð1Þ are 0, 1 and 2. For a 1.5-bit stage, although the effective resolution is 1-bit, two binary digits are produced from each stage as two comparators reside in the sub-ADC. Hence, the number of quantization levels is L1 ¼ 4. The term V REF =L1 signifies the minimum resolvable voltage of the 1.5-bit stage. After the subtraction, the residue can be written as V DAC ¼ V IN  V DAC ¼ V IN 

 V REF
 DO ð1Þ 1 L1

ð2Þ

Since for the first stage, V IN ¼ V 1 , the stage transfer function is formulated as    V REF
V 2 ¼ G1 V 1  DO ð1Þ  1 ð3Þ L1 where G1 is the gain of the first MDAC stage. So, transfer characteristics of the jth stage can be generalized to V j þ 1 ¼ Gj ½V j  ðV REF =4ÞfDO ðjÞ  1g as L1 ¼ Lj ¼ L ¼ 4. Eq. (3) can be re-arranged to express V1 in terms of V2 and consequently Vj and VN in terms of V j þ 1 and V N þ 1 as   V j þ 1 V REF
V 2 V REF
DO ð1Þ  1 V j ¼ DO ðjÞ  1 þ þ G1 4 Gj 4  V N þ 1 V REF
 V N þ 1 V REF
þ DO ðNÞ  1 ¼ M þ M DO ðNÞ  1 VN ¼ GN GN 2 2 V1 ¼

ð4Þ

The effective gain of the Nth stage (the flash stage) is GN ¼ 2M . It is worth mentioning here that the amplified residue, V N þ 1 , of the last stage needs not to be generated in a pipeline ADC implementation but theoretically this term helps to form the quantization noise of the entire ADC [1]. With the iterative usage of Vj in terms

Fig. 1. Circuit diagram of an ðN þ M  1Þ bit pipeline ADC.

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Fig. 2. Transfer curves of the first stage. (a) Transfer curves of the first stage sub-DAC, (b) transfer curve of the first stage after residue amplification.

amplified residue as  G1  Q N;1 and the sub-ADC provides the digital output DO ð1Þ. 1 N1 Since DOUT ¼ 2M  2 ∑N i ¼ 1 ∏j ¼ i Gj DO ðiÞ þ DO ðNÞ, a combination of the digital outputs of the individual stages are done using a linear combination of an estimated radix rai. For an ideal ADC, Gi ¼ rai ¼ 2 for 1.5-bit pipeline stage. Hence, rai;BE of the BE-ADC is considered to be ideal (rai;BE ¼ Gi;BE ¼ 2). However, the first stage of the pipeline ADC will have a gain G1 a ra1 ¼ 2 due to nonideal device behaviors. Hence, digital output of the ADC can be re-written as, N1 N1

DOUT ¼ 2M  2 ∑ ∏ raj DO ðiÞ þ DO ðNÞ

Fig. 3. Simplified block diagram of pipeline ADC.

i¼1 j¼i

VNþ1 V REF V1 ¼ þ G1 G2 …GN G1 G2 …GN   DO ð1Þ DO ð2Þ þ G2 …GN þ ⋯ þDO ðNÞ  G1 G2 …GN 4 4 V REF V REF V REF   ⋯ G1 G2 …GN 4G1 G2 …GN  1 4 ( ) N 1 N 1 VNþ1 V REF 1 ) V1 ¼ M þ M N1 2M  2 ∑ ∏ Gj DO ðiÞ þDO ðNÞ 2 ∏jN¼11 Gj 2 ∏j ¼ 1 Gj i¼1 j¼i V REF

1

1 2M ∏N j ¼ 1 Gj

(

N1 N1

2M  2 ∑ ∏ Gj þ1 i¼1 j¼i

N 1 N 1

j¼1

i¼2 j¼i

¼ 2M  2 ∏ raj DO ð1Þ þ 2M  2 ∑ ∏ raj DO ðiÞ þ DO ðNÞ

of V j þ 1 provides the following:



N 1

) ¼ Q N þ LSB:DOUT þ α

ð5Þ

where QN is the quantization error of the entire ADC, 1 LSB ¼ V REF =2M ∏N j ¼ 1 Gj , DOUT is the effective digital output of the ADC and α is the offset term. Since the stages enforce digital redundancy, this offset term is neglected in future calculations.

N 1

¼ 2M  2 ra1 ∏ raj DO ð1Þ þ DBE ¼ 2M þ N  4 ra1 DO ð1Þ þ DBE

ð6Þ

j¼2

In practical circuits, the gain G1 of the first stage will be either G1 42 or G1 o 2. In such cases, the MDAC output of the first stage will differ from its ideal curve and which will, in turn, affect the transfer characteristics of the ADC. Fig. 4(a) shows the MDAC curve for two cases of MDAC gain and Fig. 4(b) shows the resulting transfer curves of the ADC. Non-linearities of the ADC are represented by the missing codes and non-monotonicity in Fig. 4(b). A key objective of a foreground calibration technique is to determine the actual gain of the targeted stage. Radix ra1 must be extracted [8,11] using the calibration procedure so that ra1 ¼ G1 . This corrected ra1 is then used in Eq. (6) to form the calibrated ADC output. The dashed lines in Fig. 4(b) show the transfer curves of the ADC after calibration.

3. Proposed calibration algorithm 2.2. Calibration of a pipeline ADC In any pipeline ADC, precision of the first few stages is of importance in order to achieve the targeted resolution of the whole ADC. Since the finite op amp gain, capacitor mismatch and parasitic capacitance of the first stage contribute to the nonlinearity of the entire ADC. Remaining stages act as a back end ADC (BE-ADC) which can resolve the first stage residue with high linearity. Fig. 3 shows a simplified pipeline ADC block diagram with the first stage being under calibration and N  1 stages forming the BE-ADC. The first stage of the ADC produces the

This paper focuses on a foreground calibration technique by the determination of radix value. Instead of using the final ADC digital output DOUT, the proposed calibration algorithm uses the BE-ADC output DBE for digital post-processing and radix extraction. To determine the correct value of G1, which is a function of capacitor ratio, op-amp gain and parasitic capacitance, a very high first stage op-amp open loop gain (Aopenloop -1) has been assumed, although it is shown later that an op amp gain of 63 dB is sufficient to establish the proposed calibration algorithm for an 11-bit ADC. In pipeline ADCs, the MDAC part generally uses switched-capacitor

S. Roy et al. / Microelectronics Journal 44 (2013) 1336–1347

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Fig. 4. Transfer curves of the first stage. (a) Transfer curve of the first stage residue with two different gain factors, (b) transfer curves of the ADC with non-ideal gain factors.

Fig. 5. Proposed calibration algorithm. (a) Stage 1 of the pipeline ADC under calibration, (b) implementation of the calibration algorithm for radix extraction.

(SC) circuits for implementation. Two types of SC MDAC topologies are used for all practical purposes, viz., capacitor flip-around topology and capacitor non-flip-around topology. Viability of the proposed calibration technique for both these topologies has been discussed in Sections 3.1 and 3.2. Primary objective of the proposed calibration algorithm is to extract the value of G1 from the BE-ADC output, DBE. Gain of the MDAC of the first stage, G1, can be linearly related to the ratio of two capacitors, C1 and C2, i.e., G1 p ðC 1 =C 2 Þ. As shown in Fig. 5(a), the ADC under calibration has a non-linear first stage whose nonlinearity is manifested by the non-ideal value of ðC 1 =C 2 Þ, say, k which differs from its ideal value of 1 or 2. During ϕ1 and ϕ2, values of the MDAC gain are Gðϕ1 Þ ¼ ðC 1 =C 2 Þ and Gðϕ2 Þ ¼ ðC 2 =C 1 Þ respectively. Since DBE ¼  Q N;1 Gðϕi Þ þ Q N:BE , MDAC gain will produce G′1 ð ¼ C 1 =C 2 Þ and G″1 ð ¼ C 2 =C 1 Þ during ϕ1 and ϕ2 respectively. So, it can be written as follows: DBE ðϕ1 Þ  Q N;1 G′1 þ Q N;BE ¼ DBE ðϕ2 Þ  Q N;1 G″1 þ Q N;BE

ð7Þ

Now, if it can be shown that Q N;BE {Q N;1 , (7) will simplify to the following:  2 DBE ðϕ1 Þ G′1 C1 ¼ ″¼ ¼ G21 C2 DBE ðϕ2 Þ G1

ð8Þ

So, by swapping the capacitors C1 and C2 two different values of MDAC gains (radix values) are acquired which are finally used to determine the actual radix of the stage (see Fig. 5(b)). For the proposed calibration algorithm to be working, the condition Q N;BE {Q N;1 must be justified. After capturing the BEADC data, DBE is used for post-processing and determination of the desired radix, G1. A large sample (NS) of the BE-ADC output is taken and its standard deviation ðsBE Þ is calculated. Since the BEADC is discrete in nature, DBE ½n ¼  Q N;1 ½nG1 þ Q N;BE ½n where n is the time index. So, the following equations hold: s2BE ¼

1 NS 2 2 ∑ D  D BE N S n ¼ 1 BE

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Fig. 6. Quantization error voltages for different BE ADCs.

Fig. 7. Two types of MDAC topology. (a) MDAC of the first stage showing flip-around topology, (b) MDAC of the first stage showing non-flip-around topology.

8 !2 9 NS <∑NS Q 2 = ∑ Q N;1 N;1 n¼1 n¼1 ¼ G21  : ; NS NS ( ) S S ∑N ∑NS Q N;1 ∑N n ¼ 1 Q N;1 Q N;BE n ¼ 1 Q N;BE  n¼1  2G1 NS NS NS 8 9 ! 2= <∑NS Q 2 S ∑N n ¼ 1 N;BE n ¼ 1 Q N;BE  þ : ; NS NS ¼ G21 s2Q N;1  2G1 covðQ N;1 ; Q N;BE Þ þ s2Q N;BE

9-bit BE-ADC, where N S ¼ 8192, values of s2Q N;1 , covðQ N;1 ; Q N;BE Þ and s2Q N;BE are found to be 0.0233, 1:523  10  5 and 3:974  10  7 respectively. These values validate the assumptions G21 s2Q N;1 c covðQ N;1 ; Q N;BE Þ and G21 s2Q N;1 c s2Q N;BE which simplifies Eq. (9) to s2BE  G21 s2Q N;1 . Thus sBE ðϕ1 Þ G1 ðϕ1 Þ ¼ sBE ðϕ2 Þ G1 ðϕ2 Þ ð9Þ

Since variance of the quantization error of an ADC is related to its LSB (Least Significant Bit) as s2qn ¼ LSB2 =12, quantization error of the 1.5-bit first stage and N  1-bit BE-ADC can be related as follows: s2Q N;1 s2Q N;BE

¼

LSB21 LSB2BE

¼ 22ðN  2Þ

ð10Þ

Clearly, as the resolution of the BE-ADC increases, s2N;BE {s2N;1 . Next, the covariance term of Eq. (9) will also show that compared to the first term of the equation G21 s2N;1 , covðQ N;1 ; Q N;BE Þ represents a very negligible value. To establish this, BE-ADCs with resolutions varying from 5-bit to 9-bit were simulated in MATLAB to determine their covariances. With BE-ADC resolutions, 5-bit, 6-bit, 7-bit and 9-bit, covariances are 1:093  10  3 , 3:887  10  4 , 1:3525  10  4 and 1:523  10  5 respectively. Elaborating this fact with a

ð11Þ

Fig. 6 shows the quantization error voltages of different BEADCs. It shows that with the increasing resolution of BE-ADCs, amplitude of their quantization noise decreases. 3.1. Calibration algorithm using flip-around MDAC Fig. 7(a) shows a typical flip-around MDAC circuit with all the non-linearities. Equating the charge stored in the capacitors during φ1 and φ2 w.r.t. the summing node X the following equation will represent the actual transfer characteristics of the first stage. 9 9 8 > > > > > > = = < C 1 þC 2 C1 V REF V1  D ð1Þ: V2 ¼ 1 1 > > O > > 2 > > ; ; :C 2 þ :C 2 þ ðC 1 þ C 2 þ C P Þ> ðC 1 þ C 2 þ C P Þ> AOL AOL 8 > > <

ð12Þ

S. Roy et al. / Microelectronics Journal 44 (2013) 1336–1347

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Fig. 9. Determination of radices of multiple stages: hierarchical calibration.

assumption that the second stage of the pipeline ADC is ideal, pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi C 12 ¼ C 12 and G1;mod reduces to 2ðC 1 =C 2 Þ ¼ 2 sBE ðϕ1 Þ=sBE ðϕ2 Þ. 3.2. Calibration algorithm using non-flip-around MDAC

Fig. 8. Scaling and modification of the flip-around MDAC for radix extraction.

High open loop gain of the op-amp simplifies Eq. (12) to the following: V2 ¼

C1 þ C2 C1 V 1  :DO ð1Þ:V REF C2 C2

ð13Þ

where DO ð1Þ : f  1; 0; 1g. For ideal behavior, C 1 ¼ C 2 . But in practical circuits designed using a CMOS process, they are related by C 1 ¼ C 2 ð1 þ γ Þ, where γ is the mismatch factor. It is interesting to note that flip-around topology poses one problem in determining the proper radix of the stage as the coefficients of V1 and VREF are different, i.e., radix of this stage will not be ðC 1 þ C 2 Þ=C 2 , but to have a uniform coefficient, proper scaling would be required. Fig. 8 shows the scaling of the input signal V1 and the reference voltage VREF according to [8]. This modifies the MDAC gain and the transfer characteristics of the first stage. Newly formed areas follows: C1 þ C2 C2 ′ V1 ¼ V1 C1 2 C2

ð14Þ

C 12 þ C 22   C 1 C 22 V REF V ′1 DO ð1Þ V2 ¼ 2 C 12 C2 4 2 C 22

ð15Þ

G1;mod ¼

C1 C2

C 12 þ C 22 C 22 C 12 C 22

ð16Þ

where C 1 and C 2 are capacitors of the first stage, C 12 and C 22 are capacitors of the second stage and G1;mod is the modified radix of the first stage MDAC which now can be used for the purpose of calibration. It can be shown that after swapping the capacitors C1 and C2,  2 G1;mod ðϕ1 Þ C1 sBE ðϕ1 Þ ¼ ð17Þ ¼ C2 G1;mod ðϕ2 Þ sBE ðϕ2 Þ where during ϕ1 ADC provides the output with normal C1 and C2 connections and during ϕ2, C1 and C2 are swapped. With the

Fig. 7(b) represents a non-flip-around MDAC topology. In this topology, capacitor C1 is often termed as the sampling capacitor and C2 as a feedback capacitor. These two capacitors are related by C 1 ¼ 2ð1 þ γ ÞC 2 , where γ is the mismatch factor. As before, the transfer characteristics of the first stage MDAC can be formulated using the concept of conservation of charges in two phases, φ1 and φ2:   C1 V REF ð18Þ V 1 DO ð1Þ V2 ¼ 1 4 C2 þ ðC 1 þ C 2 þ C P Þ AOL Noticeably, uniform coefficients of V1 and VREF in the transfer characteristic give this topology an edge over the flip-around one in terms of radix extraction. With AOL -1, radix of the first stage becomes G1 ¼ C 1 =C 2 . Collecting the BE-ADC data in two phases ϕ1 and ϕ2 will give the following:  2 G1 ðϕ1 Þ C1 sBE ðϕ1 Þ ¼ ¼ G21 ¼ ð19Þ C2 G1 ðϕ2 Þ sBE ðϕ2 Þ where ϕ1 and ϕ2 stand for normal capacitor connection and swapped capacitor connection respectively. 3.3. Hierarchical calibration: linearization of multiple stages Fig. 9 shows an example of hierarchical solution for determining the radices of two non-linear pipeline stages. When the signal ctrl ¼0, stage 1 is bypassed and input signal gets converted by stage 2 and the BE-ADC. The BE-ADC output DBE is used for digital post-processing involving its standard deviation. Once radix ra2 is determined, combined stage 2 and the BE-ADC are used as the BEADC of stage 1. While extracting ra1, the value of ra2 is used for linearization of stage 1. Finally, the digital output of the ADC is DOUT ¼ 2NB fra1 ra2 DO ð1Þ þ ra2 DO ð2Þg þ DBE .

4. Behavioral simulation results using MATLAB The calibration algorithm has been verified by pipeline ADCs with 8-bit and 10-bit BE-ADC. The objective of the simulation is to calibrate the first stage of the pipeline ADC. So, non-idealities are introduced while developing the design equations of the first stage. Input voltage dynamic range is  0:5 V r V IN r þ 0:5 V, i.e., V REF ¼ 1 V. Capacitor mismatch is introduced in the first stage with C 1 ¼ 100fF and C 2 ¼ 100fF þ ΔC with ΔC ¼ 5fF while using an MDAC with flip-around topology, whereas for non-flip around

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20 INL (LSB)

SNDR (dB)

0 SFDR = 38.75 dB

−50 −100 0

5

10

15

20

−20

25

0

100

200

Frequency (MHz)

(i)

300

400

500 Codes

(i) 0 INL (LSB)

0 SNDR (dB)

0

−50 SFDR = 72.69 dB −100 0

5

10

15 (ii)

20

25

Frequency (MHz)

−1

−2

0

100

200

300

400

(ii)

500 Codes

Fig. 10. Calibration of a 9-bit pipeline ADC with flip-around MDAC. (a) FFT plot of a 9-bit pipeline ADC with flip-around MDAC: (i) before and (ii) after calibration, (b) INL improvement: (i) before and (ii) after calibration.

Fig. 11. Dynamic response of pipeline ADCs with non-flip-around MDAC. (a) FFT plot of 9-bit pipeline ADC: (i) before and (ii) after calibration, (b) FFT plot of 11-bit pipeline ADC: (i) before and (ii) after calibration.

topology, C 1 ¼ 2  C and C 2 ¼ C  ð1 þ ΔCÞ where ΔC ¼ 0:05 are used. Op-amp gain of the first stage is 80 dB. Dynamic and static analyses are done with sinusoid signals. For both the analyses, N S ¼ 8192 samples are collected. In dynamic analysis, frequency domain transformation is done using Discrete-Fourier-Transform (DFT) of the ADC output. Calculations involving signal power and noise power, such as Signal-to-Noise-and-Distortion-Ratio (SNDR), Spurious-Free-Dynamic-Range (SFDR) and consequently EffectiveNumber-of-Bits (ENOB) are determined from the DFT plots. Using 8192 samples of data, a histogram plot provides an estimate of the code transitions [16]. From these data, differential non-linearity (DNL) and consequently integral non-linearity (INL) can be determined.

INL improves from 0:28LSB r INL r  11:71LSB to 0LSB r INL r  1:57LSB. The offset of the input voltage is manifested by the assymetric INL plots in Fig. 10(b).

4.1. Simulation results of a 9-bit pipeline ADC with flip-around MDAC

4.3. Simulation results of an 11-bit pipeline ADC with non-flip-around MDAC

A 9-bit pipeline ADC has been designed with a non-linear first stage in order to calibrate its first stage. The BE-ADC resolves 8bits. Design equations of a flip-around MDAC are considered which offset the input voltage as suggested in Fig. 8. SFDR values of the ADC before and after calibration are 38.75 dB and 72.69 dB (see Fig. 10(a)) respectively. Calibration improves the SNDR from 36.95 dB to 55.72 dB. The static characteristics improvement is captured using the Integral-Non-Linearity (INL) plot in Fig. 10(b).

The resolution of the BE-ADC is increased by augmenting two more 1.5-bit stages. As expected, the calibration algorithm provides more precise radix when the BE-ADC resolves more accurately. Dynamic analyses of both ADCs are plotted in Fig. 11(a) and (b). Improvements found in the INL plots are shown in Fig. 12(a) and (b). A comparison of different dynamic and static characteristics is tabulated in Table 1.

4.2. Simulation results of a 9-bit pipeline ADC with non-flip-around MDAC A similar behavioral simulation of a 9-bit pipeline ADC with non-flip-around MDAC has been performed. Apart from the nonlinear first stage, its 8-bit BE-ADC comprises six 1.5-bit stages followed by a 2-bit flash stage.

S. Roy et al. / Microelectronics Journal 44 (2013) 1336–1347

20 INL (LSB)

INL (LSB)

5

0

−5

0

100

200

300

400

−20

500

0

500

1000

1500

2000 Codes

(i)

1

2 INL (LSB)

INL (LSB)

0

Codes

(i)

0

−1

1343

0

100

200

300

400

500 Codes

(ii)

0

−2

0

500

1000 (ii)

1500

2000 Codes

Fig. 12. Static response of pipeline ADCs with non-flip-around MDAC. (a) INL plot of 9-bit pipeline ADC: (i) before and (ii) after calibration, (b) INL plot of 11-bit pipeline ADC: (i) before and (ii) after calibration.

Table 1 ADC linearity with low and high resolution BE-ADC. Resolution of the ADC

SFDR (dB)

SNDR (dB)

ENOB (bits)

ðNÞ

BC

BC

BC

9-bit 11-bit

42.53 76.3 40.14 55.12 6.37 8.93 74.74 7 0.65 42.46 85.45 40.23 67.44 6.76 10.91 719.57 7 1.1

AC

AC

INL (LSB)

AC

BC

AC

BC: before calibration, AC: after calibration.

4.4. Linearity of the ADC with gain and capacitor mismatch The calibration algorithm presented in this paper stands on the assumption that the op-amp gain of the stage that is to be calibrated must be very high ðAOL -1Þ. But this gain cannot be arbitrarily high which might make this calibration algorithm impractical. So, a series of simulations have been done with parasitic capacitance C P ¼ 10fF, a capacitor mismatch factor 0:05 r γ r 0:05 and op-amp gain 54 dB rAOL r 72 dB. The pipeline ADC that is designed has the non-linear first stage followed by a 10-bit BE-ADC. In each of the simulations, the non-linear first stage is linearized using the calibration method and the SNDR found before (see Fig. 13(a)) and after (see Fig. 13(b)) calibration is documented. It is found from Fig. 13(b) that with AOL Z63 dB, the ADC achieves its desired 11-bit linearity. The plots in Fig. 13 also satisfy the fact that for any quantity of capacitor mismatch within  0:05 r γ r 0:05, the pipeline ADC recovers its desired linearity after the application of the calibration algorithm. In any modern day CMOS process, designing and implementing an op-amp with a dc gain of 63-dB do not pose any serious challenge.

5. Circuit implementation using a 0.18 μm CMOS process To verify the theory so far established and to further support the behavioral simulation results of Section 4, a pipeline ADC with BE-ADC resolutions of 8-bit and 10-bit has been designed and simulated in a 0.18 μm CMOS process. The ADC contains a nonlinear 1.5-bit first stage followed by BE-ADC. As established in 4.1 and 4.2, both the switched-capacitor topologies of MDAC can be used for the calibration purposes. Both these topologies have their advantages and disadvantages. A flip-around MDAC topology has a higher feedback-factor ðβ ¼ 1=2Þ and hence, it can work faster than

the non-flip-around MDAC, which has a feedback factor of β ¼ 1=3. However, as shown in Fig. 7(a) and (b), a non-flip-around MDAC uses a single reference voltage 7 V REF =4 for the entire first stage, unlike the flip-around topology, where 7 V REF =4 and 7 V REF =2 are required. This helps to implement a reference ladder circuit with lower power consumption and lower reference noise. Designing a flip-around MDAC-based ADC has been treated as a future work and the implementation presented in this paper consists of a first stage MDAC with non-flip-around topology. Fig. 14 shows the schematic of the pipeline ADC. Details of the first stage MDAC are shown in Fig. 15(a) and the corresponding waveforms are shown in Fig. 15(b). During phase ϕ1a ¼ 1, the switches are so connected that C1 is treated as the sampling capacitor and C2 is connected as the feedback capacitor. In this phase, non-overlapping clocks φ1 and φ2 are used as the sampling clock phase and the amplifying clock phase respectively. The clock φ1e has been used for bottom plate sampling in order to reduce errors due to charge injection. For a non-flip-around MDAC, ideally, C 1 ¼ 2C 2 . But to show the effectiveness of the calibration algorithm, C1 and 2C2 are deliberately made unequal while implementing the first stage MDAC. Since sampling capacitor size is determined from the thermal noise calculations, with V R ¼ 1 2 V P  P , and a resolution of 11-bit, the relationship Δ =12 ZkT=C 1 must hold. In a standard 0.18 μm CMOS process random capacitor mismatch can vary from 0.1% to 5% [13]. These conditions lead to C 1 ¼ 400 fF and C2 has been deliberately sized at 208 fF instead of 200 fF which caters to a mismatch percentage of  5%. The capacitor sizing is done to meet the condition of an 11-bit ADC, so that it satisfies the needs of a 9-bit ADC easily. In practical ICs, the device mismatch that occurs cannot be modeled in the simulation environment. Hence, C2 was deviated from its required value so that a practical mismatch scenario can be emulated. During phase ϕ1a ¼ 1, first stage MDAC gain p C 1 =C 2 . During phase ϕ1b ¼ 1, capacitors C1 and C2 interchange their roles and C2 becomes the sampling capacitor, C1 being the feedback capacitor. Due to this, the MDAC gain in phase ϕ1b becomes p C 2 =C 1 . For calibration, N samples are captured when ϕ1a is “high”, i.e., BEADC samples from 0 to ðN  1ÞT S are captured (see Fig. 15(b)), where T S ¼ 1=f S , fS being the sampling frequency of 50 MHz. Likewise, samples from NTS to 2ðN  1ÞT S provide the BE-ADC output when ϕ1b is “high”. Standard deviation of these two sets of N samples is performed and square root of their ratio determines the actual radix of the first stage which is equal to the MDAC gain of the first stage,  C 1 =C 2 . To design the first stage an op-amp of high dc gain was implemented and the sub-ADC contained

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0.05

0.03

Capacitor Mismatch (γ)

Capacitor Mismatch (γ)

0.05

0.01 −0.01 −0.03 −0.05 4000 3000 2000 1000 Op−amp Gain (V/V)

0 30

35

40

45

50

55

60

65

70

0.03 0.01 −0.01 −0.03 65 −0.05 4000

63 61

3000

59

2000

57

1000 SNDR (dB)

Op−amp Gain (V/V)

0 55

SNDR (dB)

Fig. 13. SNDR variation w.r.t. capacitor mismatch and op-amp gain. (a) SNDR variation before calibration, (b) SNDR variation after calibration.

Fig. 14. Schematic of the pipeline ADC.

Fig. 15. Proposed calibration algorithm. (a) MDAC circuit implementation of the first stage, (b) waveforms associated with the MDAC circuit.

switched capacitor-based dynamic comparators. These building blocks are briefly described in the following sections. 5.1. High gain op-amp For the first stage MDAC design, a high gain op-amp is required as suggested in (4.4). A composite cascode topology [17,18] has

been selected to design the op-amp. Fig. 16(a) shows the detailed schematic of the op-amp. The composite cascode topology as described in [18] has been applied to design the two stage opamp where each of the stages is identical. The objective of this opamp is to have a high dc gain. To achieve that high gain, composite cascode topology provided a high output resistance value, which, in turn, increased the dc gain. Looking from the drain terminal of

S. Roy et al. / Microelectronics Journal 44 (2013) 1336–1347

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Fig. 16. Building blocks of the pipeline ADC. (a) Op-amp schematic, (b) dynamic comparator schematic.

SNDR (dB)

INL (LSB)

5 0 −5 0

100

200

300

400

SNDR (dB)

INL (LSB)

0

200

5

10

300

400

20 25 Frequency (MHz)

15

20 25 Frequency (MHz)

50 SFDR = 58.11 dB

0 −50

500

0

5

10

Codes

(ii)

15 (i)

0

100

−50

500

2

0

SFDR = 42.29 dB

0

Codes

(i)

−2

50

(ii)

Fig. 17. Calibration of a 9-bit pipeline ADC with flip-around MDAC. (a) FFT plot of a 9-bit pipeline ADC with flip-around MDAC: (i) before and (ii) after calibration, (b) INL improvement: (i) before and (ii) after calibration.

50 SNDR (dB)

INL (LSB)

20

0

SFDR = 42.35 dB 0 −50

−20

0

200

400

600

800

1000

1200

1400

1600

1800 2000 Codes

5

0

0

5

10

15

20 25 Frequency (MHz)

15

20 25 Frequency (MHz)

(i)

SNDR (dB)

INL (LSB)

(i)

50 SFDR = 57.93 dB 0 −50

−5

0

200

400

600

800

1000 (ii)

1200

1400

1600

1800 2000 Codes

0

5

10 (ii)

Fig. 18. Calibration of a 9-bit pipeline ADC with flip-around MDAC. (a) FFT plot of a 9-bit pipeline ADC with flip-around MDAC: (i) before and (ii) after calibration, (b) INL improvement: (i) before and (ii) after calibration.

transistor M1, the small signal output resistance is same as that of a cascode topology, i.e., r OUT ¼ r ds1 þ r ds2 þ g m1 r ds1 r ds2  g m1 r ds1 r ds2 , where rds is the output resistances of the transistors. Assuming the

PMOS transistors to be acting as constant current source, transconductances of the first and second stages are gm2 and g m10 respectively. Hence, the overall voltage gain of the op-amp

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S. Roy et al. / Microelectronics Journal 44 (2013) 1336–1347

SNDR (dB)

INL (LSB)

20

0

−20

0

500

1000

1500

50 SFDR = 43.34 dB

0

−50

2000

0

1

2

3

4

Codes

(i)

5

6

7

8 9 10 Frequency (MHz)

6

7

8 9 10 Frequency (MHz)

(i)

SNDR (dB)

INL (LSB)

5

0

50 SFDR = 68.58 dB

0 −50

−5 0

500

1000 (ii)

1500

2000

0

1

2

3

4

Codes

5 (ii)

Fig. 19. Calibration of a 9-bit pipeline ADC with flip-around MDAC. (a) FFT plot of a 9-bit pipeline ADC with flip-around MDAC: (i) before and (ii) after calibration, (b) INL improvement: (i) before and (ii) after calibration.

becomes Adc ¼ fg m2 g m1 r ds1 r ds2 gf g m10 g m9 r ds9 r ds10 g. The op-amp uses a simple resistive divider circuit as the common-mode feedback circuit comprising RFs. In order to achieve a gain margin of more than 500, Miller compensation has been used. RC and CC form the compensation circuit. With C C ¼ 402 fF, and a load capacitance of 1 pF, the op-amp operates with a phase margin of 60.120. This fully differential op-amp, with a dynamic range of 1 V P  P and a Common Mode Rejection Ratio (CMRR) of 106.13 dB, produces an open loop voltage gain of 75.2 dB, and Unity Gain Frequency (UGF) of 1.268 GHz with a load capacitance of 400 fF. It consumes only 4.2 mW of power. 5.2. Dynamic comparator The dynamic comparator design in this pipeline ADC contains a switched capacitor comparison circuit. Followed by the comparison, the latch circuit provides the positive feedback and the buffer circuit followed by it gives the digital output of the ith stage, DO ðiÞ þ and DO ðiÞ  . The entire circuit is fully differential in nature. Instead of working in two non-overlapping clocks, it operates in two phases: in phase φ1, it samples the input signals, V i þ ; V i  and V R þ ; V R  and in phase φ1b , which is the inverted waveform of φ1, the latch decides the output DO. Using the switched capacitor, the circuit at the input enables the removal of a front end sample and hold circuit [19]. Using the charge conservation principle, the voltage at the input of the latch circuit can be found as V 1 þ ¼ fC I =ðC I þC R þ C P Þg  fV I þ þ ðC R =C I ÞV R  g. The term ðC R =C I ÞV R  actually defines the threshold of the dynamic comparator. The ratio C R =C I determines the decision threshold, according to which the latch output changes its state from “0” to “1”. In this pipeline ADC, all the 1.5-bit stages contain sub-ADCs having two dynamic comparators each. The ratio C R =C I ¼ 1=4 ensures that the transfer characteristics of the pipeline stages have the folding as depicted in Fig. 2(b). The transient simulation of the dynamic comparator shows an offset of not more than 4 mV for V I;P  P ¼ 1 V. 5.3. Digital encoder Sub-ADCs of the 1.5-bit pipeline stages provide the digital output of each stage in thermometric code. In order to transform this code to binary, a simple combinatorial block comprising only XOR gates is required. Once the binary codes from each stage are available, they are properly synched using D flip–flops and finally, summed using full adder circuits. Outputs of these full adders are

the ADC output bits which are then post-processed for calibration purposes.

6. Results and discussion As shown in Fig. 14, the first stage of designed pipeline ADC is under calibration and the rest of the stages forms the BE-ADC. Two BE-ADCs have been used to verify the calibration algorithm. The BE-ADC of 8-bit resolution is designed using six 1.5-bit pipeline stages and a 2-bit flash stage. Two more 1.5-bit stages are added in between the 1.5-bit stages and the flash stage to form the 10-bit BE-ADC. The last stages of the BE-ADCs are all similar in nature to pipeline down-scaling that do not apply to them. Minimum value of unit capacitances is held at 60 fF for these stages. In the nonlinear first stage MDAC, its sampling and feedback capacitors are purposefully deviated from their ideal values. Using the BE-ADC output data, radix of the first stage is determined and with the extracted radix value, actual ADC output is constructed. The pipeline ADC constructed has been simulated with input frequencies of 214.8 kHz and 537.1 kHz sampled at frequencies of 20 MHz and 50 MHz respectively. BE-ADCs of 8-bit and 10-bit resolutions are used for radix extraction. For all the cases, 1024 samples are captured to calculate all parameters. 6.1. Static analysis Static non-linearities are determined using a sinusoid signal input. At 537.1 kHz input signal frequency and 50 MHz sampling rate, BE-ADCs with 8-bit and 10-bit resolutions show different static characteristics and they are plotted in Fig. 17(a) and (b). INL values using 8-bit, 10-bit BE-ADCs are  5:33LSB r INL r 5:27LSB,  18:91LSB r INL r 20:91LSB, before calibration and  1:81LSB r INL r 2:06LSB,  4:76LSB rINL r 7:7LSB, after calibration, respectively. A similar simulation, using 214.8 kHz input signal frequency and sampling rate of 20 MHz, produces the static characteristic plot in Fig. 19(a). At this lower sampling rate, INL improves from  19:02LSB r INL r 19:89LSB to  5LSB r INL r 3:88LSB. 6.2. Dynamic analysis Frequency domain analyses of the ADC output are plotted in Fig. 17(b), Figs. 18(b) and 19(b). Behavior of the ADC with 8-bit and 10-bit BE-ADC is captured at two different sampling frequencies of

S. Roy et al. / Microelectronics Journal 44 (2013) 1336–1347

Table 2 ADC linearity with low and high resolution BE-ADC. Resolution of the Sampling speed ADC (MSPS)

SFDR (dB)

SNDR (dB)

ENOB (bits)

(N)

BC

BC

BC

9-bit 11-bit 11-bit

50 50 20

AC

AC

AC

42.29 58.11 40.00 48.87 6.35 7.82 42.35 57.93 39.84 48.14 6.32 7.69 43.34 68.58 41.03 64.03 6.52 10.35

BC: before calibration, AC: after calibration.

Table 3 Comparing the proposed calibration algorithm with other works. Reference N

[14] [15] [8] prop

14 13 14 14

INL

SNDR

INLafter INLbefore

Before calibration

After calibration

Before calibration

After calibration

 16 – –  100

– 62 – 39.73

– 77 80.1 82.5

– 65 E50 42.35

– 95 E90 89.34

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this calibration algorithm uses sinusoid signal at the input of the ADC which is a very widely available test signal. Unlike [8], where a special set of input signals is required at MDAC input and subADC outputs are also an independent set of signals, this work uses a sinusoid signal without any conditions set to either the MDAC or the sub-ADC. Secondly, this algorithm can work at any sampling rate of the input signal. Thirdly, in [8,10], the calibration technique demands the implementation of a convergence method to determine the final radix value but the proposed calibration algorithm requires a simple digital circuit which determines the standard deviation of the ADC output and the radix is determined from the derived value. Circuit implementation of an 11-bit pipeline ADC validates the calibration algorithm, where a BE-ADC of 10-bit linearity helps to improve the linearity of the ADC from 7-bit before calibration to 11-bit after calibration.

SFDR

N : Resolution of the ADC, prop: proposed algorithm.

50 MHz and 20 MHz. Improvement of the ADC output linearity after applying the calibration algorithm is evident from these plots. Table 2 summarizes the dynamic response of the pipeline ADC under three different conditions. An interesting observation can be made from Table 2. In circuit simulations, at a sampling rate of 50 MSPS, 9-bit and 11-bit ADCs achieve post-calibration SNDRs of 48.87 dB and 48.14 dB respectively. These values do not ensure complete recovery of the linearity of the ADC. As the behavioral simulations (see Table 1) suggest, 9-bit and 11-bit ADCs must be calibrated to a linearity equivalent to SNDR Z 61:96 dB and SNDR Z 49:92 dB respectively. Probable cause of these unexpected results is the insufficient settling of the op-amp used in the first stage. This fact is further verified when the 11-bit ADC is simulated at a sampling rate of 20 MSPS. After calibration, 11-bit, 20 MSPS pipeline ADC achieves an ENOB of 10.35 bits. Radix extracted with an 8-bit BE-ADC is ra1 ¼ 1:9076. For the 11-bit pipeline ADC, 10-bit BE-ADC helps to extract the radices, sampling at 50 MSPS and 20 MSPS, at ra1;50 M ¼ 1:9072 and ra1;20 M ¼ 1:9183 respectively. Table 3 shows a comparison chart of the proposed work with several existing calibration techniques. In this table, behavioral simulation results of different published calibration techniques are documented. For a proper comparison, behavioral simulation and calibration of a 14-bit pipeline ADC have been performed. Its design equation involves a non-linear non-flip-around MDACbased first stage as described in Section 4 and a 13-bit BE-ADC. Behavioral simulation results show improvements in terms of INL, SNDR and SFDR compared to those of the other literatures. 7. Conclusions This paper proposes a foreground calibration technique of a pipeline ADC by radix extraction with several advantages. Firstly,

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