A real-time digital calibration scheme for the cyclic ADC

Microelectronics Journal 54 (2016) 93–100

Contents lists available at ScienceDirect

Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

A real-time digital calibration scheme for the cyclic ADC Yong Zong, Jing Gao n, Zhaoyang Yin, Shilin Shen, Kaiming Nie, Wen Liu, Jiangtao Xu School of Electronic Information Engineering, Tianjin University, 92 Weijin Road, Nankai District, Tianjin 300072, China

art ic l e i nf o

a b s t r a c t

Article history: Received 30 September 2015 Received in revised form 27 April 2016 Accepted 27 April 2016

A digital calibration scheme to correct the nonlinearity caused by finite amplifier gain and capacitor mismatch for the cyclic analog-to-digital converter (ADC) is presented. The calibration block of correcting the weight of the jumping points is implemented in which adders and registers are utilized without multipliers to reduce the silicon area cost. Each calibration block is shared by five ADCs. Ten switches are added into the 1.5-bit multiplying digital-to-analog converter to choose the test input signal and set the value of the most significant bit for measuring the heights of the jumping points. The capacitor mismatch and gain errors are measured as one error, and then the weight of the jumping points is compensated in the digital domain to improve the linearity of the ADC. Designed in a 0.18 μm CMOS technology, the silicon area cost of each ADC is 0.03
1.7 mm2 and the power consumption is 0.56 mW at a supply voltage of 1.8 V. The simulation results show that the calibration improves SNDR to 83.73 dB from 55.13 dB with 1% capacitance mismatch, and the calibration needs three conversion cycles which makes it real-time to obtain the changing error parameters during normal operation. & 2016 Elsevier Ltd. All rights reserved.

Keywords: Cyclic ADC Sensor Digital calibration

1. Introduction Recently, the growth in demand for high-performance and highly integrated sensors has stimulated research and development efforts. In general, single-slope, successive approximation, and cyclic analog-to-digital converters (ADCs) are widely used for a variety of sensors, such as temperature sensors, image sensors, and pressure sensors [1–3]. Cyclic ADCs are flexible in integrated sensors because of the tradeoff among medium resolution, medium speed and low power consumption, low area [4–6]. Many non-ideal factors, such as comparator offset, charge injection, the op-amp finite gain and the capacitor mismatch, limit the accuracy of the cyclic ADC [7]. To correct the non-linear errors of the ADCs, many calibration algorithms are developed, including analog calibration and digital calibration algorithms. The analog calibration algorithms such as capacitor ratio-independent technique and random feedback capacitor interchanging technique are proposed to improve the linearity of the cyclic ADCs resulting in the increasing complexity of analog blocks and the decreasing conversion speed [8,9]. The performance of analog circuits is influenced much more than that of digital circuits by the changes of the environment. An interesting digital background calibration method that takes use of the comparator decision time to measure the missing code width and calibrate the ADC's nonlinearity is presented [10,11]. However, the silicon area of the digital n

Corresponding author. E-mail address: [email protected] (J. Gao).

http://dx.doi.org/10.1016/j.mejo.2016.04.019 0026-2692/& 2016 Elsevier Ltd. All rights reserved.

background calibration algorithms is very large, so that it is difficult to integrate the calibration block into small integrated sensors directly [12]. As a result, the digital foreground calibration algorithms are reported in recent years. In 2008, a cyclic ADC with digital error correction circuits is presented [13]. The error-correction block including memories for all the error coefficients of the 640 ADC channels is integrated in the image sensor chip, so that the number of the calibration cycles is very large when it get the error coefficients column by column. In 2012, the columnparallel two-stage cyclic ADC with 12-bit resolution used in a 33Mpixel 120-fps CMOS image sensor for super high-vision is presented to decrease the time of quantization per sample [14]. In 2014, the digital calibration for two-stage cyclic ADC is presented to increase the linearity [15]. However, all the error parameters are achieved when the system is power-on, so that the high linearity of the ADC cannot be guaranteed when the circuit parameters change. In 2010, a 13-bit low-power compact ADC suitable for sensor array applications has been developed [16]. This kind of ADC can achieve high resolution with precise first order incremental ΣΔ converter to get the upper bits, and a cyclic ADC to get the lower bits. However, it cannot reach a high speed due to the application of the ΣΔ converter. In this paper, a scheme is proposed to update the error parameters in real time while one calibration block is shared by five ADCs. The calibration algorithm is realized by compensating the weight of the jumping points in the digital domain. The area of the calibration block is relatively small because adders and registers are utilized without multipliers. This kind of ADC includes four

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conversion periods. The first three conversion periods are used to get the error parameters, and then the digital output corrected is selected and read out in the fourth conversion period. The ADC output can maintain high accuracy when the circuit parameters change at the price of large silicon area cost. Therefore, the method can be applied to the applications with strict requirement of real-time accuracy but relaxed requirement of silicon area. And with the feature size of the technology scaling down, the scheme is more preferred. Meanwhile, the performance of cyclic ADC primarily depends on one parameter: the residue gain. However, multiple sets of sample capacitors and amplifiers used in the sample-hold amplifier (SHA) and multiplying digital-to-analog converter (MDAC) will change the residue gain, which makes the calibration more difficult. To ensure the stability of the non-linear errors, only one amplifier and a couple of sample capacitors are used in the cyclic ADC proposed in this paper. The paper is organized as follows. The architecture of the cyclic ADC proposed and its overall operation are described in Section 2. In Section 3, the errors are analyzed and the digital calibration method is proposed. The ideas are verified by the simulation results in Section 4. In Section 5, the conclusions are drawn.

clks clka clk1 clk2 clk3

clk4 Fig. 2. Timing diagram of the cyclic ADC.

rewritten as

Vout =

Cs +ΔCs Cf +ΔCf

1+

Vout =

Vout =

Cs1 (V Cf 1 in +

− Vshort − Vos )

1+

Cs1 +Cf 1 ACf 1

−

Cs V Cf in

⎛ − ⎜1 + ⎝ 1+

Cs 2 (V Cf 2 in −

Vout (2) =

Cs 2 +Cf 2 ACf 2

(2)

ACf

Cs +ΔCs ⎞ ⎟V Cf +ΔCf ⎠ os

Cs +Cf

(3)

ACf

⎛ ⎜1 + ⎝

Cs ⎞ ⎟V (1) Cf ⎠ out

C

− b1 Cs Vref − f

1+

(1)

where Vout ¼ Vout þ  Vout  , Vshort is the source voltage when the switch controlled by clka is turned on. A and Vos denote the gain and offset voltage of the op-amp, respectively. Since A is sufficiently large, (Cs1 þ Cf1)/(ACf1) and (Cs2 þCf2)/(ACf2) terms in the denominator are approximately equal to (Cs þ Cf)/(ACf). Using Cs1 ¼Cs þΔCs, Cs2 ¼Cs  ΔCs, Cf1 ¼Cf þΔCf, and Cf2 ¼Cf  ΔCf, (1) is

Cs +Cf

In the next phase, the bottom plates of Cs1 and Cs2 are connected to the output of the amplifier as illustrated in Fig. 3(c). The output voltage Vout is sampled by Cs1 and Cs2, and delivered to the sub-ADC. If the reference voltage is Vref, the code b is equal to 1,  1, or 0, depending on whether the output voltage of the amplifier is more than Vref/4, less than Vref/4 or between  Vref/4 and Vref/4. An important property of the 1.5-bit/cycle is that the comparator offset, Voff, up to  Vref/4 rVoff rVref/4 can be corrected in the digital domain. This property of the 1.5-bit/cycle algorithm greatly relaxes the comparator precision requirement. Fig. 3(d) shows the second bit decision phase. The top plates of Cs1 and Cs2 are connected to the amplifier, while the bottom plates are connected to a 1.5-bit DAC which uses the decision results of the comparators. The output of this phase is given by

− Vshort ) + Vos

1+

(Vin − − Vshort ) − Vos

In the signal read-out phase, Vin ¼Vin þ  Vin  , and Vshort is approximately equal to (Vin þ þVin  )/2, and hence Vout is simplified to

2. Proposed cyclic architecture Fig. 1 shows the architecture of the proposed ADC and the timing diagram is shown in Fig. 2. The proposed ADC consists of a MDAC and a sub-ADC. The configurations during different phases are shown in Fig. 3(a)–(d). In the input signal sampling phase, as illustrated in Fig. 3(a), the differential inputs are connected to the bottom plates of the capacitors Cs1 and Cs2, and the switch controlled by clk1 is first turned on to connect the top plates of Cs1 and Cs2. The differential input signals are sampled by Cs1 and Cs2, respectively. Meanwhile, Cf1 and Cf2 are reset. During the first bit decision phase, as illustrated in Fig. 3(b), the switch controlled by clks is turned off. And the top plates of Cs1 and Cs2 are connected to the amplifier, and their bottom plates are short-circuited by turning on the switch controlled by clka. After these operations, the differential output Vout is given by

Cs −ΔCs Cf −ΔCf

(Vin + − Vshort − Vos ) −

Cs +ΔCs V Cf +ΔCf os

Cs +Cf

(4)

ACf

where Vout(1) is the output voltage of the first bit decision phase sampled by Cs1 and Cs2, b1 is the first 1.5-bit digital code. After this phase, the bottom plates of Cs1 and Cs2 are connected to the output of the amplifier, as shown in Fig. 3(c). The two operations shown in Fig. 3(c) and (d) are alternately repeated until all of the fourteen bit decision phases are finished. An extra two-bit decision phases are added to extract the error parameters accurately for calibration.

3. Digital calibration algorithm 3.1. Error analysis The foregoing results can be extended to multiple cycles in the proposed cyclic ADC. In the ith (iZ2) bit decision phase, the output is obtained as:

Vout (i) =

⎛ ⎜1 + ⎝

Cs ⎞ ⎟V (i Cf ⎠ out

C

− 1) − bi − 1 Cs Vref − f

1+ Fig. 1. Schematic of the cyclic ADC.

Cs +ΔCs V Cf +ΔCf os

Cs +Cf ACf

(5)

Y. Zong et al. / Microelectronics Journal 54 (2016) 93–100

Cf1

Cs1

Vos

Vin+

+-

Cf1

Cs1

V +-os

+

Vin-

-

Cs2

Cf 2

(b)

Cf1

Vrefp

Cs1

+

Vout+

-

Vout-

Cf1

Cs1

V+-os

Vout+

+ -

Cs2

Cf 2

Vout-

Cf2

(a)

+-

Vout+

+

-

Cs2

Vos

95

Vrefn

Vout-

Cs2

Cf2 (d)

(c) Fig. 3. Circuit configuration for A/D conversion.

Eqs. (3)–(5) show that the residue voltage of each cycle is influenced by errors caused by capacitor mismatch, finite op-amp gain and amplifier offset. Eq. (5) can be simplified

Vout (i) = (1 + p)[(2 + g ) Vout (i − 1) − bi − 1 × (1 + g ) × Vref − εVos ]

(6)

D=−1

D=0

D=1

D(Vref) (1+p)(1+g)Vref

Missing Code

where p, ε and g are coefficients of the finite op-amp gain, amplifier offset and capacitor mismatch ratio, respectively. Ideally, p ¼0, ε ¼1, g ¼0, Vos ¼0. The linearity of the ADC is not affected by the amplifier offset. And large capacitors can reduce the influence of the kT/C noise. In Eq. (6), (1 þp)(1þg)bVref is subtracted instead of bVref in actual circuit operation, while the output code is compensated by the D(bVref) in the digital domain. The difference between analog and digital domain causes missing codes at the jumping threshold points, as shown in Fig. 4.

Vout/Dout

Vin

3.2. Digital calibration 3.2.1. The principle of digital calibration Nonlinearity of the ADC mainly happens at the jumping points. Ideally, the difference value of the digital codes is one, and the difference value of analog residue voltages is Vref between two sides of the jumping points. After the residue voltages of the stage to be calibrated are quantized by ideal backend ADC, the final output digital codes are equal because of the 1.5-bit/cycle algorithm. Actually, the difference value of the residue voltages quantized by the backend ADC is not Vref due to the gain error and capacitor mismatch. Now, after getting the digital output of the non-ideal jumping height by backend quantization, the actual digital output with the non-ideal jumping height can be compensated. Thus the missing code can be eliminated at the jumping points. The algorithm cannot correct the gain slope error which does not affect the linearity of the ADC. In this paper, the error parameters are measured by modifying the method presented in [17]. The calibration process is executed from a lower bit to the most significant bit (MSB). To measure the error parameters of each bit, the cyclic ADC input is set equal to

-Vref/4

Vref/4

Fig. 4. Residue plot for cyclic ADC without calibration.

the upper comparator threshold(Vref/4), and the output is measured twice, yielding two digital codes D0 when the corresponding first bit decision is forced to 0 and D1 when the corresponding first bit decision is forced to 1. It is the same to D2 and D3 when the input signal is –Vref/4. After the error parameters are got, D(Vref) in the digital domain can be compensated:

ΔD (Vref ) = D3 − D2 for b = 00 ΔD (Vref ) = D0 − D1 for b = 10 ΔD (Vref ) = 0 for b = 01

(7)

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Y. Zong et al. / Microelectronics Journal 54 (2016) 93–100

Vout/Dout D=−1

D=0

D=1 D((1+p)(1+g)Vref)

(1+p)(1+g)Vref

Vin Fig. 7. The SFDR and SNDR versus the No. of the bits calibrated (including least 2 bits to detect the errors).

Vref/4

-Vref/4

Fig. 5. Residue plot for cyclic ADC with calibration.

where b represents the digital output of sub-ADC. Thus, the missing code can be eliminated, as shown in Fig. 5. Then the calibration will be converted to the higher bit while the calibrated bit is added into the backend ADC. After the error parameters of the MSBs are got, the digital correction starts. For simplicity, the error parameters are only obtained at the Vref/4 because jumping heights at the two-comparator threshold points are almost the same.

Fig. 8. The INL and DNL without calibration.

calculating the error parameters of the bit to be calibrated. The b in the box filled in light green color represents the least significant bit (LSB). The direction of the red arrow indicates that the calibration starts from the lower bit to MSB. Thus, all the error parameters are calculated by choosing relevant b and the digital output can be compensated in the third conversion period. Therefore, the

3.2.2. Modeling of the digital calibration algorithm p and g are constant as the non-ideal coefficients of each bit, because cyclic ADC is one stage of pipeline ADC. Therefore, all the values of b can be obtained in the first two conversion periods, as shown in Fig. 6. In figure, the b closed in the dashed box is used for

MSB-5

b1

b2

b3

b4

b5

b6

b7

b8

b9

b10

b11

b12

b13

b14

b15

b16

MSB-4

b1

b2

b3

b4

b5

b6

b7

b8

b9

b10

b11

b12

b13

b14

b15

b16

MSB-3

b1

b2

b3

b4

b5

b6

b7

b8

b9

b10

b11

b12

b13

b14

b15

b16

MSB-2

b1

b2

b3

b4

b5

b6

b7

b8

b9

b10

b11

b12

b13

b14

b15

b16

MSB-1

b1

b2

b3

b4

b5

b6

b7

b8

b9

b10

b11

b12

b13

b14

b15

b16

MSB

b1

b2

b3

b4

b5

b6

b7

b8

b9

b10

b11

b12

b13

b14

b15

b16

Fig. 6. The process of error estimation from the lower bit to MSB. (For interpretation of the references to color in this figure, the reader is referred to the web version of this article.)

Y. Zong et al. / Microelectronics Journal 54 (2016) 93–100

97

Figs. 8 and 9. The simulation results indicate that the calibration block can efficiently correct the nonlinearity caused by the capacitance mismatch and finite amplifier gain. Meanwhile, the

calibration needs three conversion cycles. Then the behavior model is established in Matlab Simulink. With the gain error p¼ 1‰ and the capacitance mismatch g ¼5‰, the SFDR is improved to 89.69 dB from 59.42 dB as shown in Fig. 7. The maximum INL is decreased to 0.31 LSB from 5.21 LSB and the maximum DNL is decreased to 0.16 LSB from 1 LSB as shown in

Vdd

Vcmfb

Vcmfb

Vb1

M4 M5

M6 M7

Vb2

M8

M9

VoutVin+

M2

Vb3

Vin- M10

M3

Vb4

M1

Vout+

M11 M12

M13

GND Fig. 9. The INL and DNL with calibration.

Fig. 11. The schematic of the folded-cascode amplifier.

-Vref/4

+Vref/4 Control the input signal in calibratron mode

MUX Vin2

Vin1

Vin3

Vin4

Vin5

Force first bit decision

ADC-1 bi(1)

Accum

Regisier

D(1)

DVref

DVref

Regisier

Regisier

D(2)

ADC-5 bi(5)

(Control)

DVref

(Control)

DVref

Accum

Accum

Accum

(ADC output)

ADC-4 bi(4)

(Control)

(Control)

DVref

(ADC output)

ADC-3 bi(3)

bi(2)

(Control)

Correction Logic

ADC-2

Regisier

Accum

Regisier

D(3)

D(4)

D(5)

(ADC output)

(ADC output)

(ADC output)

30×16b RAM

D1(n)

Control D0(n)

∆D(n)=D1(n)-D0(n)

Update e(n)

Error Estimation

Turn to next ADC

Fig. 10. Block diagram of the calibration loop for the cyclic ADC array.

98

M5

Y. Zong et al. / Microelectronics Journal 54 (2016) 93–100

clk

Vdd M9 M3

Vop

Von M3

Vip

M1P

clk M6

M8 M10

M4 M2N

Vrefn Vrefp

clk

M2P

M1N

Vin

M0

GND Fig. 12. The schematic of the dynamic comparator.

Fig. 15. Simulated ADC output spectra: (a) without calibration; (b) with calibration.

Table 1 SNDR versus capacitance mismatch.

Fig. 13. The state machine of the digital block.

linearity cannot get further improvement when the number of bits calibrated is more than six. Therefore, it is enough to calibrate the upper six bits of the ADC. 3.2.3. The architecture of the whole ADC To achieve acceptable silicon area consumption and calibration speed, each error estimation circuit is shared by five ADCs. Each ADC has a digital output circuit which mainly includes shifting

SNDR

Capacitance mismatch with 0.3%

Capacitance mismatch with 1%

Before calibration After calibration

63.56 dB 85.28 dB

55.13 dB 83.73 dB

registers and accumulators. As shown in Fig. 10, when the calibration of the ADC-n (1 r nr 5) starts, the input is set approximately equal to Vref/4 first. The comparator output is forced both high in the first bit decision phase (the 1.5-bit code is 11). By the operation of the digital output circuits, shifting registers are used to realize the storage of the error parameters and accumulators are used to get the ADC output D1(n). Repeating the above operations, the 1.5-bit code in the first bit decision phase is forced to be 01 to get another ADC output D0(n). Then control circuit turns the input signal to  Vref/4, and the digital outputs D2(n) and D3(n) are obtained by setting the 1.5-bit code in the first bit decision phase to 00 and 01, respectively. The error parameters are stored as a 16-bit binary code in the Calibration Circuits (1000 μm)

Width=150 μm (five columns)

MDAC (700 μm)

Length=1700 μm Fig. 14. Layout of proposed ADC architecture.

Y. Zong et al. / Microelectronics Journal 54 (2016) 93–100

99

Table 2 Comparison with some previous work.

Resolution Conversion rate Supply voltage Power per ADC SNDR Technology Active area(mm2) Real-time calibration FOM(pJ/step) a

This work

Ref. [5]

Ref. [13]

Ref. [16]

Ref. [18]

Ref. [19]

Ref. [20]

14 bits 333KSPS 1.8 V 0.553 mW 83.73 dB 180 nm 0.051 Y 0.102

13 bits 167KSPSa 3.3 V 0.3 mW / 180 nm / N 0.22

14 bits 15KSPSa 3.3 V / / 180 nm / N /

13 bits 19.5KSPS 1.8 V 0.115 mW 65.4 dB 180 nm 0.06 N 0.72

9 bits 50MSPS 1V 6.9 mW 50.3 dB 90 nm 0.019 N 0.504

12 bits 2MSPS 3.3 V 0.43 mW / 250 nm 0.088 N 0.05

12 bits 20MSPS 3.3 V 0.43 mW 72.5 dB 350 nm / N 0.78

The conversion rate is estimated from the references.

calibration circuits. When the calibration of ADC-n is finished, the calibration circuit will turn its connection to the next ADC (ADC(n þ1)). The calibration starts from ADC-1 to ADC-5. In addition, if all the five ADCs are calibrated, the digital output circuits can get corrected outputs with the stored parameters. 3.3. Circuits implementation The ADC is mainly consisted of a MDAC, sub-ADC and the digital block. The architecture of the MDAC and sub-ADC is shown in Fig. 11. The MDAC is a kind of switch capacitor integrator. A fully differential folded-cascode amplifier is designed in the MDAC circuits, the main architecture of which is shown in Fig. 11, because the folded-cascode amplifier has a good trade-off among the gain, output range and bandwidth. In Fig. 11, the Vcmfb is the commonmode feedback voltage. Vb1, Vb2, Vb3 and Vb4 are the bias voltages. Vin þ and Vin  consists differential input while Vout þ and Vout  consists differential output. The sub-ADC is a 1.5-bit ADC, which mainly includes two comparators, and quantizes the residue voltage. Two dynamic comparators are used in the ADC because of their low-power characteristic and one comparator's schematic is shown in Fig. 12. The W/L of M2(N,P) is one-fourth of that of M1(P,N) so the threshold of the comparator is 1/4(Vrefp  Vrefn). The inputs of the M2N and M2P in another comparator are exchanged and its threshold is 1/4(Vrefn  Vrefp). The digital module is realized by using the Verilog HDL hardware description language. The state machine of the digital block is shown in Fig. 13. State1 represents that the digital block is doing the calibration and state2 represents that the digital block is on the normal operation. The calibration process is just given in the Section 3.2.2. When the calibration is finished, the digital block goes into the normal operation state and it works like an adder accumulating the outputs of the sub-ADC. Once there happens to be a dramatic change of the environment, which has a great influence on the performance of the circuits, the digital block can go back to state1 from state2 to do the calibration again. The Design Compiler and the Encounter are used to transform the codes of digital block into transistor-level circuit.

4. Results and comparison The ADC array consisting of 5 ADCs has been designed in standard 0.18 μm CMOS technology, as shown in Fig. 14. The silicon area cost of each ADC is 0.03
1.7 mm2 and the power consumption is 0.56 mW at a supply voltage of 1.8 V. A fully differential folded-cascode amplifier is designed in the MDAC circuits with open-loop gain of 80 dB, phase margin of 68 degrees, and unity-gain frequency of 42 MHz. And the voltage swing on each output is from 0.6 to 1.2 V. The power consumption is 553 μW,

including 518.4 μW for analog part and 34.6 μW for digital calibration part. Fast Fourier transform (FFT) plots of the ADC are shown in Fig. 15.The SNDR is improved to 83.73 dB from 63.56 dB. As shown in Table 1, the calibration algorithm can tolerate 1% capacitance mismatch with the gain error p ¼0.2‰. Table 2 shows the comparison of the proposed ADC with several previous work. Due to the short calibration cycles, the scheme can realize the real-time calibration when the circuit parameters change during normal operation.

5. Conclusion A cyclic ADC with real-time digital calibration is designed in this work. The calibration block of correcting the weight of the jumping points is implemented only by adders and registers. The silicon area cost is reduced because multipliers are not utilized. The structure of MDAC is modified to measure the actual heights of the jumping points. The linearity of the ADC is improved by compensating the weight of the jumping points in the digital domain. Designed in a 0.18 μm CMOS technology, the simulation results show that the calibration improves SNDR to 83.73 dB from 55.13 dB with 1% capacitance mismatch. The linearity of the cyclic ADC is improved significantly even with larger capacitor mismatch. The calibration needs three conversion cycles, which makes it real-time to obtain the changing error parameters during normal operation.

Acknowledgments This work is supported by National Natural Science Foundation of China Grant (nos. 61404090, 61434004 and 61306070).

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