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Optimal digital reconstruction and calibration for multichannel Time Interleaved ΣΔ ADC based on Comb-filters
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Optimal digital reconstruction and calibration for multichannel Time Interleaved ADC based on Comb-filters Ali Beydoun a,∗ , Van-Tam Nguyen b,1 , Lirida Naviner b,1 , Patrick Loumeau b,1 a b
Lebanese university, Physics and Electronics Department, Hadath campus, Beirut, Lebanon Institut TELECOM - TELECOM ParisTech, SIAM Group, 46 rue Barrault, 75634 Paris Cedex 13, France
a r t i c l e
i n f o
Article history: Received 8 April 2010 Received in revised form 3 January 2012 Accepted 5 October 2012 Keywords: Sigma-delta Digital filtering Calibration Gain and offset mismatches Analog-to-digital conversion Time-interleaving
a b s t r a c t High resolution, large dynamic range wideband Analog to Digital Converter (ADC) remains a bottleneck to realize software and cognitive radio receivers. Time Interleaved Sigma-Delta (TI) architecture is a potential candidate to increase the bandwidth of the like ADCs. However, very high digital filter complexity is required and it is very sensitive to channel mismatch which is unavoidable especially in advanced manufacturing process. This paper proposes a new digital signal processing based on Comb-filter cells and correction FIR filter. Comparing to existing solutions, the proposed solution reduces Drastically the digital filter complexity and thus the power consumption and the die area of the digital post-filtering at the backend of the TI ADC. This solution was validated and synthesized in a 1.2 V, 65 nm CMOS process using VHDL language. The total die area is estimated to 0.115 mm2 . Moreover, this paper proposes a fully digital gain equalization and offset cancellation methods without any additional material resources. These methods achieve a high accuracy with a very short calibration time estimated to about 10 clock cycles. © 2012 Elsevier GmbH. All rights reserved.
1. Introduction The current evolution of telecommunication systems goes toward versatile, reconfigurable and multistandard receiver. To achieve this goal, the software and cognitive radio concepts proposed by Mitola [1,2] present an interesting solution. In the radio frequency (RF) receiver, the basic idea consists in moving the ADC as near as possible to the antenna so that most signal processing is carried out in the digital domain making smart management of the frequency resources and dynamic reconfiguration easier and less expensive in terms of hardware resource. In this context, high resolution, high sampling rate ADC with large dynamic range and high speed signal processor are required. Many solutions based on sigma-delta modulators and employing parallelism have been proposed to increase the conversion bandwidth: frequency band decomposition (FBD) [3], parallel sigma-delta () [4], and time interleaved sigma-delta (TI)) [5,6].
∗ Corresponding author. Tel.: +961 70814058. E-mail addresses: [email protected] (A. Beydoun), [email protected] (V.-T. Nguyen), [email protected] (L. Naviner), [email protected] (P. Loumeau). 1 Tel.: +33 1 45 81 78 43.
The TI converter provides the best tradeoff between performances and implementation complexity compared with the other architectures. However, it has two main drawbacks which limit its performance. The first one lies in the complexity of the digital post-processing at the backend of the ADC: to reconstruct the useful signal, the optimal filter proposed in [5] requires a large number of taps especially in high resolution applications. A huge hardware resource is then needed. The second one is its high sensitivity to both offset and gain mismatches between sigmadelta modulators, which leads to distortion and spurious tones decreasing the expected signal to noise plus distortion ratio (SNDR). In order to overcome these drawbacks, this paper presents: • an alternative digital signal processing based on Comb-filters allowing to drastically reduce the digital filter complexity and thus the power consumption and the silicon area of the digital part, • an innovative digital offset cancellation and channel gain equalization methods achieving a high accuracy at short calibration time. Moreover, its implementation does not require any additional modulator or reference signal generator. It employs only the proposed digital filter for the reconstruction of the useful signal. After a brief description of the TI ADC architecture, Section 3 presents the novel digital signal processing based on Comb-filters.
1434-8411/$ – see front matter © 2012 Elsevier GmbH. All rights reserved. http://dx.doi.org/10.1016/j.aeue.2012.10.004
Please cite this article in press as: Beydoun A, et al. Optimal digital reconstruction and calibration for multichannel Time Interleaved ADC based on Comb-filters. Int J Electron Commun (AEÜ) (2012), http://dx.doi.org/10.1016/j.aeue.2012.10.004
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Fig. 1. TI ADC architecture.
Section 4 sheds light on the effect of the gain and offset mismatches and their relevant calibration methods. The implementation of the digital part is detailed in Section 5. Finally, Section 6 concludes with the performances of the new digital filter and calibration methods. 2. TI architecture The simplified schematic of the TI converter is depicted in Fig. 1. The architecture is composed of M parallel low-pass modulators. The analog input signal is sampled at the Nyquist rate fs . Then, the signal x[n] is distributed between the M modulators through an analog demultiplexer and interpolated by a factor N to compress the useful signal bandwidth. The signal goes then through the modulator and the quantization noise shaping is carried out. Afterwards, the output of each modulator is filtered by the digital filter H(z) to suppress out of band quantization noise. Finally, the signal is decimated by a factor N to reduce the data rate before being multiplexed by a digital multiplexer to reconstruct the output signal y[n]. The output of each modulator is affected by a gain g and an offset o resulting from manufacturing process. The effect of these errors on the overall performances will be discussed in Section 4. Relying on the linear model of the modulator shown in Fig. 1, the overall output of the TI ADC y[n] is the sum of the overall signal components yx [n] and the overall quantization error components ye [n]: y[n] = yx [n] + ye [n]
(1)
The overall signal component is just a delayed version of the input signal (2) [4] if the digital filter coefficients of H(z) satisfies the condition (3). Yx (z) = z
−(M−1−L)
h [n] =
X(z)
1 n = (L − 1)/2, L : is the filter length L−1 ) is multiple of N 0 where (n − 2
(2) (3)
The theoretical SNR of a TI ADC depends on three parameters: the order of the modulators (P), the number of bits of the quantizer and the interpolation factor (N). The conversion bandwidth depends on the number of channel (M). The number of taps in digital filters (L) determines the hardware complexity needed to reach a targeted SNDR. These parameters depend on the targeted standards: the bandwidth of the input signal, the required resolution, the reconfiguration capacity. Relying on these requirements and on the theoretical performances of the TI ADC [5], a prototype of 4 channels TI has been designed in a 1.2 V 65 CMOS process [7].
Table 1 Four channels TI specifications for different standards. Standards
M
N
P
fs
fop
B
GSM/EDGE UMTS/DVB-T WiMax/WiFi
1 2 4
96 52 32
2 4 4
270 KHz 8 MHz 55 MHz
26 MHz 208 MHz 208 MHz
135 KHz 4 MHz 11/12.5 MHz
SNR 80 dB 80 dB 52 dB
The specifications for each standard are summarized in Table 1. They were chosen as a compromise of power consumption and robustness. To reach these theoretical performances, it remains to determine the best digital post-processing with the lowest computational resources. In the following of this paper and without loss of generality, only the third scenario (WiMax/WiFi) will be detailed. Simulation results with the other scenarios will be summarized in tables throughout this paper [8].
3. Digital processor An optimal filter topology which fulfills the perfect reconstruction constraints (3) was proposed in [4]. The other coefficients not expressed in (3) are calculated in order to minimize the quantization noise power at the output of the TI ADC. Fig. 2 shows the SNDR with respect to the optimal filter length. It can be noticed that: • the higher the interpolation rate N, the higher the minimum filter length (Lmin ) to reach a positive SNDR. The minimum length is approximately equal to N. • the first local maximum is reached for L = 2N • after reaching the first local maximum, the SNDR value becomes periodic with period of 2N. This is because the edge coefficients of the optimal filter impulse response are close to zero only when a completely secondary lobe on each side is added. According to these results, a 200th and 100th order optimal lowpass filters are required respectively for the second and the third scenarios to reach the targeted SNDR. This filter length carries to the implementation of 100/50 multiplications and 200/100 additions in each channel operating at the modulator frequency fop = 208 MHz. In order to reduce digital filter complexity, an alternative solution is proposed in this paper based on Comb-filters because they can operate at high sampling rates while minimizing hardware
Please cite this article in press as: Beydoun A, et al. Optimal digital reconstruction and calibration for multichannel Time Interleaved ADC based on Comb-filters. Int J Electron Commun (AEÜ) (2012), http://dx.doi.org/10.1016/j.aeue.2012.10.004
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3
80
(a)
SNDR (dB)
60 40
M=4 N=32
20
SNDR théorique
Lmin=N
0 −20
(b)
0
100
200
300
400
500
600
700
65.7 65.65
SNDR (dB)
65.6 65.55 65.5 65.45
2N
65.4 65.35 300
350
400
450
500
550
600
650
700
L Fig. 2. SNDR with respect to the optimal filter length for N = 32.
C(z) =
1 −i z N N−1
K
i=0
=
1 1 − z −N N 1 − z −1
K (4)
where K and N are the order of the Comb-filter and the decimation ratio. Compared with the optimal filter, the Comb-filter impulse response doesn’t satisfy the perfect reconstruction condition in (3). Then, the overall output signal component is not a simple delayed version of the input signal. It is a filtered version as shown in the following Eq. [10]: Yx (z) = H (z M )z −(M−1−L) X(z)
(5)
where H (z) =
J
hc [iN] z −i
with JN ≤ LC
(6)
i=d
with hc [n] is the impulse response of the Comb-filter, d the decimation delay of the impulse response hc [n], LC the length of hc [n] and J is an integer number. The filtering effect (H (zM )) appears as equiripples on the magnitude of the output spectrum. To correct this effect, the solution proposed here is to use a correction filter F(z) at the output of the TI ADC based on least mean square (LMS) FIR filter. The order of this correction filter depends on the equiripples magnitude introduced by H (zM ) and the equiripples magnitude depends on both the order of the Comb-filter and on the decimation delay d. It has been shown in [11] that, for a P modulator order, an P + 1 Comb-filter order is enough to reduce aliasing terms due to the decimation. Fig. 3 shows the H (zM ) equiripples magnitude respect to the decimation delay d for 5th (i.e. P + 1) and 6th (i. e. P + 2) Comb-filter order. It can be noticed that with a 6th order Comb-filter, minimum ripples are reached with zero delay while the 5th order Comb-filter has maximum ripples with zero delay and requires approximately N = 16 delays on the input signal to achieve minimum ripples 2
(a) Ripple magnitude (dB)
magnitudes. We can note that for a lower correction filter complexity, the order of the Comb-filter must be the first even number higher than P + 1. Fig. 4 shows the frequency response magnitude in dB of H (zM ), F(z) and the result of correction. For a 6th order Comb-filter, the ripples magnitude is about 17 dB. Therefore, a 30th order correction filter is enough to equalize ripples with a maximum error of 3 × 10−4 dB. The error with a 30th order correction filter is insignificant. In practice, ripples magnitude of 1 dB is acceptable without considerable degradation of the performances. This margin of error allows to reduce the complexity of the correction filter. The correction filter equalizes the filtering effect introduced by H (zM ) whereas it amplifies at the same time the quantization noise at the output leading to a decrease of the SNDR. So, the optimal order of the correction filter must ensure magnitude
40 Order:5 30
20
10 0
5
10
15
20
25
30
15
20
25
30
(b) Ripple magnitude (dB)
complexity [9]. The transfer function C(z) of a Comb-filter is defined by:
400
Order:6
300 200 100 0 0
5
10
retard i Fig. 3. Equiripples magnitude respect to the decimation delay d for a 5th and 6th order Comb-filter.
Please cite this article in press as: Beydoun A, et al. Optimal digital reconstruction and calibration for multichannel Time Interleaved ADC based on Comb-filters. Int J Electron Commun (AEÜ) (2012), http://dx.doi.org/10.1016/j.aeue.2012.10.004
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Magnitude (dB)
(a)
M
F(z )
After correction
0
H’(zM)
(b)
4
Magnitude (dB)
−50
3
0
0.05
0.1
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
x 10−4
2 1 0 −1 −2
0
Normalized Frequency (×π rad/sample) Fig. 4. a) Magnitude of H (zM ) transfer function and correction filter F(zM ) (b) zoom of the magnitude error.
ripples less than 1 dB without large amplification of the quantization noise. Fig. 5 shows the SNDR (calculated for sine input signal with normalized amplitude of 1 and normalized frequency of 0.12) and the magnitude ripples with respect to the correction filter length. It can be noticed that a 10th order correction filter is sufficient to have magnitude ripples less than 1 dB and an SNDR of 67 dB. In the same way, the optimal order of the correction filters for the first and the second scenarios are 14 and 10 respectively (Table 3). To illustrate the effect of the correction filter, Fig. 6 shows the power spectral densities (PSD) at the output, before and after correction, while considering a sine wave signal at the input localized at the normalized frequency f0 with normalized amplitude of 0.7.
It can be noticed that: • for a low normalized frequency (f0 = 0.02) the SNDR before correction is equal to 76 dB. The transfer function H (zM ) does not introduce high attenuation at low frequencies (Fig. 4) and then the expected SNDR is maintained. After the correction filter, the SNDR is reduced to 62 dB because the correction filter does not amplify the useful signal whereas amplifying the quantization noise. • for the normalized frequency f0 = 0.12, the SNDR before correction is equal to 58 dB. This is because the attenuation introduced by the transfer function H (zM ) reaches its maximum value at this frequency (Fig. 4). The SNDR will be improved after the correction filter to reach the desired value of 62 dB. In this case, the
f =0.1202 0
68
0
5
10
15
20
25
30
35
20 18
67.5
14
SNDR (dB)
67 12 10
66.5
8 66
6
Ripples magnitude(dB)
16
4 65.5 2
65
0 0
5
10
15
20
25
30
35
Correction filter length Fig. 5. SNDR and magnitude ripples after correction compared to correction filter length.
Please cite this article in press as: Beydoun A, et al. Optimal digital reconstruction and calibration for multichannel Time Interleaved ADC based on Comb-filters. Int J Electron Commun (AEÜ) (2012), http://dx.doi.org/10.1016/j.aeue.2012.10.004
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Before correction
After correction
0
50
f0=0.02 SNDR=76.4 dB
−100 −150 −200 −250
0
0.1
0.2
0.3
0.4
−150
−250
0.5
0
0.1
0.2
0.3
0.4
0.5
50
f =0.12 SNDR=59.3 dB
−50
f =0.12 SNDR=62.2 dB
0
0
PSD (dB)
PSD (dB)
−50 −100
−200
0
−100 −150 −200 −250 −300
f0=0.02 SNDR=62.3 dB
0
PSD (dB)
PSD (dB)
−50
−300
5
0
−50 −100 −150 −200
0
0.1
0.2
0.3
0.4
0.5
−250
0
0.1
0.2
f
0.3
0.4
0.5
f
Fig. 6. Power spectral density at the output before and after correction with a sine signal at the input.
correction filter amplifies at the same time the useful signal and the quantization noise allowing to regain the useful signal amplitude with a light amelioration of the SNDR. • after the corrections filter, the SNDR is almost constant (62 dB) regardless of the frequency of the input signal. • the correction filter, which has a linear phase, will increase the overall delay at the output signal without introducing any distortion. In fact, as the same components are used in each channel, the same delay will be added in each channel and consequently the overall signal at the output y[n] will be affected by this delay. In order to optimize the computing resources for the digital processing and as the second and the third scenarios use time interleaving technique with 4th order modulators, it is enough to implement four 6th order Comb-filters able to work with the highest interpolation factor (N = 52). As for the first scenario, it uses single channel with 2nd order modulator. Therefore, it requires only a 3rd order Comb-filter [11]. In addition to the 5 Comb-filters, a correction filter is needed for each scenario to equalize the bandpass attenuation introduced by the Comb-filter (single channel) or the filtering effect H (zM ) (multi channels). 4. Digital calibration The TI ADC is very sensitive to gain and offset mismatches, induced by the manufacturing process, between the modulators. These mismatches introduce spurious tones at the output spectrum leading to a drop down of the theoretical SNDR. Several solutions have been proposed to calibrate gain and offset mismatches. These solutions could be classified according to the three following approaches: 1. The first approach aims to compensate the gain and the offset of each channel by adding a digital sigma-delta modulator on each channel [12] or by using a PRBS (pseudo random binary sequence)-controlled chopper at the ADC input [13], 2. The second approach aims to equalize gain and offset of all modulators by using an extra modulator as a reference modulator [14],
3. The third approach uses randomization of the channel selection to spread out the spurious tones energy over the frequency spectrum. A randomization technique was proposed in [15] using an extra channel. The main drawback of these calibration method is that they require extra material resources ( modulator, PRBS generator, etc.). Furthermore, some solutions requires a feed back from the digital processing to the input of the modulator which increases the implementation constraints of the modulator. In order to overcome the drawbacks of the calibration methods mentioned above, we propose an innovative digital calibration method based on a mix of the first two approaches [16]. This new method [17] consists in: • Estimating the offset value on each channel and then subtracting it from the useful signal. This approach is chosen because even if all the offsets resulting from manufacturing process are equal, the offset value will be added to the useful signal at the output of the TI ADC and it will be difficult to distinguish it from the offset value in the useful signal leading to a significant decrease of the SNDR. • Equalizing the gain of modulators to the gain of one of them used as a reference modulator. This suppresses spurious tones without any additional modulator. 4.1. Offset cancellation Due to the time demultiplexer at the output of the TI ADC, the presence of the offset oi on each channel (Fig. 1) adds a periodic signal to the useful signal of period M. This periodic signal causes fs additive tones at integer multiples of the channel sampling rate M on the spectrum at the output of the TI leading to a huge lost of the SNDR. Fig. 7 (a) shows the PSD at the output while considering the following offsets, normalized to the reference voltage, for all channels: [−0.202, 0.717, 0.765, 0.1832] × 10−4 . In this case, the SNDR is reduced by 28 dB. The offset cancellation requires first the estimation of its value and then the subtraction of the estimated value from the output
Please cite this article in press as: Beydoun A, et al. Optimal digital reconstruction and calibration for multichannel Time Interleaved ADC based on Comb-filters. Int J Electron Commun (AEÜ) (2012), http://dx.doi.org/10.1016/j.aeue.2012.10.004
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a) Before correction 50
PSD (dB)
Spurious tone
Useful signal
0
SNDR=48.5 dB
−50 −100 −150 −200 0
0.1
0.2
0.3
0.4
0.5
b) After correction 50
PSD (dB)
Spurious tone
Useful signal
0
SNDR=76.5 dB
−50 −100 −150 −200 0
0.1
0.2
0.3
0.4
0.5 Fig. 8. SNDR compared to the accuracy on the estimated value of the offset.
f Fig. 7. The PSD at the output before and after the calibration of the offset mismatch.
The estimation of the offset value is performed by the Combfilter in each channel. Indeed, the Comb filter has a very small bandwidth and a high out of band attenuation (N = 32) which allows to have a good estimation of the offset value at its output when the input of the modulator is connected to the ground (see Fig. 9). To illustrate the efficiency of the Comb-filter, Fig. 10 presents the estimation error defined as the difference between the true offset value and the estimated one at the output of the Comb-filter. It can be noticed that the desired accuracy 10−6 for the estimated value is reached after 10 clock cycles ((M × N)/fs ). For the other modes, the lower targeted accuracy are also achieved with 10 clock cycles due to the very selective bandwidth of the Comb-filter for high decimation factor N = 52 and N = 96. Fig. 7 (b) shows the PSD of the output signal after the compensation of the offset on each channel. It can be noticed a decrease of the spurious tones amplitude until the level of the quantization noise allowing to regain the expected SNDR.
signal of each modulator. Regarding the estimation phase, it is essential to know the required accuracy on the estimated value. For this purpose, Fig. 8 shows the SNDR at the output while subtracting the offset O value with a relative error ε: (O × (1 + ε)). It can be noticed that the SNDR evolves linearly with respect to the precision before reaching saturation until the spurious tone amplitude decreases to reach the quantization noise level. According to this result, there is a linear relationship between the required accuracy for the estimated value and the expected SNDR. It is given by: estimation precision = 10−k = 10
− SNDR+26 20
(7)
As a result, a high theoretical SNDR (high interpolation rate) requires more accuracy for the estimation of the offset values. For the example considered in this paper, the required accuracy to achieve the expected SNDR is 10−6 . f 50
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5 0
−100 0
−50 −300
−400 −100
Magnitude (dB)
PSD (dB)
−200
−500 −150 −600
−200
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
−700 0.5
f Fig. 9. PSD at the output of the modulator and frequency response of the Comb-filter with K = 6 and N = 32.
Please cite this article in press as: Beydoun A, et al. Optimal digital reconstruction and calibration for multichannel Time Interleaved ADC based on Comb-filters. Int J Electron Commun (AEÜ) (2012), http://dx.doi.org/10.1016/j.aeue.2012.10.004
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7
Amplitude
(a) 0.05 0 −0.05
0
2000
4000
6000
8000
10000
12000
14000
16000
Amplitude
(b) 0.02 0
Fig. 12. Block diagram of the gain calibration method.
−0.02 2
4
6
8
Amplitude
1
10
12
14
16
18
14000
16000
(c)
−5
x 10
0 −1
2000
4000
6000
8000 n
10000
12000
Fig. 10. Estimation error (a), zoom in the interval time 0 ≤ n ≤ 18 (b), zoom in the interval time 10 ≤ n ≤ 16000 (c).
4.2. Gain equalization The multiplication of the output signal of each channel by a gain gi is equivalent, due to the digital multiplexer at the output, to multiplying the useful signal at the output of the TI ADC by a periodic signal of period M formed by the different gains gi (Fig. 1). This multiplication results in a convolution between the spectrum of the useful signal and the spectrum of the periodic signal. The fs latter spectrum is composed of tones located at frequencies k M (k an integer) whose magnitude is given by the discrete Fourrier series of the periodic signal. This convolution produces images of the spectrum of the useful signal weighted by the tone magnitudes [18]. Fig. 11 (a) shows the PSD at the output of the TI ADC where the following gains [1.0113, 1.0146, 1.0029, 0.9884] are present on all channels. It can be noticed that a 1% of gain mismatch leads to a 36 dB decrease of the desired SNDR. It is therefore essential
to equalize the channel gain mismatch to maintain the expected performances. The gain calibration method proposed in this paper supposes that the correction of the offset on each channel was already performed and then aims to equalize the gain on all channels to the gain of one of them considered as the reference channel. The block diagram of this method is depicted in Fig. 12 where the first channel is considered as the reference channel. The different steps of this method are: • The input signal is a constant signal applied to all modulators simultaneously. The magnitude of this signal Vin is fixed, without V any loss of generality, to 2R where VR is the reference voltage. Any other values in the input dynamic range of the modulator can be used. • The output signal of the ith modulator is composed of the constant input signal Vin multiplied by the gain gi and the quantization noise shaped by the modulator. The Comb-filter H(z) extracts the useful signal value Vin × gi on each channel with the same accuracy for offset estimation (Section 4.1). • The Least Mean Square (LMS) algorithm calculates the weight value wi to equalize the gain of the ith channel to that of the reference channel (channel 1 in Fig. 12): gi × wi = g1 |i=2...M
(8)
The LMS algorithm and its varieties (SD-LMS Sign-Data LMS, SELMS Sign-Error LMS, SS-LMS Sign data Sign Error LMS) have been chosen for their implementation simplicity compared to other
Before correction 0
SNR=40 dB
Spurious tone
Useful signal
PSD (dB)
−50 −100 −150 −200 −250
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
After correction 0
Useful signal
PSD (dB)
−50
SNR=76.6 dB
Spurious tone
−100 −150 −200 −250
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
f Fig. 11. PSD at the TI output before and after correction in the presence of gain mismatch.
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Table 2 Optimal parameters and computing resources for all types of the LMS algorithm. Algorithm
Multiplications
Additions
Convergence time
LMS
1
1
2
Ct = 35 fN
SD-LMS
1
0
2
Ct = 15 fN
SE-LMS
1 216
1(shift)
2
Ct = 780 f
SS-LMS
1 216
0
2
Ct = 1550 fN
1 μ=0.1 μ=0.2
0.9995
μ=0.3
op
0.999
μ=0.4
op
N
op
μ=0.5
2
0.9985
μ=0.6
w
op
μ=0.7
0.998
estimation algorithms. The estimation of wi using these algorithms is given by: LMS: ˆ i [n + 1] = w ˆ i [n] + (y1 [n] − yi [n]) × yi [n] w
(9)
SD-LMS:
μ=0.8 0.9975
(10)
SE-LMS: ˆ i [n + 1] = w ˆ i [n] + sgn [(y1 [n] − yi [n])] × yi [n] w
(11)
μ=1
0.997
0.9965
ˆ i [n + 1] = w ˆ i [n] + (y1 [n] − yi [n]) × sgn [yi [n]] w
μ=0.9
0
20
40
60
80
100
n Fig. 14. Estimation of the weight w2 with the SD-LMS algorithm for different values of .
SS-LMS: ˆ i [n + 1] = w ˆ i [n] + sgn [(y1 [n] − yi [n])] × sgn [yi [n]] w
(12)
where is the step of the algorithm. The performances of these algorithms will be summarized in Table 2 at the end of this section. In the following, only simulation results with the SD-LMS algorithm will be presented. Before evaluating the performance of the LMS algorithm, it is important to know the required accuracy for the weight values wi to ensure a good calibration of the gain mismatch. Fig. 13 presents the SNDR after the gain calibration with respect to the relative error ε introduced on the theoretical value of the weights wi : (wi × (1 + ε)). It can be noticed that, with the same reasoning as for the offset estimation values, there is a linear relationship between the required accuracy for the weight values and the SNDR. It is given by: Weight precision = 10−k = 10
− SNDR−5 19
(13)
10−4
For example, an accuracy of is required to regain the targeted SNDR (76 dB) for the third mode. The step of the LMS algorithm controls the convergence time and the accuracy for the estimated weights. Fig. 14 shows the estimated weight w2 at each iteration n using the SD-LMS algorithm for
Fig. 13. SNDR at the output of the TI with respect to the relative error ε on the weight values.
Fig. 15. Maximum estimation error of the weight w2 with respect to .
Fig. 16. The estimation of the weights using SD-LMS algorithme with = 1.
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Before correction 0
Spurious tones (offset)
Spurious tones (gain)
SNDR=39.4 dB
PSD (dB)
−50 −100 −150 −200
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
After correction 0
PSD (dB)
Spurious tones (gain)
Spurious tones (offset)
−50
SNDR=76.4 dB
−100 −150 −200 −250
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
f Fig. 17. PSD at the TI output before and after correction in the presence of gain and offset mismatch simultaneously.
different values of and Fig. 15 shows the maximum estimation error once the convergence is achieved with respect to . It can be noticed that the value = 1 ensures the shortest convergence time with the best accuracy (6.6 × 10−6 compared to the desired accuracy 10−4 ). Moreover, this value simplifies the implementation of this algorithm by removing the multiplication operation. Fig. 16 shows the estimated weights with the SD-LMS algorithm with the step = 1. In these conditions, the convergence of the algorithm to the desired weight values is reached after 10 clock cycles. Fig. 11 (b) shows the he PSD at the output after applying the calibration algorithm for 15 clock cycles. As a result, there is a decrease of the amplitude of spurious tones to the level of quantization noise thus regaining the expected SNDR. In order to consider a real example, gain and offset are considered simultaneously in the basic example with values given by the following vectors: O = [−0.202, 0.717, 0.765, 0.1832] × 10−4 and g = [1.0113, 1.0146, 1.0029, 0.9884] The offset cancellation is applied first and then the gain equalization algorithm is applied taking into account the residual offset mismatch remaining after the offset cancellation. Fig. 17 shows the PSD at the output before and after calibration. It can be noticed that the gain equalization algorithm regains the expected performance even in the presence of weak offset mismatch. The total run time calibration is 25 clock cycles. Table 2 summarizes the optimal step and the convergence time for the four types of the LMS algorithm. The SE-LMS and SS-LMS present the easiest implementation way and the least hardware complexity. However, they present the largest convergence time. The SD-LMS is the best tradeoff between convergence time and implementation complexity.
5. Digital part implementation The two main blocks of the digital part are the Comb-filter and the correction filter. According to Eq. 4, Comb-filter can be efficiently implemented using the recursive architecture as shown in Fig. 18. To avoid overflow, the integration part requires register lengths of:
Bin + K × log 2(N)
(14)
where Bin is the input word length. However, the recursive architecture does not have the optimal power consumption when the filter order and the decimation ratio are high [19]. An alternative non-recursive structure could be used to overcome this drawback but the decimation ratio must be a power of 2 [19] which is not the case for all modes in our designed circuit. According to formula 14, the output signal at the last integrator must be quantized with 38 and 22 bits for the 6th and 3rd order Comb-filter respectively. On the other hand, due to the several differentiator stages, the amplitude of the output signal will decrease. This means that rounding may be applied at the output of the last differentiator to delete the extra Least significant bits (LSB). Fig. 19 shows the SNDR computed at the output of 6th order Comb-filter (modes 2 and 3) with respect to the number of deleted LSB bits. It is clearly shown that a deletion of 15 LSB bits doesn’t degrades the targeted SNDR. In the same manner, it was verified by simulation that a deletion of 5 LSB bits doesn’t degrade the expected the desired SNDR for the first mode with 3rd order Comb-filter.
Fig. 18. Recursive Comb-filter architecture.
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120
SNDR (dB)
100 80 60 40 20 30 30
20 20 10
10
Nbit2
0
0
Nbit1
Fig. 21. SNDR with respect to the number of deleted low bits Nbit1 and Nbit2 . Fig. 19. SNDR at the 6th order Comb-filter output respect to the number of deleted low bits.
As well as for the correction filter, it can be implemented in an optimal way using coefficients symmetry as shown in Fig. 20 (Vm is the maximum coefficient value). We have verified by simulation that coefficient values must be quantized with 8 bits resolution to maintain the expected SNDR of the TI ADC. To optimize the silicon area, a rounding is applied after each multiplication to keep the useful most significant bits and delete the other LSB bits ( Nbit i ). Fig. 21 shows the
Table 3 Computing digital reconstruction resources and implementation results. Entity
Order
Comb filter (mode 1) Comb filter (mode 1/2) Correction filter (mode 1) Correction filter (mode 2) Correction filter (mode 3)
3 6 14 10 10
fop 26 MHz 208 MHz 270 KHz 8 MHZ 55 MHz
Gates number
Area
434 4 × 3399 1612 1666 2119
0.00367 4 × 0.0165 0.013 0.014 0.0184
i=1,2
SNDR at TI ADC output when varying Nbit1 and Nbit2 separately. It can be noticed that the sum of deleted bit number Nbit1 + Nbit2 is almost constant while maintaining the expected
SNDR. The combination with the largest Nbit1 value has been chosen because the number of multiplication before the accumulator is higher than the number of multiplication after the accumulator.
Fig. 20. Correction filter F(z) implementation architecture.
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Table 3 summarizes the synthesis results of each component in a 1.2 V, 65 nm CMOS process using VHDL language. The estimated silicon area is 0.115 mm2 . 6. Conclusion Theoretically and also in the system-level’s point of view, TI is a promising solution for wide band conversion. The performance of the converter depends on four parameters, the number of channels, the interpolation rate, the order of the modulator and the filter complexity. Thus, there is an additional freedom degree compared to traditional ADC. However, their implementation and their performance remains limited due to various sources of imperfection. This paper has proposed a novel solution for the digital reconstruction and for gain and offset calibration in TI ADC. The proposed solution is based on the use of a Comb-filter after each modulator. Comb-filters ensure a good reconstruction of the useful signal with much lower computing resources than that using optimal filters. Moreover, Comb-filters are used in the gain and offset calibration process. The proposed calibration method has a very short calibration time estimated of 10 clock cycles for offset and gain calibration. This method could be used also with other parallel ADC architecture as the Parallel Sigma Delta () using Hadamard modulation. Implemented in a 1.2 V, 65 nm CMOS, the total die area is estimated to 0.115 mm2 . The proposed calibration method facilitates the adaptation of time interleaved architecture to achieve high performances ADC. However, there are a lot of challenges and difficulties to implement such a converter. Here are some of them: • Interpolation at the input of the S. modulator is always needed even with Nyquist solution i.e. N = M. In fact, it re-samples the input signal at very high rate, therefore all modulators work at the much higher rate than fs , unlike traditional TI ADCs. Even when a Nyquist solution is envisaged, all modulators work at the “full rate” fs . In another word, the main advantage of traditional TI ADC namely the reduced rate of individual ADC disappears. • Implementation of the interpolation function is a very challenging task. • Dynamic channel mismatch is much more difficult and more expensive to calibrate, especially at high rate. • Clock skew needs to be reduced or correction technique is required even when a full rate sample/hold circuit is used at the frond-end of the ADC. Acknowledgement This research work was supported by the French Research Agency in the frame of project Versanum ANR-05-RNRT-010-01. References [1] Mitola J, Zvonar Z. Software radio technologies: selected readings. Wiley-IEEE Press; 2001. [2] Mitola III J, Maguire Jr G. Cogniive radio: making software radios more personal. IEEE Pers Commun 1999;6:13–8. [3] Benabes P, Beydoun A, Oksman J. Extended frequency-band-decomposition sigma-delta A/D converter. In: Analog integrated circuits and signal processing. 2009. [4] Galton I, Jensen HT. Delta-sigma modulator based A/D conversion without oversampling. IEEE Trans Circuit Syst II 1995 December;42:773–84. [5] Eshraghi A. High-speed parallel delta-sigma analog-to-digital converters. PhD Thesis, Washington State University; 1999 May. [6] Nguyen V, Loumeau P, Naviner J. Analysis of time-interleaved delta-sigma analog to digital converter. IEEE Vehicular Technol Conf 2002;4:1594–7. [7] Versanum project. French Research Agency ANR-05-RNRT-010-01.
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[8] Beydoun A, Jabbour C, Fakhoury H, Nguyen VT, Naviner L, Loumeau P. A 65 nm CMOS versatile ADC using time interleaving and modulation for multimode receiver. In: IEEE, NEWCAS-TAISA. 2009. [9] Naviner L, Naviner B, de Barros J. Programmable digital channel selector for multimode radio receiver. In: Signal processing and information technology, 2004. Proceedings of the fourth IEEE international symposium on. 2004. p. 5–8. [10] Eshraghi A, Fiez T. A time-interleaved parallel A/D converter. IEEE Trans Circuit Syst II March 2003;50:118–29. [11] Norsworthy S, Schreier R, Temes G. Delta-sigma data converters, theory, design and simulation. NJ: IEEE Press; 1997. [12] Batten R, Eshraghi A, Fiez T. Calibation of parallel ADCs. IEEE Trans Circuits Syst II 2002;49:390–9. [13] Eklund J, Gustafsson F. Digital offset compensation of time-interleaved ADC using randomchopper sampling. In: Proceedings of the 2000 IEEE international symposium on circuits and systems. ISCAS 2000, Geneva. 2000. [14] Ferragina V, Fornasari A, Gatti U, Malcovati P, Maloberti F. Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators. IEEE Trans Circuits Syst I: Regul Pap 2004;51:2365–73. [15] Eshraghi A, Fiez T. A comparative analysis of parallel delta-sigma adc architectures. IEEE Trans Circuit Syst I 2004 March;51:450–8. [16] Beydoun A, Nguyen VT, Loumeau P. Correction des dfauts analogiques dans des convertisseurs analogiques/numriques parallles, notamment pour des applications multistandars, radio logicielle et/ou radio-cognitive. Patent, Number Fr 09-55351; July 2009. [17] Beydoun A, Nguyen VT, Loumeau P. A novel digital calibration technique for gain and offset mismatch in parallel TI ADCs. Dallas, Texas: IEEE, ICASSP; 2010. [18] Petraglia A, Mitra S.IEEE transactions on analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer. Instrumentation and measurement, vol. 40. 1991. p. 831–5. [19] Gao Y, Jia L, Isoaho J, Tenhunen H. A comparison design of Comb decimators for sigma-delta analog-to-digital converters. Analog Integrated Circuits Signal Process 2000;22:51–60. Ali Beydoun was born in Beirut, Lebanon, in 1980. He received a B.S. in Electronics from the University of Lebanon in 2002, an Engineering Degree in Telecommunications from the ENSIETA school, Brest, France, in 2004 and a Ph.D in Electronics from Paris XI university in 2007. From 2007 to 2009, he was a research assistant at the Institut Telecom - ParisTech. Since October 2009, he is assistant professor at the Lebanese university. His research focuses on the development of advanced RF architecture for software and cognitive radio applications and spectrum sensing algorithms. Van Tam Nguyen received the Diplme d’Ingnieur from Ecole Suprieure d’Electricit (Supelec - www.supelec.fr) and a M.Sc. degree in automatic and signal processing from University Paris Sud (www.u-psud.fr) in 2000, and a Ph.D. degree in Communications and Electronic from Ecole Nationnale Suprieure des Tlcommunications (Telecom ParisTech- www.telecom-paristech.fr) in 2004. From 2000 to 2005 he was research engineer at Schlumberger and Telecom ParisTech working mainly on European Project SPRING (Scientific Multidisciplinary Network for metering - IST1999-12342). In 2005 he joined Telecom ParisTech as an Associate Professor. His main research interests are in the areas of cognitive radio network, software defined radio, sensor network, wireless communication system and network. In particular, his research focuses on reconfigurable radio interface, flexible radio frequency front-end, digital/analog/radio frequency partioning, mixed signal interference cancellation, sensing algorithm for cognitive radio, algorithms for MIMO spectrum sensing, cooperation sensing with reduced delay in relaying decisions, digital oriented architecture for SoC sensor and routing algorithms in wireless sensor network for power saving. Lirida Alves de Barros Naviner received the Electrical Engineering and the M.S. degrees from the Federal University of Paraiba (UFPB-Brazil, 1988 and 1990), the Ph.D degree from the Ecole Nationale Suprieure des Tlcommunications (ENSTFrance, 1994) and the HDR degree from the University Pierre et Marie Curie (UPMC-France, 2006). She joined the team of UFPB in 1994, where she was a faculty member in the Electrical Engineering and the Computation Science Departments. Since 1998 she works at Telecom ParisTech where she is a professor in the Department Electronics and Communications. Her research interests include evolvable hardware, reconfigurable and reliable circuits, algorithms and architectures for telecommunications. This relates to applications with severe constraints of computation power and flexibility. She has a large experience on algorithm-architecture codesign of hardware IP and her actual research focuses on design for reliability. [Dr. Lirida Naviner has published more than hundred papers and has supervised several works in these and related areas]. Dr. Lirida Naviner is IEEE Senior Member and she is member of the reviewing committee of many international conferences and journals. Patrick Loumeau received the engineer degree in 1982 from the Institut National des Telecommunications in Paris, France. He received the authorization to manage research diploma in 2000. He joined the Ecole Nationale Superieure des Telecommunications of Paris in 1982. He is Professor in the Analog and Mixed IC Design group, Communications and Electronics Department. He is in charge of research on analog and mixed IC for telecommunications. He has realized a number of research and development project with industry, national research center and universities. He has co-authored more than 50 technical publications in international congress and revues. He is a member of IEEE Solid State Circuits Society, and Circuits and Systems Society.
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Contents lists available at SciVerse ScienceDirect
International Journal of Electronics and Communications (AEÜ) journal homepage: www.elsevier.com/locate/aeue
Optimal digital reconstruction and calibration for multichannel Time Interleaved ADC based on Comb-filters Ali Beydoun a,∗ , Van-Tam Nguyen b,1 , Lirida Naviner b,1 , Patrick Loumeau b,1 a b
Lebanese university, Physics and Electronics Department, Hadath campus, Beirut, Lebanon Institut TELECOM - TELECOM ParisTech, SIAM Group, 46 rue Barrault, 75634 Paris Cedex 13, France
a r t i c l e
i n f o
Article history: Received 8 April 2010 Received in revised form 3 January 2012 Accepted 5 October 2012 Keywords: Sigma-delta Digital filtering Calibration Gain and offset mismatches Analog-to-digital conversion Time-interleaving
a b s t r a c t High resolution, large dynamic range wideband Analog to Digital Converter (ADC) remains a bottleneck to realize software and cognitive radio receivers. Time Interleaved Sigma-Delta (TI) architecture is a potential candidate to increase the bandwidth of the like ADCs. However, very high digital filter complexity is required and it is very sensitive to channel mismatch which is unavoidable especially in advanced manufacturing process. This paper proposes a new digital signal processing based on Comb-filter cells and correction FIR filter. Comparing to existing solutions, the proposed solution reduces Drastically the digital filter complexity and thus the power consumption and the die area of the digital post-filtering at the backend of the TI ADC. This solution was validated and synthesized in a 1.2 V, 65 nm CMOS process using VHDL language. The total die area is estimated to 0.115 mm2 . Moreover, this paper proposes a fully digital gain equalization and offset cancellation methods without any additional material resources. These methods achieve a high accuracy with a very short calibration time estimated to about 10 clock cycles. © 2012 Elsevier GmbH. All rights reserved.
1. Introduction The current evolution of telecommunication systems goes toward versatile, reconfigurable and multistandard receiver. To achieve this goal, the software and cognitive radio concepts proposed by Mitola [1,2] present an interesting solution. In the radio frequency (RF) receiver, the basic idea consists in moving the ADC as near as possible to the antenna so that most signal processing is carried out in the digital domain making smart management of the frequency resources and dynamic reconfiguration easier and less expensive in terms of hardware resource. In this context, high resolution, high sampling rate ADC with large dynamic range and high speed signal processor are required. Many solutions based on sigma-delta modulators and employing parallelism have been proposed to increase the conversion bandwidth: frequency band decomposition (FBD) [3], parallel sigma-delta () [4], and time interleaved sigma-delta (TI)) [5,6].
∗ Corresponding author. Tel.: +961 70814058. E-mail addresses: [email protected] (A. Beydoun), [email protected] (V.-T. Nguyen), [email protected] (L. Naviner), [email protected] (P. Loumeau). 1 Tel.: +33 1 45 81 78 43.
The TI converter provides the best tradeoff between performances and implementation complexity compared with the other architectures. However, it has two main drawbacks which limit its performance. The first one lies in the complexity of the digital post-processing at the backend of the ADC: to reconstruct the useful signal, the optimal filter proposed in [5] requires a large number of taps especially in high resolution applications. A huge hardware resource is then needed. The second one is its high sensitivity to both offset and gain mismatches between sigmadelta modulators, which leads to distortion and spurious tones decreasing the expected signal to noise plus distortion ratio (SNDR). In order to overcome these drawbacks, this paper presents: • an alternative digital signal processing based on Comb-filters allowing to drastically reduce the digital filter complexity and thus the power consumption and the silicon area of the digital part, • an innovative digital offset cancellation and channel gain equalization methods achieving a high accuracy at short calibration time. Moreover, its implementation does not require any additional modulator or reference signal generator. It employs only the proposed digital filter for the reconstruction of the useful signal. After a brief description of the TI ADC architecture, Section 3 presents the novel digital signal processing based on Comb-filters.
1434-8411/$ – see front matter © 2012 Elsevier GmbH. All rights reserved. http://dx.doi.org/10.1016/j.aeue.2012.10.004
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Fig. 1. TI ADC architecture.
Section 4 sheds light on the effect of the gain and offset mismatches and their relevant calibration methods. The implementation of the digital part is detailed in Section 5. Finally, Section 6 concludes with the performances of the new digital filter and calibration methods. 2. TI architecture The simplified schematic of the TI converter is depicted in Fig. 1. The architecture is composed of M parallel low-pass modulators. The analog input signal is sampled at the Nyquist rate fs . Then, the signal x[n] is distributed between the M modulators through an analog demultiplexer and interpolated by a factor N to compress the useful signal bandwidth. The signal goes then through the modulator and the quantization noise shaping is carried out. Afterwards, the output of each modulator is filtered by the digital filter H(z) to suppress out of band quantization noise. Finally, the signal is decimated by a factor N to reduce the data rate before being multiplexed by a digital multiplexer to reconstruct the output signal y[n]. The output of each modulator is affected by a gain g and an offset o resulting from manufacturing process. The effect of these errors on the overall performances will be discussed in Section 4. Relying on the linear model of the modulator shown in Fig. 1, the overall output of the TI ADC y[n] is the sum of the overall signal components yx [n] and the overall quantization error components ye [n]: y[n] = yx [n] + ye [n]
(1)
The overall signal component is just a delayed version of the input signal (2) [4] if the digital filter coefficients of H(z) satisfies the condition (3). Yx (z) = z
−(M−1−L)
h [n] =
X(z)
1 n = (L − 1)/2, L : is the filter length L−1 ) is multiple of N 0 where (n − 2
(2) (3)
The theoretical SNR of a TI ADC depends on three parameters: the order of the modulators (P), the number of bits of the quantizer and the interpolation factor (N). The conversion bandwidth depends on the number of channel (M). The number of taps in digital filters (L) determines the hardware complexity needed to reach a targeted SNDR. These parameters depend on the targeted standards: the bandwidth of the input signal, the required resolution, the reconfiguration capacity. Relying on these requirements and on the theoretical performances of the TI ADC [5], a prototype of 4 channels TI has been designed in a 1.2 V 65 CMOS process [7].
Table 1 Four channels TI specifications for different standards. Standards
M
N
P
fs
fop
B
GSM/EDGE UMTS/DVB-T WiMax/WiFi
1 2 4
96 52 32
2 4 4
270 KHz 8 MHz 55 MHz
26 MHz 208 MHz 208 MHz
135 KHz 4 MHz 11/12.5 MHz
SNR 80 dB 80 dB 52 dB
The specifications for each standard are summarized in Table 1. They were chosen as a compromise of power consumption and robustness. To reach these theoretical performances, it remains to determine the best digital post-processing with the lowest computational resources. In the following of this paper and without loss of generality, only the third scenario (WiMax/WiFi) will be detailed. Simulation results with the other scenarios will be summarized in tables throughout this paper [8].
3. Digital processor An optimal filter topology which fulfills the perfect reconstruction constraints (3) was proposed in [4]. The other coefficients not expressed in (3) are calculated in order to minimize the quantization noise power at the output of the TI ADC. Fig. 2 shows the SNDR with respect to the optimal filter length. It can be noticed that: • the higher the interpolation rate N, the higher the minimum filter length (Lmin ) to reach a positive SNDR. The minimum length is approximately equal to N. • the first local maximum is reached for L = 2N • after reaching the first local maximum, the SNDR value becomes periodic with period of 2N. This is because the edge coefficients of the optimal filter impulse response are close to zero only when a completely secondary lobe on each side is added. According to these results, a 200th and 100th order optimal lowpass filters are required respectively for the second and the third scenarios to reach the targeted SNDR. This filter length carries to the implementation of 100/50 multiplications and 200/100 additions in each channel operating at the modulator frequency fop = 208 MHz. In order to reduce digital filter complexity, an alternative solution is proposed in this paper based on Comb-filters because they can operate at high sampling rates while minimizing hardware
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3
80
(a)
SNDR (dB)
60 40
M=4 N=32
20
SNDR théorique
Lmin=N
0 −20
(b)
0
100
200
300
400
500
600
700
65.7 65.65
SNDR (dB)
65.6 65.55 65.5 65.45
2N
65.4 65.35 300
350
400
450
500
550
600
650
700
L Fig. 2. SNDR with respect to the optimal filter length for N = 32.
C(z) =
1 −i z N N−1
K
i=0
=
1 1 − z −N N 1 − z −1
K (4)
where K and N are the order of the Comb-filter and the decimation ratio. Compared with the optimal filter, the Comb-filter impulse response doesn’t satisfy the perfect reconstruction condition in (3). Then, the overall output signal component is not a simple delayed version of the input signal. It is a filtered version as shown in the following Eq. [10]: Yx (z) = H (z M )z −(M−1−L) X(z)
(5)
where H (z) =
J
hc [iN] z −i
with JN ≤ LC
(6)
i=d
with hc [n] is the impulse response of the Comb-filter, d the decimation delay of the impulse response hc [n], LC the length of hc [n] and J is an integer number. The filtering effect (H (zM )) appears as equiripples on the magnitude of the output spectrum. To correct this effect, the solution proposed here is to use a correction filter F(z) at the output of the TI ADC based on least mean square (LMS) FIR filter. The order of this correction filter depends on the equiripples magnitude introduced by H (zM ) and the equiripples magnitude depends on both the order of the Comb-filter and on the decimation delay d. It has been shown in [11] that, for a P modulator order, an P + 1 Comb-filter order is enough to reduce aliasing terms due to the decimation. Fig. 3 shows the H (zM ) equiripples magnitude respect to the decimation delay d for 5th (i.e. P + 1) and 6th (i. e. P + 2) Comb-filter order. It can be noticed that with a 6th order Comb-filter, minimum ripples are reached with zero delay while the 5th order Comb-filter has maximum ripples with zero delay and requires approximately N = 16 delays on the input signal to achieve minimum ripples 2
(a) Ripple magnitude (dB)
magnitudes. We can note that for a lower correction filter complexity, the order of the Comb-filter must be the first even number higher than P + 1. Fig. 4 shows the frequency response magnitude in dB of H (zM ), F(z) and the result of correction. For a 6th order Comb-filter, the ripples magnitude is about 17 dB. Therefore, a 30th order correction filter is enough to equalize ripples with a maximum error of 3 × 10−4 dB. The error with a 30th order correction filter is insignificant. In practice, ripples magnitude of 1 dB is acceptable without considerable degradation of the performances. This margin of error allows to reduce the complexity of the correction filter. The correction filter equalizes the filtering effect introduced by H (zM ) whereas it amplifies at the same time the quantization noise at the output leading to a decrease of the SNDR. So, the optimal order of the correction filter must ensure magnitude
40 Order:5 30
20
10 0
5
10
15
20
25
30
15
20
25
30
(b) Ripple magnitude (dB)
complexity [9]. The transfer function C(z) of a Comb-filter is defined by:
400
Order:6
300 200 100 0 0
5
10
retard i Fig. 3. Equiripples magnitude respect to the decimation delay d for a 5th and 6th order Comb-filter.
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Magnitude (dB)
(a)
M
F(z )
After correction
0
H’(zM)
(b)
4
Magnitude (dB)
−50
3
0
0.05
0.1
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
x 10−4
2 1 0 −1 −2
0
Normalized Frequency (×π rad/sample) Fig. 4. a) Magnitude of H (zM ) transfer function and correction filter F(zM ) (b) zoom of the magnitude error.
ripples less than 1 dB without large amplification of the quantization noise. Fig. 5 shows the SNDR (calculated for sine input signal with normalized amplitude of 1 and normalized frequency of 0.12) and the magnitude ripples with respect to the correction filter length. It can be noticed that a 10th order correction filter is sufficient to have magnitude ripples less than 1 dB and an SNDR of 67 dB. In the same way, the optimal order of the correction filters for the first and the second scenarios are 14 and 10 respectively (Table 3). To illustrate the effect of the correction filter, Fig. 6 shows the power spectral densities (PSD) at the output, before and after correction, while considering a sine wave signal at the input localized at the normalized frequency f0 with normalized amplitude of 0.7.
It can be noticed that: • for a low normalized frequency (f0 = 0.02) the SNDR before correction is equal to 76 dB. The transfer function H (zM ) does not introduce high attenuation at low frequencies (Fig. 4) and then the expected SNDR is maintained. After the correction filter, the SNDR is reduced to 62 dB because the correction filter does not amplify the useful signal whereas amplifying the quantization noise. • for the normalized frequency f0 = 0.12, the SNDR before correction is equal to 58 dB. This is because the attenuation introduced by the transfer function H (zM ) reaches its maximum value at this frequency (Fig. 4). The SNDR will be improved after the correction filter to reach the desired value of 62 dB. In this case, the
f =0.1202 0
68
0
5
10
15
20
25
30
35
20 18
67.5
14
SNDR (dB)
67 12 10
66.5
8 66
6
Ripples magnitude(dB)
16
4 65.5 2
65
0 0
5
10
15
20
25
30
35
Correction filter length Fig. 5. SNDR and magnitude ripples after correction compared to correction filter length.
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Before correction
After correction
0
50
f0=0.02 SNDR=76.4 dB
−100 −150 −200 −250
0
0.1
0.2
0.3
0.4
−150
−250
0.5
0
0.1
0.2
0.3
0.4
0.5
50
f =0.12 SNDR=59.3 dB
−50
f =0.12 SNDR=62.2 dB
0
0
PSD (dB)
PSD (dB)
−50 −100
−200
0
−100 −150 −200 −250 −300
f0=0.02 SNDR=62.3 dB
0
PSD (dB)
PSD (dB)
−50
−300
5
0
−50 −100 −150 −200
0
0.1
0.2
0.3
0.4
0.5
−250
0
0.1
0.2
f
0.3
0.4
0.5
f
Fig. 6. Power spectral density at the output before and after correction with a sine signal at the input.
correction filter amplifies at the same time the useful signal and the quantization noise allowing to regain the useful signal amplitude with a light amelioration of the SNDR. • after the corrections filter, the SNDR is almost constant (62 dB) regardless of the frequency of the input signal. • the correction filter, which has a linear phase, will increase the overall delay at the output signal without introducing any distortion. In fact, as the same components are used in each channel, the same delay will be added in each channel and consequently the overall signal at the output y[n] will be affected by this delay. In order to optimize the computing resources for the digital processing and as the second and the third scenarios use time interleaving technique with 4th order modulators, it is enough to implement four 6th order Comb-filters able to work with the highest interpolation factor (N = 52). As for the first scenario, it uses single channel with 2nd order modulator. Therefore, it requires only a 3rd order Comb-filter [11]. In addition to the 5 Comb-filters, a correction filter is needed for each scenario to equalize the bandpass attenuation introduced by the Comb-filter (single channel) or the filtering effect H (zM ) (multi channels). 4. Digital calibration The TI ADC is very sensitive to gain and offset mismatches, induced by the manufacturing process, between the modulators. These mismatches introduce spurious tones at the output spectrum leading to a drop down of the theoretical SNDR. Several solutions have been proposed to calibrate gain and offset mismatches. These solutions could be classified according to the three following approaches: 1. The first approach aims to compensate the gain and the offset of each channel by adding a digital sigma-delta modulator on each channel [12] or by using a PRBS (pseudo random binary sequence)-controlled chopper at the ADC input [13], 2. The second approach aims to equalize gain and offset of all modulators by using an extra modulator as a reference modulator [14],
3. The third approach uses randomization of the channel selection to spread out the spurious tones energy over the frequency spectrum. A randomization technique was proposed in [15] using an extra channel. The main drawback of these calibration method is that they require extra material resources ( modulator, PRBS generator, etc.). Furthermore, some solutions requires a feed back from the digital processing to the input of the modulator which increases the implementation constraints of the modulator. In order to overcome the drawbacks of the calibration methods mentioned above, we propose an innovative digital calibration method based on a mix of the first two approaches [16]. This new method [17] consists in: • Estimating the offset value on each channel and then subtracting it from the useful signal. This approach is chosen because even if all the offsets resulting from manufacturing process are equal, the offset value will be added to the useful signal at the output of the TI ADC and it will be difficult to distinguish it from the offset value in the useful signal leading to a significant decrease of the SNDR. • Equalizing the gain of modulators to the gain of one of them used as a reference modulator. This suppresses spurious tones without any additional modulator. 4.1. Offset cancellation Due to the time demultiplexer at the output of the TI ADC, the presence of the offset oi on each channel (Fig. 1) adds a periodic signal to the useful signal of period M. This periodic signal causes fs additive tones at integer multiples of the channel sampling rate M on the spectrum at the output of the TI leading to a huge lost of the SNDR. Fig. 7 (a) shows the PSD at the output while considering the following offsets, normalized to the reference voltage, for all channels: [−0.202, 0.717, 0.765, 0.1832] × 10−4 . In this case, the SNDR is reduced by 28 dB. The offset cancellation requires first the estimation of its value and then the subtraction of the estimated value from the output
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a) Before correction 50
PSD (dB)
Spurious tone
Useful signal
0
SNDR=48.5 dB
−50 −100 −150 −200 0
0.1
0.2
0.3
0.4
0.5
b) After correction 50
PSD (dB)
Spurious tone
Useful signal
0
SNDR=76.5 dB
−50 −100 −150 −200 0
0.1
0.2
0.3
0.4
0.5 Fig. 8. SNDR compared to the accuracy on the estimated value of the offset.
f Fig. 7. The PSD at the output before and after the calibration of the offset mismatch.
The estimation of the offset value is performed by the Combfilter in each channel. Indeed, the Comb filter has a very small bandwidth and a high out of band attenuation (N = 32) which allows to have a good estimation of the offset value at its output when the input of the modulator is connected to the ground (see Fig. 9). To illustrate the efficiency of the Comb-filter, Fig. 10 presents the estimation error defined as the difference between the true offset value and the estimated one at the output of the Comb-filter. It can be noticed that the desired accuracy 10−6 for the estimated value is reached after 10 clock cycles ((M × N)/fs ). For the other modes, the lower targeted accuracy are also achieved with 10 clock cycles due to the very selective bandwidth of the Comb-filter for high decimation factor N = 52 and N = 96. Fig. 7 (b) shows the PSD of the output signal after the compensation of the offset on each channel. It can be noticed a decrease of the spurious tones amplitude until the level of the quantization noise allowing to regain the expected SNDR.
signal of each modulator. Regarding the estimation phase, it is essential to know the required accuracy on the estimated value. For this purpose, Fig. 8 shows the SNDR at the output while subtracting the offset O value with a relative error ε: (O × (1 + ε)). It can be noticed that the SNDR evolves linearly with respect to the precision before reaching saturation until the spurious tone amplitude decreases to reach the quantization noise level. According to this result, there is a linear relationship between the required accuracy for the estimated value and the expected SNDR. It is given by: estimation precision = 10−k = 10
− SNDR+26 20
(7)
As a result, a high theoretical SNDR (high interpolation rate) requires more accuracy for the estimation of the offset values. For the example considered in this paper, the required accuracy to achieve the expected SNDR is 10−6 . f 50
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5 0
−100 0
−50 −300
−400 −100
Magnitude (dB)
PSD (dB)
−200
−500 −150 −600
−200
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
−700 0.5
f Fig. 9. PSD at the output of the modulator and frequency response of the Comb-filter with K = 6 and N = 32.
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Amplitude
(a) 0.05 0 −0.05
0
2000
4000
6000
8000
10000
12000
14000
16000
Amplitude
(b) 0.02 0
Fig. 12. Block diagram of the gain calibration method.
−0.02 2
4
6
8
Amplitude
1
10
12
14
16
18
14000
16000
(c)
−5
x 10
0 −1
2000
4000
6000
8000 n
10000
12000
Fig. 10. Estimation error (a), zoom in the interval time 0 ≤ n ≤ 18 (b), zoom in the interval time 10 ≤ n ≤ 16000 (c).
4.2. Gain equalization The multiplication of the output signal of each channel by a gain gi is equivalent, due to the digital multiplexer at the output, to multiplying the useful signal at the output of the TI ADC by a periodic signal of period M formed by the different gains gi (Fig. 1). This multiplication results in a convolution between the spectrum of the useful signal and the spectrum of the periodic signal. The fs latter spectrum is composed of tones located at frequencies k M (k an integer) whose magnitude is given by the discrete Fourrier series of the periodic signal. This convolution produces images of the spectrum of the useful signal weighted by the tone magnitudes [18]. Fig. 11 (a) shows the PSD at the output of the TI ADC where the following gains [1.0113, 1.0146, 1.0029, 0.9884] are present on all channels. It can be noticed that a 1% of gain mismatch leads to a 36 dB decrease of the desired SNDR. It is therefore essential
to equalize the channel gain mismatch to maintain the expected performances. The gain calibration method proposed in this paper supposes that the correction of the offset on each channel was already performed and then aims to equalize the gain on all channels to the gain of one of them considered as the reference channel. The block diagram of this method is depicted in Fig. 12 where the first channel is considered as the reference channel. The different steps of this method are: • The input signal is a constant signal applied to all modulators simultaneously. The magnitude of this signal Vin is fixed, without V any loss of generality, to 2R where VR is the reference voltage. Any other values in the input dynamic range of the modulator can be used. • The output signal of the ith modulator is composed of the constant input signal Vin multiplied by the gain gi and the quantization noise shaped by the modulator. The Comb-filter H(z) extracts the useful signal value Vin × gi on each channel with the same accuracy for offset estimation (Section 4.1). • The Least Mean Square (LMS) algorithm calculates the weight value wi to equalize the gain of the ith channel to that of the reference channel (channel 1 in Fig. 12): gi × wi = g1 |i=2...M
(8)
The LMS algorithm and its varieties (SD-LMS Sign-Data LMS, SELMS Sign-Error LMS, SS-LMS Sign data Sign Error LMS) have been chosen for their implementation simplicity compared to other
Before correction 0
SNR=40 dB
Spurious tone
Useful signal
PSD (dB)
−50 −100 −150 −200 −250
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
After correction 0
Useful signal
PSD (dB)
−50
SNR=76.6 dB
Spurious tone
−100 −150 −200 −250
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
f Fig. 11. PSD at the TI output before and after correction in the presence of gain mismatch.
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Table 2 Optimal parameters and computing resources for all types of the LMS algorithm. Algorithm
Multiplications
Additions
Convergence time
LMS
1
1
2
Ct = 35 fN
SD-LMS
1
0
2
Ct = 15 fN
SE-LMS
1 216
1(shift)
2
Ct = 780 f
SS-LMS
1 216
0
2
Ct = 1550 fN
1 μ=0.1 μ=0.2
0.9995
μ=0.3
op
0.999
μ=0.4
op
N
op
μ=0.5
2
0.9985
μ=0.6
w
op
μ=0.7
0.998
estimation algorithms. The estimation of wi using these algorithms is given by: LMS: ˆ i [n + 1] = w ˆ i [n] + (y1 [n] − yi [n]) × yi [n] w
(9)
SD-LMS:
μ=0.8 0.9975
(10)
SE-LMS: ˆ i [n + 1] = w ˆ i [n] + sgn [(y1 [n] − yi [n])] × yi [n] w
(11)
μ=1
0.997
0.9965
ˆ i [n + 1] = w ˆ i [n] + (y1 [n] − yi [n]) × sgn [yi [n]] w
μ=0.9
0
20
40
60
80
100
n Fig. 14. Estimation of the weight w2 with the SD-LMS algorithm for different values of .
SS-LMS: ˆ i [n + 1] = w ˆ i [n] + sgn [(y1 [n] − yi [n])] × sgn [yi [n]] w
(12)
where is the step of the algorithm. The performances of these algorithms will be summarized in Table 2 at the end of this section. In the following, only simulation results with the SD-LMS algorithm will be presented. Before evaluating the performance of the LMS algorithm, it is important to know the required accuracy for the weight values wi to ensure a good calibration of the gain mismatch. Fig. 13 presents the SNDR after the gain calibration with respect to the relative error ε introduced on the theoretical value of the weights wi : (wi × (1 + ε)). It can be noticed that, with the same reasoning as for the offset estimation values, there is a linear relationship between the required accuracy for the weight values and the SNDR. It is given by: Weight precision = 10−k = 10
− SNDR−5 19
(13)
10−4
For example, an accuracy of is required to regain the targeted SNDR (76 dB) for the third mode. The step of the LMS algorithm controls the convergence time and the accuracy for the estimated weights. Fig. 14 shows the estimated weight w2 at each iteration n using the SD-LMS algorithm for
Fig. 13. SNDR at the output of the TI with respect to the relative error ε on the weight values.
Fig. 15. Maximum estimation error of the weight w2 with respect to .
Fig. 16. The estimation of the weights using SD-LMS algorithme with = 1.
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Before correction 0
Spurious tones (offset)
Spurious tones (gain)
SNDR=39.4 dB
PSD (dB)
−50 −100 −150 −200
0
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0.1
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0.3
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0.5
After correction 0
PSD (dB)
Spurious tones (gain)
Spurious tones (offset)
−50
SNDR=76.4 dB
−100 −150 −200 −250
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
f Fig. 17. PSD at the TI output before and after correction in the presence of gain and offset mismatch simultaneously.
different values of and Fig. 15 shows the maximum estimation error once the convergence is achieved with respect to . It can be noticed that the value = 1 ensures the shortest convergence time with the best accuracy (6.6 × 10−6 compared to the desired accuracy 10−4 ). Moreover, this value simplifies the implementation of this algorithm by removing the multiplication operation. Fig. 16 shows the estimated weights with the SD-LMS algorithm with the step = 1. In these conditions, the convergence of the algorithm to the desired weight values is reached after 10 clock cycles. Fig. 11 (b) shows the he PSD at the output after applying the calibration algorithm for 15 clock cycles. As a result, there is a decrease of the amplitude of spurious tones to the level of quantization noise thus regaining the expected SNDR. In order to consider a real example, gain and offset are considered simultaneously in the basic example with values given by the following vectors: O = [−0.202, 0.717, 0.765, 0.1832] × 10−4 and g = [1.0113, 1.0146, 1.0029, 0.9884] The offset cancellation is applied first and then the gain equalization algorithm is applied taking into account the residual offset mismatch remaining after the offset cancellation. Fig. 17 shows the PSD at the output before and after calibration. It can be noticed that the gain equalization algorithm regains the expected performance even in the presence of weak offset mismatch. The total run time calibration is 25 clock cycles. Table 2 summarizes the optimal step and the convergence time for the four types of the LMS algorithm. The SE-LMS and SS-LMS present the easiest implementation way and the least hardware complexity. However, they present the largest convergence time. The SD-LMS is the best tradeoff between convergence time and implementation complexity.
5. Digital part implementation The two main blocks of the digital part are the Comb-filter and the correction filter. According to Eq. 4, Comb-filter can be efficiently implemented using the recursive architecture as shown in Fig. 18. To avoid overflow, the integration part requires register lengths of:
Bin + K × log 2(N)
(14)
where Bin is the input word length. However, the recursive architecture does not have the optimal power consumption when the filter order and the decimation ratio are high [19]. An alternative non-recursive structure could be used to overcome this drawback but the decimation ratio must be a power of 2 [19] which is not the case for all modes in our designed circuit. According to formula 14, the output signal at the last integrator must be quantized with 38 and 22 bits for the 6th and 3rd order Comb-filter respectively. On the other hand, due to the several differentiator stages, the amplitude of the output signal will decrease. This means that rounding may be applied at the output of the last differentiator to delete the extra Least significant bits (LSB). Fig. 19 shows the SNDR computed at the output of 6th order Comb-filter (modes 2 and 3) with respect to the number of deleted LSB bits. It is clearly shown that a deletion of 15 LSB bits doesn’t degrades the targeted SNDR. In the same manner, it was verified by simulation that a deletion of 5 LSB bits doesn’t degrade the expected the desired SNDR for the first mode with 3rd order Comb-filter.
Fig. 18. Recursive Comb-filter architecture.
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120
SNDR (dB)
100 80 60 40 20 30 30
20 20 10
10
Nbit2
0
0
Nbit1
Fig. 21. SNDR with respect to the number of deleted low bits Nbit1 and Nbit2 . Fig. 19. SNDR at the 6th order Comb-filter output respect to the number of deleted low bits.
As well as for the correction filter, it can be implemented in an optimal way using coefficients symmetry as shown in Fig. 20 (Vm is the maximum coefficient value). We have verified by simulation that coefficient values must be quantized with 8 bits resolution to maintain the expected SNDR of the TI ADC. To optimize the silicon area, a rounding is applied after each multiplication to keep the useful most significant bits and delete the other LSB bits ( Nbit i ). Fig. 21 shows the
Table 3 Computing digital reconstruction resources and implementation results. Entity
Order
Comb filter (mode 1) Comb filter (mode 1/2) Correction filter (mode 1) Correction filter (mode 2) Correction filter (mode 3)
3 6 14 10 10
fop 26 MHz 208 MHz 270 KHz 8 MHZ 55 MHz
Gates number
Area
434 4 × 3399 1612 1666 2119
0.00367 4 × 0.0165 0.013 0.014 0.0184
i=1,2
SNDR at TI ADC output when varying Nbit1 and Nbit2 separately. It can be noticed that the sum of deleted bit number Nbit1 + Nbit2 is almost constant while maintaining the expected
SNDR. The combination with the largest Nbit1 value has been chosen because the number of multiplication before the accumulator is higher than the number of multiplication after the accumulator.
Fig. 20. Correction filter F(z) implementation architecture.
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Table 3 summarizes the synthesis results of each component in a 1.2 V, 65 nm CMOS process using VHDL language. The estimated silicon area is 0.115 mm2 . 6. Conclusion Theoretically and also in the system-level’s point of view, TI is a promising solution for wide band conversion. The performance of the converter depends on four parameters, the number of channels, the interpolation rate, the order of the modulator and the filter complexity. Thus, there is an additional freedom degree compared to traditional ADC. However, their implementation and their performance remains limited due to various sources of imperfection. This paper has proposed a novel solution for the digital reconstruction and for gain and offset calibration in TI ADC. The proposed solution is based on the use of a Comb-filter after each modulator. Comb-filters ensure a good reconstruction of the useful signal with much lower computing resources than that using optimal filters. Moreover, Comb-filters are used in the gain and offset calibration process. The proposed calibration method has a very short calibration time estimated of 10 clock cycles for offset and gain calibration. This method could be used also with other parallel ADC architecture as the Parallel Sigma Delta () using Hadamard modulation. Implemented in a 1.2 V, 65 nm CMOS, the total die area is estimated to 0.115 mm2 . The proposed calibration method facilitates the adaptation of time interleaved architecture to achieve high performances ADC. However, there are a lot of challenges and difficulties to implement such a converter. Here are some of them: • Interpolation at the input of the S. modulator is always needed even with Nyquist solution i.e. N = M. In fact, it re-samples the input signal at very high rate, therefore all modulators work at the much higher rate than fs , unlike traditional TI ADCs. Even when a Nyquist solution is envisaged, all modulators work at the “full rate” fs . In another word, the main advantage of traditional TI ADC namely the reduced rate of individual ADC disappears. • Implementation of the interpolation function is a very challenging task. • Dynamic channel mismatch is much more difficult and more expensive to calibrate, especially at high rate. • Clock skew needs to be reduced or correction technique is required even when a full rate sample/hold circuit is used at the frond-end of the ADC. Acknowledgement This research work was supported by the French Research Agency in the frame of project Versanum ANR-05-RNRT-010-01. References [1] Mitola J, Zvonar Z. Software radio technologies: selected readings. Wiley-IEEE Press; 2001. [2] Mitola III J, Maguire Jr G. Cogniive radio: making software radios more personal. IEEE Pers Commun 1999;6:13–8. [3] Benabes P, Beydoun A, Oksman J. Extended frequency-band-decomposition sigma-delta A/D converter. In: Analog integrated circuits and signal processing. 2009. [4] Galton I, Jensen HT. Delta-sigma modulator based A/D conversion without oversampling. IEEE Trans Circuit Syst II 1995 December;42:773–84. [5] Eshraghi A. High-speed parallel delta-sigma analog-to-digital converters. PhD Thesis, Washington State University; 1999 May. [6] Nguyen V, Loumeau P, Naviner J. Analysis of time-interleaved delta-sigma analog to digital converter. IEEE Vehicular Technol Conf 2002;4:1594–7. [7] Versanum project. French Research Agency ANR-05-RNRT-010-01.
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[8] Beydoun A, Jabbour C, Fakhoury H, Nguyen VT, Naviner L, Loumeau P. A 65 nm CMOS versatile ADC using time interleaving and modulation for multimode receiver. In: IEEE, NEWCAS-TAISA. 2009. [9] Naviner L, Naviner B, de Barros J. Programmable digital channel selector for multimode radio receiver. In: Signal processing and information technology, 2004. Proceedings of the fourth IEEE international symposium on. 2004. p. 5–8. [10] Eshraghi A, Fiez T. A time-interleaved parallel A/D converter. IEEE Trans Circuit Syst II March 2003;50:118–29. [11] Norsworthy S, Schreier R, Temes G. Delta-sigma data converters, theory, design and simulation. NJ: IEEE Press; 1997. [12] Batten R, Eshraghi A, Fiez T. Calibation of parallel ADCs. IEEE Trans Circuits Syst II 2002;49:390–9. [13] Eklund J, Gustafsson F. Digital offset compensation of time-interleaved ADC using randomchopper sampling. In: Proceedings of the 2000 IEEE international symposium on circuits and systems. ISCAS 2000, Geneva. 2000. [14] Ferragina V, Fornasari A, Gatti U, Malcovati P, Maloberti F. Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators. IEEE Trans Circuits Syst I: Regul Pap 2004;51:2365–73. [15] Eshraghi A, Fiez T. A comparative analysis of parallel delta-sigma adc architectures. IEEE Trans Circuit Syst I 2004 March;51:450–8. [16] Beydoun A, Nguyen VT, Loumeau P. Correction des dfauts analogiques dans des convertisseurs analogiques/numriques parallles, notamment pour des applications multistandars, radio logicielle et/ou radio-cognitive. Patent, Number Fr 09-55351; July 2009. [17] Beydoun A, Nguyen VT, Loumeau P. A novel digital calibration technique for gain and offset mismatch in parallel TI ADCs. Dallas, Texas: IEEE, ICASSP; 2010. [18] Petraglia A, Mitra S.IEEE transactions on analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer. Instrumentation and measurement, vol. 40. 1991. p. 831–5. [19] Gao Y, Jia L, Isoaho J, Tenhunen H. A comparison design of Comb decimators for sigma-delta analog-to-digital converters. Analog Integrated Circuits Signal Process 2000;22:51–60. Ali Beydoun was born in Beirut, Lebanon, in 1980. He received a B.S. in Electronics from the University of Lebanon in 2002, an Engineering Degree in Telecommunications from the ENSIETA school, Brest, France, in 2004 and a Ph.D in Electronics from Paris XI university in 2007. From 2007 to 2009, he was a research assistant at the Institut Telecom - ParisTech. Since October 2009, he is assistant professor at the Lebanese university. His research focuses on the development of advanced RF architecture for software and cognitive radio applications and spectrum sensing algorithms. Van Tam Nguyen received the Diplme d’Ingnieur from Ecole Suprieure d’Electricit (Supelec - www.supelec.fr) and a M.Sc. degree in automatic and signal processing from University Paris Sud (www.u-psud.fr) in 2000, and a Ph.D. degree in Communications and Electronic from Ecole Nationnale Suprieure des Tlcommunications (Telecom ParisTech- www.telecom-paristech.fr) in 2004. From 2000 to 2005 he was research engineer at Schlumberger and Telecom ParisTech working mainly on European Project SPRING (Scientific Multidisciplinary Network for metering - IST1999-12342). In 2005 he joined Telecom ParisTech as an Associate Professor. His main research interests are in the areas of cognitive radio network, software defined radio, sensor network, wireless communication system and network. In particular, his research focuses on reconfigurable radio interface, flexible radio frequency front-end, digital/analog/radio frequency partioning, mixed signal interference cancellation, sensing algorithm for cognitive radio, algorithms for MIMO spectrum sensing, cooperation sensing with reduced delay in relaying decisions, digital oriented architecture for SoC sensor and routing algorithms in wireless sensor network for power saving. Lirida Alves de Barros Naviner received the Electrical Engineering and the M.S. degrees from the Federal University of Paraiba (UFPB-Brazil, 1988 and 1990), the Ph.D degree from the Ecole Nationale Suprieure des Tlcommunications (ENSTFrance, 1994) and the HDR degree from the University Pierre et Marie Curie (UPMC-France, 2006). She joined the team of UFPB in 1994, where she was a faculty member in the Electrical Engineering and the Computation Science Departments. Since 1998 she works at Telecom ParisTech where she is a professor in the Department Electronics and Communications. Her research interests include evolvable hardware, reconfigurable and reliable circuits, algorithms and architectures for telecommunications. This relates to applications with severe constraints of computation power and flexibility. She has a large experience on algorithm-architecture codesign of hardware IP and her actual research focuses on design for reliability. [Dr. Lirida Naviner has published more than hundred papers and has supervised several works in these and related areas]. Dr. Lirida Naviner is IEEE Senior Member and she is member of the reviewing committee of many international conferences and journals. Patrick Loumeau received the engineer degree in 1982 from the Institut National des Telecommunications in Paris, France. He received the authorization to manage research diploma in 2000. He joined the Ecole Nationale Superieure des Telecommunications of Paris in 1982. He is Professor in the Analog and Mixed IC Design group, Communications and Electronics Department. He is in charge of research on analog and mixed IC for telecommunications. He has realized a number of research and development project with industry, national research center and universities. He has co-authored more than 50 technical publications in international congress and revues. He is a member of IEEE Solid State Circuits Society, and Circuits and Systems Society.
Please cite this article in press as: Beydoun A, et al. Optimal digital reconstruction and calibration for multichannel Time Interleaved ADC based on Comb-filters. Int J Electron Commun (AEÜ) (2012), http://dx.doi.org/10.1016/j.aeue.2012.10.004