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FPGA realization of multi-scroll chaotic oscillators
Accepted Manuscript FPGA Realization of Multi-Scroll Chaotic Oscillators E. Tlelo-Cuautle, J.J. Rangel-Magdaleno, A.D. Pano-Azucena, P.J. ObesoRodelo, J.C. Nunez-Perez PII: DOI: Reference:
S1007-5704(15)00087-8 http://dx.doi.org/10.1016/j.cnsns.2015.03.003 CNSNS 3498
To appear in:
Communications in Nonlinear Science and Numerical Simulation
Please cite this article as: Tlelo-Cuautle, E., Rangel-Magdaleno, J.J., Pano-Azucena, A.D., Obeso-Rodelo, P.J., Nunez-Perez, J.C., FPGA Realization of Multi-Scroll Chaotic Oscillators, Communications in Nonlinear Science and Numerical Simulation (2015), doi: http://dx.doi.org/10.1016/j.cnsns.2015.03.003
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FPGA Realization of Multi-Scroll Chaotic Oscillators E. Tlelo-Cuautle, J.J. Rangel-Magdaleno, A.D. Pano-Azucena1 INAOE, Mexico
P.J. Obeso-Rodelo, J.C. Nunez-Perez2 CITEDI-IPN, Mexico
Abstract Chaotic oscillators have been realized using field-programmable gate arrays (FPGAs) showing good results. However, only 2-scrolls have been observed experimentally, and all reported works use commercially-available software tools for FPGA synthesis. In this manner, as a first contribution we show the FPGA realization of two multi-scroll chaotic oscillators that are characterized by their maximum Lyapunov exponent (MLE) for generating from 2- to 6-scrolls. The first multi-scroll chaotic oscillator is based on saturated function series and the second on Chua’s circuit. As a second contribution, we show their hardware realization by applying two numerical methods: Forward Euler (FE) and Runge Kutta (RK). The advantage of realizing those multi-scroll chaotic oscillators is that one can avoid the use of multiplier entities, thus optimizing FPGA resources and increasing the processing speed, as we show by realizing single constant multiplication (SCM) blocks. The experiments are verified by performing co-simulation for an FPGA Spartan 3 of Xilinx. Finally, experimental results are shown for different values of MLE (already optimized) for both multi-scroll chaotic oscillators, and the FPGA used resources are listed for generating 6-scrolls when applying FE and RK. Keywords: FPGA, Chaos, Multi-scroll, Computer arithmetic, VHDL, 1 Email: 2 Email:
[email protected]. [email protected].
Preprint submitted to Journal of LATEX Templates
March 10, 2015
maximum Lyapunov exponent, Chua’s circuit, saturated function series.
1. Introduction Chaotic oscillators have been investigated to guarantee chaotic regime by optimizing the maximum Lyapunov exponent (MLE) and ensuring a good distribution of trajectories in the phase-space portraits for generating multi-scroll 5
attractors [1]. Those optimized chaotic oscillators have been realized with different kinds of electronic devices, trying to generate the higher number of scrolls [2]. However, it has been observed the difficulty of programming different values for the parameters involved in the mathematical model of a chaotic oscillator. For example: in [1] the MLE of two multi-scroll chaotic oscillators is optimized;
10
one based on saturated function series and the other on Chua’s circuit. Both chaotic oscillators can have different values of their coefficients as well as their piecewise-linear (PWL) function can change, so that one needs to use precision circuit elements to tune the desired value for the coefficient or PWL function, but the major problem is when tuning values having more than three decimals, i.e.
15
< 0.001. Because precision resistors are used to tune those decimal values, and since they have very high variation, then we appeal using field-programmable gate arrays (FPGAs) to program coefficient parameters and PWL functions having three or more decimals. FPGAs have been used to realize applications on chaotic systems. For ex-
20
ample: in [3] a chaotic map with high MLE is implemented into an FPGA, in [4] an FPGA-based 3D chaotic system is realized by an auto-switched numerical resolution of multiple three dimensional continuous chaotic systems, in [5] an FPGA-realization of a self-synchronizing chaotic decoder in the presence of noise is presented, in [6] the FPGA design for a pseudo-random number gener-
25
ator is given, in [7] other FPGA design for a discrete chaotic map is presented, and more recently: in [8] an implementation of an FPGA-based real time novel chaotic oscillator is introduced. Although the MLE and phase portraits are shown, they are not optimized; only 2-scrolls are generated, and the hardware
2
architecture from VHDL (Very High Speed Integrated Circuit Hardware De30
scription Language) simulations is not described. In this manner, this article shows the FPGA realization of two multi-scroll chaotic oscillators having optimal and different MLEs: one based on saturated function series and the other based on Chua’s circuit. In addition, their FPGA realization is described by applying two numerical methods (Forward Euler and Runge Kutta) for solving
35
their models given by three first-order differential equations. We show their hardware description, the computer arithmetic, and their co-simulation for a low-cost FPGA from Xilinx. Both chaotic oscillators are realized for generating from 2- to 6-scrolls. At the end, we show several experimental results for different MLEs, and the FPGA used resources are listed for generating 6-scrolls
40
when applying both numerical methods.
2. Multi-scroll chaotic oscillators In [1], two multi-scroll chaotic oscillators are described: one based on saturated function series and the second on Chua’s circuit. They are optimized by maximizing their MLE and minimizing the dispersions of their trajectories in 45
the phase portraits among all scrolls in an attractor. 2.1. Chaotic oscillator based on saturated function series This multi-scroll chaotic oscillator is described by three differential equations, as given by (1), where a, b, c, and d1 are positive constants that can have values in the interval [0, 1]. The dynamical system is controlled by a PWL
50
approximation that describes the saturated function series f , which is obtained as follows: Let f0 be the saturated function described by (2), where: 1/m is the slope of the middle segment and m > 0; the upper radial {f0 (x; m) = 1 |x > m}, and the lower radial {f0 (x; m) = −1 |x < −m} are called saturated plateaus, and the segment {f0 (x; m) = x/m | |x| ≤ m} between the two saturated plateaus is
3
55
the saturated slope. x˙ = y (1)
y˙ = z z˙ = −ax − by − cz + d1 f (x; m) 1, f0 (x; m) =
if x > m
x if |x| ≤ m m, −1, if x < −m,
(2)
The saturated functions described by fh and f−h can be defined as: 2, fh (x; m, h) =
if x > h + m
x−h m , if |x − h| ≤ m 0, if x < h − m,
and f−h (x; m, −h) =
0,
(3)
if x > h + m
x−h m , if |x − h| ≤ m −2, if x < h − m,
(4)
where h is the saturated delay, and h > m. Therefore, the saturated function 60
series for generating s scrolls can be defined by (5) [1], for s > 2.
f (x; m) =
s−2 ∑
f2i−s+2 (x; m, 2i − s + 2)
(5)
i=0
2.2. Chaotic oscillator based on Chua’s diode The multi-scroll chaotic oscillator based on Chua’s circuit is described by (6) [1], where α and β are positive and real constants, and g(x) is the PWL function known as Chua’s diode and defined by (7), where mi are negative slopes. The 65
constants bi are real numbers and are associated to break point values. For
4
generating an even number (2n) of scrolls, q takes values q = 1, 2, 3, . . . , and for generating an odd number (2n + 1) of scrolls, q = 2, 3, 4, . . . . x˙ = α[y − x − g(x)], y˙ = x − y + z,
(6)
z˙ = −βy, g(x) = m2n−1 x +
2n−1 1 ∑ (mi−1 − mi )(|x + bi | − |x − bi |), 2 i=q
(7)
2.3. Optimized multi-scroll chaotic oscillators Reference [2] shows the experimental realization of multi-scroll chaotic os70
cillators based on saturated function series. In that cases the PWL function is modified and the coefficients are set to a=b=c=d1 =0.7, but the MLE is low. Therefore, the work in [1] is used herein to maximize MLE by varying a, b, c, and d1 with four decimals, i.e. between [0.0001..1.0000]. The resulting PWL function, optimized coefficients, and their associated MLE are listed in Table 1. Table 1: Optimized values for the oscillator based on saturated function series. Scrolls
2
3
5
6
75
Variable values slope x/m
break points (x − h)/m
60.60606
-0.0165, 0.0165
60.60606
60.60606
60.60606
MLE
coefficient (a, b, c, d1 ) 1.0000, 1.0000, 0.4997, 1.0000
0.3761
1.0000, 0.7000, 0.7000, 0.2542
0.3425
0.7000, 0.7000, 0.7000, 0.7000
0.2658
0.9097, 10000, 0.2632, 0.9946
0.4574
0.7002, 1.0000, 0.1858, 1.0000
0.3802
0.8224, 0.7317, 0.6642, 1.0000
0.3132
1.0000, 0.7250, 0.2250, 1.0000
0.6919
-0.5±0.165, 0.5±0.165
0.9890, 0.6810, 0.2040, 0.9790
0.6645
-1.5±0.165, 1.5±0.165
1.0000, 0.7330, 0.2050, 1.0000
0.6471
-0.0165, 0.0165
1.0000, 0.6750, 0.2100, 1.0000
0.7200
-1±0.165, 1±0.165
1.0000, 0.7530, 0.1740, 1.0000
0.6758
-2±0.165, 2±0.165
0.9670, 0.8230, 0.3380, 0.9550
0.5630
-0.5±0.165, 0.5±0.165
For the multi-scroll chaotic oscillator based on Chua’s circuit, the MLE optimization has also been performed in [1] by varying the PWL function and 5
the coefficient values. The negative slopes of the PWL function associated to Chua’s diode are different for generating even and odd number of scrolls as well as their break points, and the coefficients are also varied, resulting in the values 80
listed in Table 2. The optimized values listed in Tables 1 and 2 are used in the following sections to describe the FPGA realization of both multi-scroll chaotic oscillators by applying two numerical methods: Forward Euler and 4th order Runge Kutta. Table 2: Optimized values for the oscillator based on Chua’s circuit [1]. Scrolls
2
3
4
5
6
Variable values
MLE
slopes m0 (or m2 ), m1
break points
coef. (α, β)
-3.036, -0.276
0.1
10, 15
0.21256
-1.131, -0.395
2.618
11.991, 14.997
0.525590
-3.036, -0.276
0.8
10, 15
0.21121
-0.385, -0.234
2.394
10.297, 12.565
0.43266
-3.036 -0.276
0.1, 0.66, 0.86
10, 15
0.16851
-3.981 -0.397
0.101, 1.206, 1.467
11.489, 14.674
0.49122
-3.036, -0.276
0.8, 1.37, 2.97, 3.54
10, 15
0.22363
-2.813, -0.356
0.893, 1.559, 3.432, 4.114
10.227, 11.786
0.58500
-3.036, -0.276
0.10, 0.66, 0.86, 1.42, 1.62
10, 15
0.12587
-1.464, -0.381
0.19, 0.70, 1.58, 2.21, 3.31
10.556, 11.415
0.43326
3. Hardware realization 85
The multi-scroll chaotic oscillators described by (1) and (6) are simulated herein by applying two numerical integration methods: Forward Euler (FE) and 4th-order Runge Kutta (RK). Those dynamical systems in (1) and (6) are associated to solve an initial value problem of the form:
x˙ = f (x)
(8)
The solution of (8) depends on initial conditions xo , and f (x) includes the 90
PWL functions described by (5) and (7). The following subsections show the hardware realization of FE and RK into an FPGA for both chaotic oscillators. 6
3.1. Hardware realization of FE This numerical integration method is based on the iterative formula:
ji+1 = ji + ∆tf (ji )
(9)
where ∆t is the time-step and f (j) is taken from (8). The discretization of (1) 95
by applying (9), leads us iterating the three state variables as follows: x(i + 1) = x(i) + ∆t ∗ (y(i)); y(i + 1) = y(i) + ∆t ∗ (z(i));
(10)
z(i + 1) = z(i) + ∆t ∗ (−a ∗ x(i) − b ∗ y(i) − c ∗ z(i) + d ∗ f (x(i))); where the saturated function (5) becomes f (x(i)) that is embedded into z(i + 1) and has three values for generating 2-scrolls [2] (according to subsection 2.1). The hardware implementation of (10) is associated to VHDL programming, where it consists of adders, subtractors and multipliers. The FPGA realiza100
tion allows us proposing the length of bits being processed among the hardware blocks. For instance, according to computer arithmetic, we propose using 28bits fixed-point words, taking: 1 bit for the sign, 3 for the integer part, and 24 for the decimal part, as shown in Table 3. The VHDL entities for the adder and subtractor are easily implemented, and are shown in Fig. 1. However,
105
the multiplier entity consumes as many hardware resources as the word-length increases. Fortunately, in VHDL and for optimizing FPGA resources, a multiplication by a fixed-point constant can be realized without multipliers, just using adders, subtractors and shifts. This is a great advantage in realizing multi-scroll chaotic oscillators, as it is the case of (1) when multiplying by a, b, c and d1 ,
110
and of (6) when multiplying by α and β. In those cases, one can avoid the use of multipliers, as explained in the following. The multiplication block when one operator is a fixed-point constant can be implemented by a block called single constant multiplication (SCM) [9], which minimizes FPGA resources and increases the processing speed because it uses
7
Table 3: Distribution of the fixed-point 28-bits word.
Sign
Integer part
Decimal part
1 bit
3 bits
24 bits
0
000
.000000000000000000000000
Figure 1: 28-bits length adder and subtractor entities.
115
only adders, subtractors and shifts. As an example: One can see at3 that the multiplication of an input x by a constant 5 can be implemented by (11), indicating that the input x is shifted twice to the left and then x is added. In this case: if x=2, in binary it is 0010. Two shifts to the left gives 1000, and adding x it equals to: 1000+0010=1010. We use the tool introduced in [9] to
120
implement SCM and multiple constant multiplication (MCM) blocks with the minimum number of adders, subtractors and shifts. y = (x << 2) + x
(11)
In this article, the number x multiplying the constant is called in and the result out. Figure 2 shows the SCM implementation when the constant is 0.7, e.g. a = b = c = d1 =0.7 in [1], and 0.01. 125
As one sees, Fig. 2(a) requires 1 subtractor, 4 adders and 5 shift blocks; and Fig. 2(b) requires 1 subtractor, 2 adders and 4 shift blocks. From these diagrams one can generate VHDL code to create the multiplier entity shown in Fig. 3. Equations x(i + 1) and y(i + 1) in (10) can be implemented directly as shown
130
in Fig. 4, where Xini, Y ini represent the initial conditions and Xout, Y out the output values of the state variables x, y, respectively. 3 http://www.spiral.net/hardware/multless.html
8
Figure 2: SCM for a constant of: (a) 0.7, and (b) 0.01.
Figure 3: 28-bits length multiplier entity.
Figure 4: Block diagrams for implementing x(i + 1) and y(i + 1) from (10).
Equation z(i+1) from (10) is quite complex, because it embeds the saturated function series. Its implementation requires adders, subtractors and SCMs for the coefficients a, b, c, d1 , the value of the slope m, the saturation levels and the 135
step-size ∆t, which are constants. In addition, to generate the PWL functions 9
f (x) in (1) and g(x) in (6), comparator blocks are needed depending on the number of linear segments to generate from 2- to 6-scrolls. For instance, z(i + 1) from (10) is implemented as shown in Fig. 5, where Xini, Y ini, Zini are the initial conditions, and Zout the state variable output.
Figure 5: Block diagram for implementing z(i + 1) from (10).
140
The diagrams shown in Figs. 4 and 5 can be described by an entity called chaotic oscillator unit, as shown in Fig. 6, where Xini, Y ini, Zini are the initial conditions of 28-bits, also one can see the clock signal, reset, and the outputs associated to the three state variables. Now, one can realize the chaotic oscillator by adding a feedback loop with
145
the help of a multiplexer that will control the iterations and provide the initial conditions to the chaotic oscillator unit. The first iteration then will need 8 clock cycles that are managed by a counter embedded into the chaotic oscillator unit. The counter sends a logic signal after counting 8 through the pin Sel to the multiplexer. Afterwards, the feedback loop is activated to perform the required 10
Figure 6: Chaotic oscillator unit entity.
150
iterations. All this is performed at a second level of design composed of three entities, as shown in Fig. 7, where the registers entity holds the values of the state variables x(i), y(i), z(i). It waits some clock cycles until z(i) is available because it requires more evaluations than x(i), y(i), as appreciated in Fig 5.
Figure 7: Whole chaotic oscillator diagram executing FE.
Finally, Fig. 8 shows the top-level entity of the realization of (1) for gener155
ating 2-scrolls, and by applying the FE numerical method.
Figure 8: Top-level description of (1) when executing FE.
11
3.2. Hardware realization of RK The 4-th order RK numerical method is based on the iterative formula: ji+1 = ji + ∆tK4 (xi , ji ; ∆t)
(12)
where K4 (xi , ji ; ∆t) requires the evaluation of four constants given by, K4 (xi , ji ; ∆t) ,
1 (k1 + 2k2 + 2k3 + k4 ) 6 k1 , f (xi , ji )
∆t k1 , xi + 2 ∆t k3 , f [ji + k2 , xi + 2 k2 , f [ji +
∆t ] 2 ∆t ] 2
(13)
k4 , f [ji + ∆tk3 , xi + ∆t] where ∆t is the time-step and f (j) is taken from (8). 160
The hardware realization of RK can be performed also in a similar way than for implementing FE in the previous subsection. However, more hardware operations are required to implement (13). For instance, the MATLAB simulation by applying FE and RK with the same parameters is shown in Figs. 9 and 10. Although both numerical methods behave quite similar, their FPGA realization
165
is quite different, as shown in the following sections.
Figure 9: MATLAB simulation of (1) by executing FE.
12
Figure 10: MATLAB simulation of (1) by executing RK.
The multi-scroll chaotic oscillator based on Chua’s circuit can be realized in a similar way. However, when generating more than 2-scrolls, the PWL functions increase and one should consider the values of the coefficients and functions listed in Tables 1 and 2.
170
4. Co-Simulation results in Active-MATLAB The co-simulation helps to verify the hardware implementation before its physical realization and one can have access to each signal. In this article, the compilation of the chaotic oscillator described by VHDL code is performed by using Active-HDL, which provides an interface for MATLAB-Simulink, and
175
allows to perform the co-simulation of blocks that can be described by mathematical models or VHDL. Active-MATLAB generates a file *.m for each entity or component described by VHDL, and herein it generates a file associated to the top-level description (see Fig. 8). Within Simulink one can integrate blocks from Active, as shown in Fig. 11, where a pulse generator is used for the CLOCK
180
signal at 10 kHz, for the RESET signal a constant is used with a logic value of 1. An scope is used to visualize the signals, and the blocks To workspace capture the data and save them in arrays. We used a time simulation of 3×106 seconds. Figure 12 shows the co-simulation of (1) described in Active by VHDL code by
13
applying FE and showing 6-scrolls.
Figure 11: Active-HDL co-simulation schematic.
185
In a similar manner, by applying RK we used the VHDL code previously generated for the entities adder, subtractor, multiplier, multiplexer, counter and register. Figure 13 shows the co-simulation of (1) described in Active by VHDL code by applying RK and showing 6-scrolls. One can appreciate the good agreement of Figs. 12 and 13 with those from
190
MATLAB simulations (Figs. 9 and 10). Therefore, we proceed to synthesize the VHDL code into an FPGA.
Figure 12: Co-simulation of (1) implemented by applying FE.
14
Figure 13: Co-simulation of (1) implemented by applying RK.
5. Experimental results In the experiments we used the low-cost XC3S1000-5FT256 FPGA Spartan3 from Xilinx. The initial conditions were set to: x(0) = 0.1, y(0) = 0.1 and 195
z(0) = 0. Compared to using electronic devices, as done in [2], the use of an FPGA allows us to program the coefficient values with several decimals, in this work 3 and 4 decimals were used, as listed in Tables 1 and 2. In addition, the generated attractors that are shown in the following subsections are more stable when using FPGAs than those using active devices with precision resistors for
200
tuning the coefficient values of the chaotic oscillators. 5.1. FPGA realization of the oscillator based on saturated function series The FPGA realization of the multi-scroll chaotic oscillator based on saturated function series generates from 2- to 6-scrolls. Figure 14 shows the phase portraits for generating 2, 3, 5 and 6-scrolls and plotting the state variables
205
x − z in the oscilloscope. We selected also the experimental results for the state variable x, because one can appreciate the equal number of equilibrium points: 2, 3, 5, and 6. Figure 14 shows the results by applying FE and for the lowest value of MLE from Table 1, i.e. for each number of scrolls, the right part of the Table shows
15
Figure 14: FPGA generation of: 2-, 3-, 5-, and 6-scrolls phase portraits x − z (left), and state variables x (right) by applying FE and for the lowest value of MLE from Table 1.
210
3 values of the MLE, then the lowest value is plotted. One can appreciate the good generation of the desired number of scrolls. Figure 15 shows the phase portraits for generating also 2, 3, 5 and 6-scrolls and plotting the state variables x − z in the oscilloscope, but now by applying RK. Again, we selected the experimental results for the state variable x, and for
215
the lowest value of MLE from Table 1. One can see a little difference between Figs. 14 and 15, but the main difference is the FPGA resources used for each numerical method, which are listed in subsection 5.3. Figure 16 shows the phase portraits for generating 2, 3, 5 and 6-scrolls and
16
Figure 15: FPGA generation of: 2-, 3-, 5-, and 6-scrolls phase portraits x − z (left), and state variables x (right) by applying RK and for the lowest value of MLE from Table 1.
plotting the state variables x − z in the oscilloscope, but now when selecting the 220
values of the coefficients a, b, c, and d1 , to generate the highest value of MLE from Table 1. As one sees, these attractors are more complex than the ones shown in Figs. 14 and 15, this is because the MLE is higher than the others listed in Table 1 and then it guarantees better unpredictability of the dynamics of the chaotic oscillator [10].
225
5.2. FPGA realization of the oscillator based on Chua’s circuit The FPGA realization of the multi-scroll chaotic oscillator based on Chua’s circuit also generates from 2- to 6-scrolls. Figure 17 shows the phase portraits 17
Figure 16: FPGA generation of: 2-, 3-, 5-, and 6-scrolls phase portraits x − z for the highest value of MLE from Table 1.
for generating 2, 3, 5 and 6-scrolls and plotting the state variables x − z in the oscilloscope. In this Figure, the scrolls on the left column were generated using 230
the lowest value of MLE and the scrolls on the right column were generated using the highest values of MLE from Table 2, but by applying FE. The same procedure is performed by applying RK, and the experimental results are shown in Fig. 18. Once again, one can appreciate the good generation of the desired scrolls and they have better unpredictability as the value of the MLE increase,
235
as already known for chaotic systems [10]. 5.3. FPGA resources used for generating 6-scrolls by applying FE and RK As mentioned above, the experiments were realized by using the low cost XC3S1000-5FT256 FPGA Spartan-3 from Xilinx. The used resources are listed in the following Tables, where one can appreciate the difference between apply-
240
ing a simple numerical method like Forward Euler (FE) and a more elaborated one like the 4-th order Runge-Kutta (RK). The experimental results showed similar results for generating the desired number of scrolls, but the used resources are different for the oscillator based on saturated function series (Tables 4 and 5) and the one based on Chua’s circuit (Tables 6 and 7). For instance, as we
245
expected, and since RK is more accurate than FE, the FPGA logical resources 18
Figure 17: FPGA generation of: 2-, 3-, 5-, and 6-scrolls phase portraits x − y by applying FE and for the lowest value of MLE (left) and the highest value of MLE (right) from Table 2.
consumption doubles for both examples (saturated function series and Chua’s circuit). One can deduce it by comparing Tables 4 and 6, where both FPGA realizations are done by applying FE, and where one can appreciate a considerable increase in the use of resources. The same is observed by comparing Tables 250
5 and 7, where RK is applied. From the mathematical point of view, it is more recommended to use a more elaborated numerical method like RK instead of FE, because it is more stable and allows a step-size smaller than a the simple FE method. As one can infer, an important advantage of realizing chaotic oscillators
19
Figure 18: FPGA generation of: 2-, 3-, 5-, and 6-scrolls phase portraits x − y by applying RK and for the lowest value of MLE (left) and the highest value of MLE (right) from Table 2.
255
based on PWL functions, is that the more complex case (Table 7), was synthesizable in a low cost FPGA, even with available logic to perform other task. It is also worth mentioning that the use of SCM/MCM blocks is critical to achieve implementations on a low cost FPGA. Finally, it can be appreciated that the complexity of the algorithms is directly related to the maximum operating fre-
260
quency, which was: 70.943 MHz for Table 4, 69.500 MHz for Table 5, 58.648 MHz for Table 6, and 48.209 MHz for Table 7. These operating frequencies are much higher than when using electronic devices as in [2], thus showing that FPGA realizations are much better. In addition the operating frequencies in
20
these FPGA realizations can be increased when using high-performance chips, 265
i.e. higher cost FPGAs, where also the percentage of resource utilization will decrease. Table 4: FPGA mapping final report for generating 6-scrolls by using saturated functions series and by applying FE.
Resources
Used
Available
Utilization
Slice Registers
995
15,360
6%
Number of occupied Slices
1,681
7,680
21%
Number of 4 input LUTs
2,894
15,360
18%
Number of bonded IOBs
25
173
14%
Number of MULTI18X18s
18
24
75%
Number of BUFGMUXs
1
8
12%
Table 5: FPGA mapping final report for generating 6-scrolls by using saturated functions series and by applying RK.
Resources
Used
Available
Utilization
Slice Registers
1,891
15,360
12%
Number of occupied Slices
4,422
7,680
57%
Number of 4 input LUTs
8,149
15,360
53%
Number of bonded IOBs
25
173
14%
Number of MULTI18X18s
24
24
100%
Number of BUFGMUXs
1
8
12%
6. Conclusion It has been shown that by using FPGAs one can realize multi-scroll chaotic oscillators that have better behavior than by using active devices like operational 270
amplifiers. In this article the cases of study were two oscillators: one based on saturated function series and other based on Chua’s circuit. Both chaotic oscillators were realized with FPGAs for generating from 2- to 6-scrolls and characterized by their maximum Lyapunov exponent (MLE), which was optimized
21
Table 6: FPGA mapping final report for generating 6-scrolls by using Chua’s circuit and by applying FE.
Resources
Used
Available
Utilization
Slice Registers
1,477
15,360
9%
Number of occupied Slices
2,727
7,680
35%
Number of 4 input LUTs
4,967
15,360
32%
Number of bonded IOBs
24
173
13%
Number of MULTI18X18s
24
24
100%
Number of BUFGMUXs
1
8
12%
Table 7: FPGA mapping final report for generating 6-scrolls by using Chua’s circuit and by applying RK.
Resources
Used
Available
Utilization
Slice Registers
2,667
15,360
17%
Number of occupied Slices
5,347
7,680
69%
Number of 4 input LUTs
9,714
15,360
63%
Number of bonded IOBs
25
173
14%
Number of MULTI18X18s
24
24
100%
Number of BUFGMUXs
1
8
12%
to guarantee better unpredictability. The realizations were implemented at the 275
hardware level, showing that these kind of chaotic oscillators can reduce the use of multiplier entities by using single constant multiplication (SCM) blocks, which optimize the FPGA resources and increase the processing speed. The hardware implementation was performed by applying two numerical methods: Forward Euler (FE) and Runge Kutta (RK). A co-simulation using Matlab and Active-HDL
280
was performed before the physical synthesis into the FPGA to guarantee the generation of scrolls. Finally, the experimental results for both chaotic oscillators, and by implementing different values of the coefficients associated to different values of MLE for both chaotic oscillators, leads us to conclude on the suitability of FPGAs for realizing chaotic oscillators with multiple scrolls and
285
high MLE.
22
Acknowledgments This work is partially supported by CONACyT/Mexico under the projects: 237991 and 136056.
References 290
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G.
de
la
Fraga,
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Tlelo-Cuautle,
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(2014)
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[2] J. Munoz-Pacheco, E. Tlelo-Cuautle, I. Toxqui-Toxqui, C. Sanchez-Lopez, R. Trejo-Guerra, Frequency limitations in generating multi-scroll chaotic attractors using cfoas, International Journal of Electronics 101 (11) (2014) 1559–1569. doi:10.1080/00207217.2014.880999. [3] C. Wannaboon, W. San-Um, Digital Chaotic Signal Generator Using Ro-
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[7] Hongjun Wang, Bingbing Song, Qiang Liu, Jing Pan, Qun Ding, FPGA Design and Applicable Analysis of Discrete Chaotic Maps, International Journal of Bifurcation and Chaos in Applied Sciences and Engineering 24 (2014) 1450054 (15 pp.). [8] I. Koyuncu, A. T. Ozcerit, I. Pehlivan, Implementation of FPGA-based real
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time novel chaotic oscillator, NONLINEAR DYNAMICS 77 (1-2) (2014) 49–59. doi:{10.1007/s11071-014-1272-x}. [9] Y. Voronenko, M. P¨ uschel, Multiplierless multiple constant multiplication, ACM Trans. Algorithms 3 (2). doi:10.1145/1240233.1240234. URL http://doi.acm.org/10.1145/1240233.1240234
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[10] A. Wolf, J. B. Swift, H. L. Swinney, J. A. Vastano, Determining lyapunov exponents from a time series, Physica (1985) 285–317.
24
Highlights • •
• •
Realization of multi-scroll chaotic oscillatos using FPGAs Easy of programming coefficient values of dynamical systems using 4 decimals to implement different values of coefficient for optimal maximum Lyapunov exponents (MLE) Use of single constant multiplier entities to avoid the use of multipliers and increase the processing time Verifying hardware realization by performing co-simulation with Active-HDL
S1007-5704(15)00087-8 http://dx.doi.org/10.1016/j.cnsns.2015.03.003 CNSNS 3498
To appear in:
Communications in Nonlinear Science and Numerical Simulation
Please cite this article as: Tlelo-Cuautle, E., Rangel-Magdaleno, J.J., Pano-Azucena, A.D., Obeso-Rodelo, P.J., Nunez-Perez, J.C., FPGA Realization of Multi-Scroll Chaotic Oscillators, Communications in Nonlinear Science and Numerical Simulation (2015), doi: http://dx.doi.org/10.1016/j.cnsns.2015.03.003
This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
FPGA Realization of Multi-Scroll Chaotic Oscillators E. Tlelo-Cuautle, J.J. Rangel-Magdaleno, A.D. Pano-Azucena1 INAOE, Mexico
P.J. Obeso-Rodelo, J.C. Nunez-Perez2 CITEDI-IPN, Mexico
Abstract Chaotic oscillators have been realized using field-programmable gate arrays (FPGAs) showing good results. However, only 2-scrolls have been observed experimentally, and all reported works use commercially-available software tools for FPGA synthesis. In this manner, as a first contribution we show the FPGA realization of two multi-scroll chaotic oscillators that are characterized by their maximum Lyapunov exponent (MLE) for generating from 2- to 6-scrolls. The first multi-scroll chaotic oscillator is based on saturated function series and the second on Chua’s circuit. As a second contribution, we show their hardware realization by applying two numerical methods: Forward Euler (FE) and Runge Kutta (RK). The advantage of realizing those multi-scroll chaotic oscillators is that one can avoid the use of multiplier entities, thus optimizing FPGA resources and increasing the processing speed, as we show by realizing single constant multiplication (SCM) blocks. The experiments are verified by performing co-simulation for an FPGA Spartan 3 of Xilinx. Finally, experimental results are shown for different values of MLE (already optimized) for both multi-scroll chaotic oscillators, and the FPGA used resources are listed for generating 6-scrolls when applying FE and RK. Keywords: FPGA, Chaos, Multi-scroll, Computer arithmetic, VHDL, 1 Email: 2 Email:
[email protected]. [email protected].
Preprint submitted to Journal of LATEX Templates
March 10, 2015
maximum Lyapunov exponent, Chua’s circuit, saturated function series.
1. Introduction Chaotic oscillators have been investigated to guarantee chaotic regime by optimizing the maximum Lyapunov exponent (MLE) and ensuring a good distribution of trajectories in the phase-space portraits for generating multi-scroll 5
attractors [1]. Those optimized chaotic oscillators have been realized with different kinds of electronic devices, trying to generate the higher number of scrolls [2]. However, it has been observed the difficulty of programming different values for the parameters involved in the mathematical model of a chaotic oscillator. For example: in [1] the MLE of two multi-scroll chaotic oscillators is optimized;
10
one based on saturated function series and the other on Chua’s circuit. Both chaotic oscillators can have different values of their coefficients as well as their piecewise-linear (PWL) function can change, so that one needs to use precision circuit elements to tune the desired value for the coefficient or PWL function, but the major problem is when tuning values having more than three decimals, i.e.
15
< 0.001. Because precision resistors are used to tune those decimal values, and since they have very high variation, then we appeal using field-programmable gate arrays (FPGAs) to program coefficient parameters and PWL functions having three or more decimals. FPGAs have been used to realize applications on chaotic systems. For ex-
20
ample: in [3] a chaotic map with high MLE is implemented into an FPGA, in [4] an FPGA-based 3D chaotic system is realized by an auto-switched numerical resolution of multiple three dimensional continuous chaotic systems, in [5] an FPGA-realization of a self-synchronizing chaotic decoder in the presence of noise is presented, in [6] the FPGA design for a pseudo-random number gener-
25
ator is given, in [7] other FPGA design for a discrete chaotic map is presented, and more recently: in [8] an implementation of an FPGA-based real time novel chaotic oscillator is introduced. Although the MLE and phase portraits are shown, they are not optimized; only 2-scrolls are generated, and the hardware
2
architecture from VHDL (Very High Speed Integrated Circuit Hardware De30
scription Language) simulations is not described. In this manner, this article shows the FPGA realization of two multi-scroll chaotic oscillators having optimal and different MLEs: one based on saturated function series and the other based on Chua’s circuit. In addition, their FPGA realization is described by applying two numerical methods (Forward Euler and Runge Kutta) for solving
35
their models given by three first-order differential equations. We show their hardware description, the computer arithmetic, and their co-simulation for a low-cost FPGA from Xilinx. Both chaotic oscillators are realized for generating from 2- to 6-scrolls. At the end, we show several experimental results for different MLEs, and the FPGA used resources are listed for generating 6-scrolls
40
when applying both numerical methods.
2. Multi-scroll chaotic oscillators In [1], two multi-scroll chaotic oscillators are described: one based on saturated function series and the second on Chua’s circuit. They are optimized by maximizing their MLE and minimizing the dispersions of their trajectories in 45
the phase portraits among all scrolls in an attractor. 2.1. Chaotic oscillator based on saturated function series This multi-scroll chaotic oscillator is described by three differential equations, as given by (1), where a, b, c, and d1 are positive constants that can have values in the interval [0, 1]. The dynamical system is controlled by a PWL
50
approximation that describes the saturated function series f , which is obtained as follows: Let f0 be the saturated function described by (2), where: 1/m is the slope of the middle segment and m > 0; the upper radial {f0 (x; m) = 1 |x > m}, and the lower radial {f0 (x; m) = −1 |x < −m} are called saturated plateaus, and the segment {f0 (x; m) = x/m | |x| ≤ m} between the two saturated plateaus is
3
55
the saturated slope. x˙ = y (1)
y˙ = z z˙ = −ax − by − cz + d1 f (x; m) 1, f0 (x; m) =
if x > m
x if |x| ≤ m m, −1, if x < −m,
(2)
The saturated functions described by fh and f−h can be defined as: 2, fh (x; m, h) =
if x > h + m
x−h m , if |x − h| ≤ m 0, if x < h − m,
and f−h (x; m, −h) =
0,
(3)
if x > h + m
x−h m , if |x − h| ≤ m −2, if x < h − m,
(4)
where h is the saturated delay, and h > m. Therefore, the saturated function 60
series for generating s scrolls can be defined by (5) [1], for s > 2.
f (x; m) =
s−2 ∑
f2i−s+2 (x; m, 2i − s + 2)
(5)
i=0
2.2. Chaotic oscillator based on Chua’s diode The multi-scroll chaotic oscillator based on Chua’s circuit is described by (6) [1], where α and β are positive and real constants, and g(x) is the PWL function known as Chua’s diode and defined by (7), where mi are negative slopes. The 65
constants bi are real numbers and are associated to break point values. For
4
generating an even number (2n) of scrolls, q takes values q = 1, 2, 3, . . . , and for generating an odd number (2n + 1) of scrolls, q = 2, 3, 4, . . . . x˙ = α[y − x − g(x)], y˙ = x − y + z,
(6)
z˙ = −βy, g(x) = m2n−1 x +
2n−1 1 ∑ (mi−1 − mi )(|x + bi | − |x − bi |), 2 i=q
(7)
2.3. Optimized multi-scroll chaotic oscillators Reference [2] shows the experimental realization of multi-scroll chaotic os70
cillators based on saturated function series. In that cases the PWL function is modified and the coefficients are set to a=b=c=d1 =0.7, but the MLE is low. Therefore, the work in [1] is used herein to maximize MLE by varying a, b, c, and d1 with four decimals, i.e. between [0.0001..1.0000]. The resulting PWL function, optimized coefficients, and their associated MLE are listed in Table 1. Table 1: Optimized values for the oscillator based on saturated function series. Scrolls
2
3
5
6
75
Variable values slope x/m
break points (x − h)/m
60.60606
-0.0165, 0.0165
60.60606
60.60606
60.60606
MLE
coefficient (a, b, c, d1 ) 1.0000, 1.0000, 0.4997, 1.0000
0.3761
1.0000, 0.7000, 0.7000, 0.2542
0.3425
0.7000, 0.7000, 0.7000, 0.7000
0.2658
0.9097, 10000, 0.2632, 0.9946
0.4574
0.7002, 1.0000, 0.1858, 1.0000
0.3802
0.8224, 0.7317, 0.6642, 1.0000
0.3132
1.0000, 0.7250, 0.2250, 1.0000
0.6919
-0.5±0.165, 0.5±0.165
0.9890, 0.6810, 0.2040, 0.9790
0.6645
-1.5±0.165, 1.5±0.165
1.0000, 0.7330, 0.2050, 1.0000
0.6471
-0.0165, 0.0165
1.0000, 0.6750, 0.2100, 1.0000
0.7200
-1±0.165, 1±0.165
1.0000, 0.7530, 0.1740, 1.0000
0.6758
-2±0.165, 2±0.165
0.9670, 0.8230, 0.3380, 0.9550
0.5630
-0.5±0.165, 0.5±0.165
For the multi-scroll chaotic oscillator based on Chua’s circuit, the MLE optimization has also been performed in [1] by varying the PWL function and 5
the coefficient values. The negative slopes of the PWL function associated to Chua’s diode are different for generating even and odd number of scrolls as well as their break points, and the coefficients are also varied, resulting in the values 80
listed in Table 2. The optimized values listed in Tables 1 and 2 are used in the following sections to describe the FPGA realization of both multi-scroll chaotic oscillators by applying two numerical methods: Forward Euler and 4th order Runge Kutta. Table 2: Optimized values for the oscillator based on Chua’s circuit [1]. Scrolls
2
3
4
5
6
Variable values
MLE
slopes m0 (or m2 ), m1
break points
coef. (α, β)
-3.036, -0.276
0.1
10, 15
0.21256
-1.131, -0.395
2.618
11.991, 14.997
0.525590
-3.036, -0.276
0.8
10, 15
0.21121
-0.385, -0.234
2.394
10.297, 12.565
0.43266
-3.036 -0.276
0.1, 0.66, 0.86
10, 15
0.16851
-3.981 -0.397
0.101, 1.206, 1.467
11.489, 14.674
0.49122
-3.036, -0.276
0.8, 1.37, 2.97, 3.54
10, 15
0.22363
-2.813, -0.356
0.893, 1.559, 3.432, 4.114
10.227, 11.786
0.58500
-3.036, -0.276
0.10, 0.66, 0.86, 1.42, 1.62
10, 15
0.12587
-1.464, -0.381
0.19, 0.70, 1.58, 2.21, 3.31
10.556, 11.415
0.43326
3. Hardware realization 85
The multi-scroll chaotic oscillators described by (1) and (6) are simulated herein by applying two numerical integration methods: Forward Euler (FE) and 4th-order Runge Kutta (RK). Those dynamical systems in (1) and (6) are associated to solve an initial value problem of the form:
x˙ = f (x)
(8)
The solution of (8) depends on initial conditions xo , and f (x) includes the 90
PWL functions described by (5) and (7). The following subsections show the hardware realization of FE and RK into an FPGA for both chaotic oscillators. 6
3.1. Hardware realization of FE This numerical integration method is based on the iterative formula:
ji+1 = ji + ∆tf (ji )
(9)
where ∆t is the time-step and f (j) is taken from (8). The discretization of (1) 95
by applying (9), leads us iterating the three state variables as follows: x(i + 1) = x(i) + ∆t ∗ (y(i)); y(i + 1) = y(i) + ∆t ∗ (z(i));
(10)
z(i + 1) = z(i) + ∆t ∗ (−a ∗ x(i) − b ∗ y(i) − c ∗ z(i) + d ∗ f (x(i))); where the saturated function (5) becomes f (x(i)) that is embedded into z(i + 1) and has three values for generating 2-scrolls [2] (according to subsection 2.1). The hardware implementation of (10) is associated to VHDL programming, where it consists of adders, subtractors and multipliers. The FPGA realiza100
tion allows us proposing the length of bits being processed among the hardware blocks. For instance, according to computer arithmetic, we propose using 28bits fixed-point words, taking: 1 bit for the sign, 3 for the integer part, and 24 for the decimal part, as shown in Table 3. The VHDL entities for the adder and subtractor are easily implemented, and are shown in Fig. 1. However,
105
the multiplier entity consumes as many hardware resources as the word-length increases. Fortunately, in VHDL and for optimizing FPGA resources, a multiplication by a fixed-point constant can be realized without multipliers, just using adders, subtractors and shifts. This is a great advantage in realizing multi-scroll chaotic oscillators, as it is the case of (1) when multiplying by a, b, c and d1 ,
110
and of (6) when multiplying by α and β. In those cases, one can avoid the use of multipliers, as explained in the following. The multiplication block when one operator is a fixed-point constant can be implemented by a block called single constant multiplication (SCM) [9], which minimizes FPGA resources and increases the processing speed because it uses
7
Table 3: Distribution of the fixed-point 28-bits word.
Sign
Integer part
Decimal part
1 bit
3 bits
24 bits
0
000
.000000000000000000000000
Figure 1: 28-bits length adder and subtractor entities.
115
only adders, subtractors and shifts. As an example: One can see at3 that the multiplication of an input x by a constant 5 can be implemented by (11), indicating that the input x is shifted twice to the left and then x is added. In this case: if x=2, in binary it is 0010. Two shifts to the left gives 1000, and adding x it equals to: 1000+0010=1010. We use the tool introduced in [9] to
120
implement SCM and multiple constant multiplication (MCM) blocks with the minimum number of adders, subtractors and shifts. y = (x << 2) + x
(11)
In this article, the number x multiplying the constant is called in and the result out. Figure 2 shows the SCM implementation when the constant is 0.7, e.g. a = b = c = d1 =0.7 in [1], and 0.01. 125
As one sees, Fig. 2(a) requires 1 subtractor, 4 adders and 5 shift blocks; and Fig. 2(b) requires 1 subtractor, 2 adders and 4 shift blocks. From these diagrams one can generate VHDL code to create the multiplier entity shown in Fig. 3. Equations x(i + 1) and y(i + 1) in (10) can be implemented directly as shown
130
in Fig. 4, where Xini, Y ini represent the initial conditions and Xout, Y out the output values of the state variables x, y, respectively. 3 http://www.spiral.net/hardware/multless.html
8
Figure 2: SCM for a constant of: (a) 0.7, and (b) 0.01.
Figure 3: 28-bits length multiplier entity.
Figure 4: Block diagrams for implementing x(i + 1) and y(i + 1) from (10).
Equation z(i+1) from (10) is quite complex, because it embeds the saturated function series. Its implementation requires adders, subtractors and SCMs for the coefficients a, b, c, d1 , the value of the slope m, the saturation levels and the 135
step-size ∆t, which are constants. In addition, to generate the PWL functions 9
f (x) in (1) and g(x) in (6), comparator blocks are needed depending on the number of linear segments to generate from 2- to 6-scrolls. For instance, z(i + 1) from (10) is implemented as shown in Fig. 5, where Xini, Y ini, Zini are the initial conditions, and Zout the state variable output.
Figure 5: Block diagram for implementing z(i + 1) from (10).
140
The diagrams shown in Figs. 4 and 5 can be described by an entity called chaotic oscillator unit, as shown in Fig. 6, where Xini, Y ini, Zini are the initial conditions of 28-bits, also one can see the clock signal, reset, and the outputs associated to the three state variables. Now, one can realize the chaotic oscillator by adding a feedback loop with
145
the help of a multiplexer that will control the iterations and provide the initial conditions to the chaotic oscillator unit. The first iteration then will need 8 clock cycles that are managed by a counter embedded into the chaotic oscillator unit. The counter sends a logic signal after counting 8 through the pin Sel to the multiplexer. Afterwards, the feedback loop is activated to perform the required 10
Figure 6: Chaotic oscillator unit entity.
150
iterations. All this is performed at a second level of design composed of three entities, as shown in Fig. 7, where the registers entity holds the values of the state variables x(i), y(i), z(i). It waits some clock cycles until z(i) is available because it requires more evaluations than x(i), y(i), as appreciated in Fig 5.
Figure 7: Whole chaotic oscillator diagram executing FE.
Finally, Fig. 8 shows the top-level entity of the realization of (1) for gener155
ating 2-scrolls, and by applying the FE numerical method.
Figure 8: Top-level description of (1) when executing FE.
11
3.2. Hardware realization of RK The 4-th order RK numerical method is based on the iterative formula: ji+1 = ji + ∆tK4 (xi , ji ; ∆t)
(12)
where K4 (xi , ji ; ∆t) requires the evaluation of four constants given by, K4 (xi , ji ; ∆t) ,
1 (k1 + 2k2 + 2k3 + k4 ) 6 k1 , f (xi , ji )
∆t k1 , xi + 2 ∆t k3 , f [ji + k2 , xi + 2 k2 , f [ji +
∆t ] 2 ∆t ] 2
(13)
k4 , f [ji + ∆tk3 , xi + ∆t] where ∆t is the time-step and f (j) is taken from (8). 160
The hardware realization of RK can be performed also in a similar way than for implementing FE in the previous subsection. However, more hardware operations are required to implement (13). For instance, the MATLAB simulation by applying FE and RK with the same parameters is shown in Figs. 9 and 10. Although both numerical methods behave quite similar, their FPGA realization
165
is quite different, as shown in the following sections.
Figure 9: MATLAB simulation of (1) by executing FE.
12
Figure 10: MATLAB simulation of (1) by executing RK.
The multi-scroll chaotic oscillator based on Chua’s circuit can be realized in a similar way. However, when generating more than 2-scrolls, the PWL functions increase and one should consider the values of the coefficients and functions listed in Tables 1 and 2.
170
4. Co-Simulation results in Active-MATLAB The co-simulation helps to verify the hardware implementation before its physical realization and one can have access to each signal. In this article, the compilation of the chaotic oscillator described by VHDL code is performed by using Active-HDL, which provides an interface for MATLAB-Simulink, and
175
allows to perform the co-simulation of blocks that can be described by mathematical models or VHDL. Active-MATLAB generates a file *.m for each entity or component described by VHDL, and herein it generates a file associated to the top-level description (see Fig. 8). Within Simulink one can integrate blocks from Active, as shown in Fig. 11, where a pulse generator is used for the CLOCK
180
signal at 10 kHz, for the RESET signal a constant is used with a logic value of 1. An scope is used to visualize the signals, and the blocks To workspace capture the data and save them in arrays. We used a time simulation of 3×106 seconds. Figure 12 shows the co-simulation of (1) described in Active by VHDL code by
13
applying FE and showing 6-scrolls.
Figure 11: Active-HDL co-simulation schematic.
185
In a similar manner, by applying RK we used the VHDL code previously generated for the entities adder, subtractor, multiplier, multiplexer, counter and register. Figure 13 shows the co-simulation of (1) described in Active by VHDL code by applying RK and showing 6-scrolls. One can appreciate the good agreement of Figs. 12 and 13 with those from
190
MATLAB simulations (Figs. 9 and 10). Therefore, we proceed to synthesize the VHDL code into an FPGA.
Figure 12: Co-simulation of (1) implemented by applying FE.
14
Figure 13: Co-simulation of (1) implemented by applying RK.
5. Experimental results In the experiments we used the low-cost XC3S1000-5FT256 FPGA Spartan3 from Xilinx. The initial conditions were set to: x(0) = 0.1, y(0) = 0.1 and 195
z(0) = 0. Compared to using electronic devices, as done in [2], the use of an FPGA allows us to program the coefficient values with several decimals, in this work 3 and 4 decimals were used, as listed in Tables 1 and 2. In addition, the generated attractors that are shown in the following subsections are more stable when using FPGAs than those using active devices with precision resistors for
200
tuning the coefficient values of the chaotic oscillators. 5.1. FPGA realization of the oscillator based on saturated function series The FPGA realization of the multi-scroll chaotic oscillator based on saturated function series generates from 2- to 6-scrolls. Figure 14 shows the phase portraits for generating 2, 3, 5 and 6-scrolls and plotting the state variables
205
x − z in the oscilloscope. We selected also the experimental results for the state variable x, because one can appreciate the equal number of equilibrium points: 2, 3, 5, and 6. Figure 14 shows the results by applying FE and for the lowest value of MLE from Table 1, i.e. for each number of scrolls, the right part of the Table shows
15
Figure 14: FPGA generation of: 2-, 3-, 5-, and 6-scrolls phase portraits x − z (left), and state variables x (right) by applying FE and for the lowest value of MLE from Table 1.
210
3 values of the MLE, then the lowest value is plotted. One can appreciate the good generation of the desired number of scrolls. Figure 15 shows the phase portraits for generating also 2, 3, 5 and 6-scrolls and plotting the state variables x − z in the oscilloscope, but now by applying RK. Again, we selected the experimental results for the state variable x, and for
215
the lowest value of MLE from Table 1. One can see a little difference between Figs. 14 and 15, but the main difference is the FPGA resources used for each numerical method, which are listed in subsection 5.3. Figure 16 shows the phase portraits for generating 2, 3, 5 and 6-scrolls and
16
Figure 15: FPGA generation of: 2-, 3-, 5-, and 6-scrolls phase portraits x − z (left), and state variables x (right) by applying RK and for the lowest value of MLE from Table 1.
plotting the state variables x − z in the oscilloscope, but now when selecting the 220
values of the coefficients a, b, c, and d1 , to generate the highest value of MLE from Table 1. As one sees, these attractors are more complex than the ones shown in Figs. 14 and 15, this is because the MLE is higher than the others listed in Table 1 and then it guarantees better unpredictability of the dynamics of the chaotic oscillator [10].
225
5.2. FPGA realization of the oscillator based on Chua’s circuit The FPGA realization of the multi-scroll chaotic oscillator based on Chua’s circuit also generates from 2- to 6-scrolls. Figure 17 shows the phase portraits 17
Figure 16: FPGA generation of: 2-, 3-, 5-, and 6-scrolls phase portraits x − z for the highest value of MLE from Table 1.
for generating 2, 3, 5 and 6-scrolls and plotting the state variables x − z in the oscilloscope. In this Figure, the scrolls on the left column were generated using 230
the lowest value of MLE and the scrolls on the right column were generated using the highest values of MLE from Table 2, but by applying FE. The same procedure is performed by applying RK, and the experimental results are shown in Fig. 18. Once again, one can appreciate the good generation of the desired scrolls and they have better unpredictability as the value of the MLE increase,
235
as already known for chaotic systems [10]. 5.3. FPGA resources used for generating 6-scrolls by applying FE and RK As mentioned above, the experiments were realized by using the low cost XC3S1000-5FT256 FPGA Spartan-3 from Xilinx. The used resources are listed in the following Tables, where one can appreciate the difference between apply-
240
ing a simple numerical method like Forward Euler (FE) and a more elaborated one like the 4-th order Runge-Kutta (RK). The experimental results showed similar results for generating the desired number of scrolls, but the used resources are different for the oscillator based on saturated function series (Tables 4 and 5) and the one based on Chua’s circuit (Tables 6 and 7). For instance, as we
245
expected, and since RK is more accurate than FE, the FPGA logical resources 18
Figure 17: FPGA generation of: 2-, 3-, 5-, and 6-scrolls phase portraits x − y by applying FE and for the lowest value of MLE (left) and the highest value of MLE (right) from Table 2.
consumption doubles for both examples (saturated function series and Chua’s circuit). One can deduce it by comparing Tables 4 and 6, where both FPGA realizations are done by applying FE, and where one can appreciate a considerable increase in the use of resources. The same is observed by comparing Tables 250
5 and 7, where RK is applied. From the mathematical point of view, it is more recommended to use a more elaborated numerical method like RK instead of FE, because it is more stable and allows a step-size smaller than a the simple FE method. As one can infer, an important advantage of realizing chaotic oscillators
19
Figure 18: FPGA generation of: 2-, 3-, 5-, and 6-scrolls phase portraits x − y by applying RK and for the lowest value of MLE (left) and the highest value of MLE (right) from Table 2.
255
based on PWL functions, is that the more complex case (Table 7), was synthesizable in a low cost FPGA, even with available logic to perform other task. It is also worth mentioning that the use of SCM/MCM blocks is critical to achieve implementations on a low cost FPGA. Finally, it can be appreciated that the complexity of the algorithms is directly related to the maximum operating fre-
260
quency, which was: 70.943 MHz for Table 4, 69.500 MHz for Table 5, 58.648 MHz for Table 6, and 48.209 MHz for Table 7. These operating frequencies are much higher than when using electronic devices as in [2], thus showing that FPGA realizations are much better. In addition the operating frequencies in
20
these FPGA realizations can be increased when using high-performance chips, 265
i.e. higher cost FPGAs, where also the percentage of resource utilization will decrease. Table 4: FPGA mapping final report for generating 6-scrolls by using saturated functions series and by applying FE.
Resources
Used
Available
Utilization
Slice Registers
995
15,360
6%
Number of occupied Slices
1,681
7,680
21%
Number of 4 input LUTs
2,894
15,360
18%
Number of bonded IOBs
25
173
14%
Number of MULTI18X18s
18
24
75%
Number of BUFGMUXs
1
8
12%
Table 5: FPGA mapping final report for generating 6-scrolls by using saturated functions series and by applying RK.
Resources
Used
Available
Utilization
Slice Registers
1,891
15,360
12%
Number of occupied Slices
4,422
7,680
57%
Number of 4 input LUTs
8,149
15,360
53%
Number of bonded IOBs
25
173
14%
Number of MULTI18X18s
24
24
100%
Number of BUFGMUXs
1
8
12%
6. Conclusion It has been shown that by using FPGAs one can realize multi-scroll chaotic oscillators that have better behavior than by using active devices like operational 270
amplifiers. In this article the cases of study were two oscillators: one based on saturated function series and other based on Chua’s circuit. Both chaotic oscillators were realized with FPGAs for generating from 2- to 6-scrolls and characterized by their maximum Lyapunov exponent (MLE), which was optimized
21
Table 6: FPGA mapping final report for generating 6-scrolls by using Chua’s circuit and by applying FE.
Resources
Used
Available
Utilization
Slice Registers
1,477
15,360
9%
Number of occupied Slices
2,727
7,680
35%
Number of 4 input LUTs
4,967
15,360
32%
Number of bonded IOBs
24
173
13%
Number of MULTI18X18s
24
24
100%
Number of BUFGMUXs
1
8
12%
Table 7: FPGA mapping final report for generating 6-scrolls by using Chua’s circuit and by applying RK.
Resources
Used
Available
Utilization
Slice Registers
2,667
15,360
17%
Number of occupied Slices
5,347
7,680
69%
Number of 4 input LUTs
9,714
15,360
63%
Number of bonded IOBs
25
173
14%
Number of MULTI18X18s
24
24
100%
Number of BUFGMUXs
1
8
12%
to guarantee better unpredictability. The realizations were implemented at the 275
hardware level, showing that these kind of chaotic oscillators can reduce the use of multiplier entities by using single constant multiplication (SCM) blocks, which optimize the FPGA resources and increase the processing speed. The hardware implementation was performed by applying two numerical methods: Forward Euler (FE) and Runge Kutta (RK). A co-simulation using Matlab and Active-HDL
280
was performed before the physical synthesis into the FPGA to guarantee the generation of scrolls. Finally, the experimental results for both chaotic oscillators, and by implementing different values of the coefficients associated to different values of MLE for both chaotic oscillators, leads us to conclude on the suitability of FPGAs for realizing chaotic oscillators with multiple scrolls and
285
high MLE.
22
Acknowledgments This work is partially supported by CONACyT/Mexico under the projects: 237991 and 136056.
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Highlights • •
• •
Realization of multi-scroll chaotic oscillatos using FPGAs Easy of programming coefficient values of dynamical systems using 4 decimals to implement different values of coefficient for optimal maximum Lyapunov exponents (MLE) Use of single constant multiplier entities to avoid the use of multipliers and increase the processing time Verifying hardware realization by performing co-simulation with Active-HDL