p-Si structures in wide range frequency and voltage

Journal Pre-proof Frequency and voltage dependence of barrier height, surface states, and series resistance in Al/Al2O3/p-Si structures in wide range frequency and voltage

Çağrı Gökhan TÜRK, Serhat Orkun TAN, Şemsettin Altındal, Burhanettin İnem PII:

S0921-4526(19)30856-7

DOI:

https://doi.org/10.1016/j.physb.2019.411979

Reference:

PHYSB 411979

To appear in:

Physica B: Physics of Condensed Matter

Received Date:

03 December 2019

Accepted Date:

31 December 2019

Please cite this article as: Çağrı Gökhan TÜRK, Serhat Orkun TAN, Şemsettin Altındal, Burhanettin İnem, Frequency and voltage dependence of barrier height, surface states, and series resistance in Al/Al2O3/p-Si structures in wide range frequency and voltage, Physica B: Physics of Condensed

Matter (2019), https://doi.org/10.1016/j.physb.2019.411979

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Frequency and voltage dependence of barrier height, surface states, and series resistance in Al/Al2O3/p-Si structures in wide range frequency and voltage

1Çağrı

Gökhan TÜRK, 2Serhat Orkun TAN, 1Şemsettin Altındal, 3Burhanettin İnem

1Gazi

University, Faculty of Sciences, Department of Physics, Ankara-Turkey University, Faculty of Technology, Department of Electrical Engineering, Karabuk-Turkey 3Gazi University, Faculty of Technology, Department of Metallurgical and Material Engineering, AnkaraTurkey 2Karabük

Abstract In this study, Al/Al2O3/p-Si (MIS) type structures were fabricated and then the effects of Al2O3 interlayer on the electrical characteristics have been investigated at room temperature. For this purpose, capacitance/conductance-voltage-frequency (C/G-V-f) measurements were performed in the wide range frequency (1kHz-5 MHz) and voltage ( 3V) to get more reliable and accuracy results on the barrier height (BH) formation at Al/p-Si interface, conduction mechanisms, and main electrical parameters. Experimental results indicate that C and G/ values are strong function of frequency and voltage particularly in the regions of accumulation and depletion. Calculating from the interception and slope of C-2-V plot, the doping acceptor atoms (NA), BH and depletion layer width (WD) were obtained for each frequency, respectively. Both BH and WD values exponentially increase by frequency increment. Nicollian-Brews method were used to extract voltage dependence profiles of Rs and frequency from C and G data. Keywords: Electrical Data; Conduction Mechanism; Series resistance; Surface states. Corresponding author: Serhat Orkun TAN

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1.

INTRODUCTION

In recently, metal-semiconductor (MS) structures with an interlayer as ferroelectric, and polymer materials have gained substantial interest when considering its influence on the quality of the structure [1-9]. Utilizing high- dielectric interlayer such as Al2O3, TiO2 [1-4], BaTiO3, Bi3Ti4O12 [5,6], and metal or graphene-doped polymer materials [7-10] at M/S interface can be improve the quality and performance of these devices. Therefore, these high-dielectrics materials have been used an interlayer instead of low-dielectric insulating layer such as SiO2 (3.8). Among them, Al2O3 has been attracted for electronic device applications due to its large bandgap (7 eV), highbreakdown electric field (109 V.m-1), high-dielectric (9), high-thermal stability, low leakage current, good interface with Si crystal wafer, and thermodynamic stability on Si up to high temperatures [10]. Although, there are various methods to grown Al2O3 film, but atomic layer deposition (ALD) is popular due to the great chemical versatility and control over film uniformity [3]. Because, such high dielectric can be quite increased the performance of the MS structure by passivated the surface states (Nss) and dislocations at junction, increased the BH and decreased the leakage current [1,6,12]. Additionally, the utilizing high- dielectric interlayer such as Al2O3, TiO2 [1-4], BaTiO3, Bi3Ti4O12 [5,6], and metal or graphene-doped polymer materials [7-9] at MS interface can be improve the quality and performance of these devices. But, during the fabrication processing, many unwanted interface traps which are referred to dangling bonds, oxygenvacancies, atom-like bonds and anti-site defects may be located at or very close to the interlayer/semiconductor interface and they have an energy distribution within the bandgap of semiconductor (Eg) and even they project into the semiconductor’s conduction (Ec) and valence band (Ev) [10-13]. Since electronic charges (electrons or holes) are captured in these traps, they can behave as positive or negative charges at the interface. The homogeneity of these interlayer and their thickness are also very effective both on the electric and dielectric characteristics of these devices. Therefore, one of the important reasons to choose Al2O3 as an interlayer is to prove the effects of natural oxide defects such as oxygen cavities and defects such as grain boundaries on the electrical and dielectric properties MIS type structures. In addition , the performance of MS structures with and without interlayer rely on many aspects as barrier height (BH) disposition between MS, frequency, applied electric field or voltage, series

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resistance (Rs), and sample temperature [14-16]. Ideally, the capacitance (C) and conductance (G/) values of MIS type devices are usually frequency independent, but in application states may substantially disparate particularly at low and intermediate frequencies by the reason of the traps entity and their relaxation/life time (), interfacial and dipole/orientation polarizations, and Rs [1115]. Because, the charges at these traps are able to react to the exterior alternating at low/intermediate frequencies and so lead a surplus capacitance and conductance measured of them. Besides, interlayer may be polarized temperately under an exterior dc field that shifts the charges from equilibrium condition. In the light of above discussions, in this study, we focused the effect of Al2O3 interlayer, interface states and series resistance on the electrical qualifications. For this aim, including a set of C-V and G/-V data of the fabricated of Al/Al2O3/p-Si (MIS) structure, both the forward and reverse biases impedance measurement were implemented between 1kHz-5 MHz and  3V to acquire more veridical and reliable outputs on the barrier height (B) formation and the conduction mechanisms. 2. EXPERIMENTAL DETAILS In this study, Al/Al2O3/p-Si (MIS) structure were grown on the Boron-doped (p-type Si) single crystal with (100) surface orientation and 2 inch (=5.08 cm) radius, 300 µm thickness, 1 .cm resistivity or 1.39x1016 cm-3 doping acceptor atoms (NA). Before fabrication, p-Si wafer was ultrasonically degreased in CHClCCl2, CH3COCH and CH3OH organic solvents for 5 minutes and then it was rinsed in deionized water (DW) having resistivity of 18 M cm for enough prolonged time (~10 min) to remove organic impurities at p-Si wafer. After that, p-Si wafer was etched in a solution of 6 HNO3:1 HF:35 H2O and was also rinsed in DW at 10 minutes and the it was dried by high-pure dry nitrogen (N2) gas. Following to the cleaning process of the surface p-Si wafer, immediately it was taken into higher vacuum thermal metal evaporation system to realize back ohmic and obstacle any oxidation on the surface of p-Si wafer and hence the high purity Al (99.999%) layer with 150 nm was evaporated on the whole back side of the p-Si wafer at 10-6 Torr and then it was annealed at 550 oC in nitrogen ambient to perform high-quality or low resistivity ohmic contact. After ohmic contact, a layer of Al2O3 was grown on the Si substrate by ALD

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technique. ALD produces films with ripping conformance and precisely controlled thickness. The detailed ALD mechanism has been reported elsewhere [17,18]. Immediately, after Al2O3 growth on Si wafer, high purity Al (99.999%) dots with 150 nm thicknesses and 1 mm diameter was also thermally evaporated onto the (Al2O3) layer at 10-6 Torr by use a shadow mask in same metal evaporation system. Cu holder mounted the fabricated structures by silver dag and then the electrical contacts were made to the upper electrodes by utilizing silver pasted and thin Ag coated Cu wires to perform electrical measurements. Impedance measurements were made by using an HP 4192A LF impedance analyzer in the large frequency interval (1 kHz to 5 MHz) and biases (±3V) by 50 mV steps. A connection was made between IEEE-488 AC/DC converter card and HP 4192A LF impedance analyzer to control these measurements. The fabricated Al/(Al2O3)p-Si structure was schematically presented in Fig. 1.

Fig. 1. The schematic presentation of the structure. 3. RESULTS AND DISCUSIONS Fig. 2 and 3 show the capacitance-voltage-frequency (C-V-f) and conductance-voltagefrequency (G/-V-f) data of the Al/Al2O3/p-Si (MIS) structure, respectively. In order to acquire more truthful and reliable results on the electric characteristics, these measurements were implemented between 1 kHz-5 MHz and  3V by 50 mV steps. As indicated in Fig. 2, the C-V plot has accumulation, depletion and inversion zones for each frequency and the capacitance values increase with increasing biases. But, the alternation in C is substantially high in depletion and accumulation zones due to the interface traps located at (Al2O3)/p-Si interface and Rs respectively. As indicated in figures 2 and 3, both the C-V and G/-V plots have strong/weak

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accumulation, depletion and weak/strong inversion regions each frequency. That is to say, C and G values become independent from voltage in strong inversion and strong accumulation regions. This indicated that the measured voltage range (±3V) is very suitable and hence it is not necessary the other voltages. The measured range may be changed from 1 V to a few bias voltage (±20V) depend on interfacial layer and sample characteristics. The observed discrepancies between C-V and G/-V plots at lower frequencies (f≤100 kHz) can be ascribed by the interface traps, their relaxation times, and their restructure and reordering under an external electric field. It is well known that the interlayer can be polarized simply under an electric field that disbalances the charges position at lower and intermediate frequencies. Similarly, tracking ac signal is simple for surface states and hence yield to surplus total value of both C and G, that based on the ac signal frequency and interface states relaxation time.

Fig. 2. C-V-f characteristics of the structure.

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Fig. 3. G/-V-f characteristics of the structure. As can be clearly seen in Fig. 3, the G/-V plot has a distinctive peak and its position shift towards to accumulation regions due to restructure and reordering of charges at traps under external electric field or bias voltage. But the peak behavior become disappear above 100 kHz because of the relaxation time of surface states closer to period (T=1/2f) and hence they cannot follow the alternating signal. Therefore, after 100 kHz, Rs becomes more effectual on the C and G values at accumulation zone. Nicollian and Goetzberger [13] have observed that both the value of C and G decrease with increasing frequency because of at low and moderate frequencies surface states can simply track the alternating signal and gain a surplus capacitance and conductance to them. Additionally, as presented in Fig. 2 and 3, after 100 kHz G/ rapidly increase with increasing frequencies while C decreases at the accumulation zone. This type of C and G demeanor with frequency is named as an inductive behavior. These observed increment in the C and G with frequency decrement can be conceded on the bases of charge storage at surface states and they cause an increment at dielectric constant (’) and dielectric loss (’’). The Nss existence is the result of semiconductor’s periodic lattice structure interruption, impurity concentration, cleaning and surface preparation, the formation of interlayer

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and its homogeneity and the organic pollution in the laboratory environment. The positive or negative charges behavior of electrons and holes at the interface are in case of the traps in these states [19]. When interlayer thickness is higher than a few nm (≥ 3 nm), the charges at these states are in equilibrium with the semiconductor, whereas it is less than at about 3 nm they are in equilibrium. On the other hand, Nss are more pronounced at low and moderate frequencies, but the Rs effect can also be ignored in related frequencies. For the purpose of acquiring resistance’s voltage dependent profile (Ri), admittance method improved by Nicollian and Brews [13] can be used by impedance measurements. On the authority of this method, the value of Ri at high frequencies (f ≥0.5 MHz) at strong accumulation region corresponds to the real value of Rs for MIS type structure. But it can be also subtracted for any measured Cm and Gm values as follow [13]: But it can be also subtracted for any measured Cm and Gm values as follow: Rs 

Gm

G    Cm  2 m

2

(1)

In Eq.1;  f is the angular frequency, for the real Rs value at strong accumulation zone, the Cma and Gma values must be used instead of Cm and Gm values in Eq. 1. These crucial values required that exceptional notice be given to Rs effects in the admittance-based measured methods application (C-V and G/w-V).

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Fig. 4. The Rs-V plot of the structure. As presented in Fig. 4, Rs vs V plots have typical peaks for every frequency. While the peak magnitude increasing with decreasing frequency, its location moves in the direction of negative biases due to the surface states particular density distribution and their restructure and reordering under external electric field based on relaxation time. Besides, Rs at strong accumulation zone for each frequency equaled to the real value of Rs for 3 V. As shown inset in Fig 4, Rs almost decreases exponentially with frequency increment. In general, Rs can originate from the back ohmic and front rectifier contacts, the contact made by the probe wires to the rectifier contact, the bulk resistance of the semiconductor, some impurities at surface of semiconductor, and extremely nonuniform doped donor/acceptor atoms in the semiconductor [13]. The existence of Rs leads to serious errors in the extraction of electric parameters, but it can be decreased by better cleaning and sample fabrication processes, low barrier height (BH) formation between metal and semiconductor, making admittance/ impedance measurements (Y=1/Z=G+jwC) at low or

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intermediate frequencies, and measuring Rs and correcting the measured admittance before the intended information is acquired. The investigation of main electrical parameters such as BH, depletion layer width (WD), and doping concentration atoms (NA or ND) as function of frequency is more important to procure more veridical and reliable results on the conduction mechanisms. Because only at one or narrow frequency and voltage range of these parameters cannot supply this information. When measurements are implemented at enough high frequencies (f ≥100 kHz), the depletion layer capacitance in a MIS or MOS type structures can be derived as [20-21].

C 2 

2( B  c2V  E F ) qc22 s o A2 N A

(2)

and c2 can be extracted from the slope of C-2-V curves as;

c2 

i

 i  q N ss 2



N A (exp erimental ) N A (theory )

(3)

The theoretical value of doping acceptor atoms (NA=1/qhh=1.39x1016 cm-3) was calculated by using the value of resistivity of n-Si wafer (1 .cm) by supplier hole mobility (h=450 cm2/(V,s)), but the experimental value of it was calculated from the slope (tan=C-2/V=2/qsoA2NA) of the liner part C-2 vs V plot for each frequency. In Eq. 2 and 3; the interlayer’s dielectric constant, electronic charge, interlayer thickness, diode area interface states density, carrier (acceptor) concentration are denoted by ɛi, q, δ, A, Nss and NA, respectively. As shown in Eq. 3, while the value of c2 goes to 1 then Nss goes to zero (ideal case), but when c2 goes to zero then Nss goes to . The value of c2 was found from the Eq.3 and were tabulated in Table 1. The frequency dependence mean value of Nss was also calculated from the Eq.3 by using the values of  (=25 nm) and i (=9) and tabulated in Table 1. The interception of C-2 with the reverse bias axis is V0 and derived by;

Vo  VD 

kT q

(4)

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Here, the diffusion potential is Vd at zero biases and  B (C-V) can be extracted by the expression below from Fig 6 for intermediate and high frequencies.  B (C  V )  VD  E F   B

(5)

The energy gap is between valance band edge and the bulk Fermi level is EF, the effective density of states at valance band of Si is NV and they are given by the below equations. EF 

kT Ln( NV / N A ) q

NV  4,82 x10 T 15

3/ 2

(6) * h

(m / mo )

3/ 2

(7)

Here, holes effective and electrons rest masses can be expressed as mh and mo, respectively [22].  B is the image force lower barrier and Em is the maximum electric field which is given by the

followings, respectively.

 qEm   B     4 s o 

 2qN AV0  Em      s o 

1/ 2

(8)

1/ 2

(9)

The value of depletion layer width (WD) can be also calculated from the intercept voltage (Vo=VD-kT/q) and slope (=2/qsoA2NA) of the liner part C-2 vs V plot for each frequency. Thus,  B (C-V) values can be acquired from Eq. (5) after calculating Vd, EF and  B values from the

above equations. The acquired values of EF, V0, NA,  B and  B (C-V) were presented in Table 1. C-2-V plot indicates unbending lines in large reverse biases zone and the diffusion potential is acquired in terms of these lines’ extrapolation to the bias axis as presented in Fig. 5. The interface states density and interlayer can be expressed as a function of the intersection and slope of the C2-V

graph. [23-25]. Interface states and interlayer charges are unable to track the ac signal

especially in the strong inversion zone as seen at C-2-V plot in Fig. 5.

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Table 1. The distinct parameters extracted from C-V plots for the structure. WD

Nss

Emax

B

B(C-V)

(m)

(eV-1.cm-2)

104x(V.cm-1)

(meV)

(eV)

0.470

9.3

2.25x1012

4.47

80.21

0.180

0.191

0.482

14.2

2.14x1012

4.53

80.75

0.238

6.937

0.190

0.500

18.1

1.99x1012

4.61

81.47

0.307

0.199

7.063

0.190

0.508

19.2

1.93x1012

4.65

81.83

0.332

50

0.235

7.221

0.189

0.519

21.5

1.85x1012

4.70

82.29

0.388

70

0.277

7.330

0.189

0.527

23.3

1.79x1012

4.74

82.59

0.436

100

0.309

7.430

0.189

0.534

23.4

1.74x1012

4.74

82.59

0.440

200

0.377

7.529

0.188

0.542

25.6

1.68x1012

4.80

83.15

0.507

300

0.397

7.558

0.188

0.544

26.2

1.67x1012

4.81

83.23

0.527

500

0.438

7.588

0.188

0.546

27.4

1.66x1012

4.82

83.31

0.567

700

0.463

7.625

0.188

0.549

28.2

1.64x1012

4.83

83.39

0.592

1000

0.490

7.617

0.188

0.548

29.0

1.64x1012

4.83

83.39

0.620

2000

0.558

7.529

0.188

0.542

31.1

1.68x1012

4.80

83.15

0.688

3000

0.604

7.471

0.188

0.537

32.5

1.72x1012

4.78

82.99

0.734

5000

0.694

7.410

0.188

0.533

34.0

1.74x1012

4.83

83.39

0.824

f

Vo

NA

EF

(kHz)

(V)

1015x(cm-3)

(eV)

10

0.043

6.518

0.192

20

0.109

6.698

30

0.174

40

c2

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6.4E+19

5.9E+19

C -2 ( F-2 )

5.4E+19

5.0E+19

4.5E+19

4.0E+19

C(10kHz) C(40kHz) C(100kHz) C(500kHz) C(2000kHz) -1.8

C(20 kHz) C(50kHz) C(200kHz) C(700kHz) C(3000kHz) -1.7

C(30kHz) C(70kHz) C(300kHz) C(1000kHz) C5000kHz) -1.6

V(V)

-1.5

-1.4

-1.3

Fig. 5. C-2-V plot for the structure. As presented in Fig.6,  B (C-V) values almost linearly increase with frequencies increment as presented in Fig. 6 and Table 1. This is an expected behaviour and ascribed by the interface states have a special density distribution in the band gap of Si [26-29]. Usually, the value of C and G in the MS and MIS type structures at high frequencies is independent from the frequency and increases with bias increment in the ideal case, but situation is substantially distinctive at low and intermediate frequencies and they becomes depend on the Nss capability to follow the ac signal when the existence of a native or deposited interfacial layer at M/S interface [11,13]. Therefore, at lower-frequencies, the Nss can simply track the ac signal and hence yield an excess C and G to the measured real values of them, but at high frequencies they cannot contribute to the C and G since their relaxation time () is too long to permit the charge to move in and out of them in response to ac signal [11,13]. Therefore, the existence interlayer can simply polarize under electric field that dislocates the charges from their equilibrium states.

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0,90

 B (C-V), (eV

0,75

0,60

0,45 y = 0,096x - 0,6857

0,30

2

R = 0,991

0,15

0,00 9

10

11

12

13

14

15

16

Ln (f)

Fig. 6. The B-ln(f) plots for the Al/Al2O3/p-Si (MIS) structure. As shown in Fig 7 (a), while c2 increase with frequency increment especially at low and intermediate frequencies, the mean values of Nss decreases because they cannot ac signal at high frequencies The value of c2 is almost the reverse value of ideality factor (n=1/c2) obtained from the forward bias I-V data which is a measure of the deviated from ideal case. In ideal case the value of c2 is almost equal to unity like ideality factor. As can be table 1, the calculated order of mean value of Nss (1012 eV-1.cm-2) are very suitable for the MIS type structure. Such lower values

0.55 0.51 0.47 0.43 0.39 0.35 0.31 0.27 0.23 0.19 0.15 0.11 0.07 0.03 -0.01

2.4E+12

2.2E+12

c2 2.0E+12

1.8E+12

9

10

11

12

13

14

Ln (f)

15

16

Fig. 7 Nss and c2 versus Ln(f) plots for the structure.

1.6E+12

Nss (eV-1.cm-2)

c2

of Nss is the passivated effect of high-dielectric Al2O3 insulator layer.

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The voltage or energy dependent profile of the Nss is also can also be obtained from the measured low frequency (1 kHz) - high frequency (5 MHz) capacitance method because the MIS structure behavior is differ from the ideal case due to the surface states and relaxation time presence at low frequencies. At low frequency (f≤1kHz) almost all surface states can monitor the ac signal and yield an excess capacitance, which depend on frequency or period (f=1/T). But, this contribution of surface state capacitance to the total capacitance can be negligible small. Fot this reason, the voltage dependent profile of Nss is also calculated from the low-high frequency capacitance method by utilizing the following expression and is given in Fig.8 [11,13,28-33]. Nss= 1/(qA) {[1/CLF-1/Cox]-1-[1/CHF-1/Cox]-1}

(10)

Here, the diode area, the measured low and high frequency capacitance, and the oxide layer capacitance are denoted by A, CLF, CHF, and Cox, respectively. Cox can be acquired from the C and G/ values for adequately higher frequencies (f≥5MHz) at strong accumulation zone by the expression below.

  G 2  Cox  Cma 1   ma     Cma  

(11)

Nss (eV-1.cm-2)

1E+14

1E+13

1E+12

1E+11

1E+10

1E+09 -3

-2

-1

0

1

V (V)

2

3

Fig. 8 Nss vs V plots for the Al/Al2O3/p-Si structure obtained from CLF-CHF method.

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As shown in Fig. 8, the value of Nss are strong function of applied biases as well as frequency and their magnitude change from zone to zone biases range devolve on a special dispersion of them and their relaxation time and homogeneity of interfacial layer and series resistance. As presented in Fig. 7 and Fig.8, the magnitude of Nss obtained from CLF-CHF method are higher than the obtained mean value of them from c2. These results approved that C has higher values at low frequency (1 kHz) due to Nss which can easily track the ac signal. And yield an excess capacitance and the contribution of Nss decrease with increasing frequency. In other words, the measured capacitance values are not promoted by Nss at adequately higher frequencies since a sense of balance occurs between them and the semiconductor. As a result, in the literature similar outcomes have already been found in recently [1,3,10]. Among them, electric and dielectric properties of the Al/Al2O3/p-Si SBD have been investigated by D. E. Yıldız et al. as function of frequency and voltage between 10 kHz-1 MHz and a sturdy function both on the frequency and voltage was determined due to the presence of surface states, series resistance and interlayer [10]. Ç. Ş. Güçlü et al. have been fabricated a (Au/Ti)/Al2O3/nGaAs structure with thin (30 Å) interfacial layer formed by atomic layer deposition and observed similar results [1]. On the other hand, the electrical and dielectric features of TiN/Al2O3/p-Si MIS structure were analyzed between 380-450 K at 1 MHz by S. Hlali et al [3] by using C-V-T and GV-T measurements. They were uncovered that the forward biases C-V plots display a distinct peak at high temperatures due to the series resistance and interface states at Al2O3/p-Si. All these results are also indicated that the use of aAl2O3 film at M/S interface leads to an increase of dielectric permittivity so can be more storage electronic charges or energy and leads to a decrement in the Rs and Nss values.

4. CONCLUSION In this study, we focused the Nss, Rs, and Al2O3 insulator layer effects on the electrical characteristics in wide frequency (1 kHz-5MHz) and voltage ( 3V) at room temperature to acquire more and more reliable and precise results on the main electrical parameters, conduction mechanisms, and the BH formation at M/S interface. Firstly, revealing the Rs effect on the C-V and G/-V measurements, the Rs-V plot were extracted from the measured C and G data for each frequency as a function of applied biases. The Rs-V plot shows a peak in depletion region. While

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the peak magnitude decreases with frequency increment, location of it move towards to accumulation region due to restructure and reordering of charges at surface states or traps. Secondly, for each frequency NA, BH and WD were calculated from the incline and interception of C-2-V plot, respectively, and their values increase with frequency increment almost as exponentially. Such behavior of them stems from Al2O3 interlayer existence, interface traps with different relaxation times, interfacial and dipole polarization. In conclusion, the location of Nss between Si/Al2O3 and Rs were considerably affected the electrical qualifications of the Al/Al2O3/pSi, which are dependable on the non-ideal behavior of C-V data. Ultimately, feasible applications can also be benefited from Al/Al2O3/p-Si structure as a suitable electronic material. Acknowledgements: This study was supported by Gazi University Scientific Research Project. (Project Number: GU-BAP.05/2019-26). REFERENCES [1] Ç. Ş. Güçlü, A. F. Özdemir, A. Karabulut, A. Kökce, Ş. Altındal, Mater. Sci. Semicond. Process. 89, 26-31 (2019). [2] O. Pakma, N. Serin, T. Serin, Ş.Altındal, Physica B, 406: 4, (2011), 771-776. [3] S. Hlali, A. Farji, N. Hizem, L. Militaru, A. Kalboussi, A. Souifi, J. Alloys Compd, 713, 194203 (2017) [4] Y. Şafak-Asar, T. Asar, Ş. Altındal, S. Özçelik, J. Alloys Compd, 628, 442-449 (2015). [5] V. Rajagopal Reddy, V. Manjunath, V. Janardhanam, Y. H. Kil, C. J. Choi, Journal of Elec Materi., 43, 3499-3507 (2014). [6] H.G. Çetinkaya, M. Yıldırım, P. Durmuş, Ş. Altındal, J. Alloys Compd, 721, 750-756, (2017). [7] S. Altındal Yerişkin, M. Balbaşı, S. Demirezen, Indian J Phys, 91, 421-430 (2017). [8] Ç. Bilkan, Y. Azizian-Kalandaragh, Ş. Altindal, R. Shokrani-Havigh, Physica B, 500, (2016), 154–160. [9] S.O. Tan, IEEE Trans. Nanotechnol., 18, 432-436, (2019). [10] D. E. Yıldız, M. Yıldırım, M. Gökçen, Journal of Vacuum Science & Technology A 32, 031509. [11] S. M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, New York, 1981.

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Credit author statement

Çağrı Gökhan Türk: Visualization, Data curation, Serhat Orkun Tan: Writing-Original draft preparation, Reviewing and Editing, Investigation, Şemsettin Altındal: Conceptualization, Methodology, Burhanettin İnem: Supervision, Validation

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Declaration of interests ☒ The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. ☐The authors declare the following financial interests/personal relationships which may be considered as potential competing interests: