Wide operating voltage range and low power consumption EPROM structure for consumer oriented ASIC applications

Parallel testing of parametric faults in a threedimensional d)namic random-access memory P MAZUMDER (Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA) IEEE J. Solid State Circuits (USA), vol. 23, no. 4, pp. 933-941 (Aug. 1988) A testable design of dynamic random-access memory (DRAM) architecture which allows one to access multiple cells in a word line simultaneously is presented. The technique utilises the two-dimensional (2-D) organisation of the DRAM and the resulting speedup of the conventional algorithm is considerable. The failure mechanism in the three-dimensional (3-D) DRAM with trench-type capacitor is specifically investigated. As opposed to the earlier approaches for testing parametric faults that used sliding diagonaltype tests with O(n 3/2) complexity, the algorithms discussed here are different and have O(v/n/p) complexity, wherep is the number ofsubarrays within the DRAM chip. These algorithms can be applied externally from the chip and also they can be easily generated for built-in self-test applications. (12 refs.) Wide operating voltage range and low power consumption EPROM structure for consumer oriented ASIC applications T MARUYAMA, Y KAWAMURA, N KITAGAWA, K SHINADA, N HANADA, Y SUZUKI (Toshiba Semicond. Syst. Eng. Center, Kawasaki, Japan) Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (Cat. No. 88CH2584-I), Rochester, NY, USA, 16-19 May 1988(New York' HY, USA: IEEE 1988), pp. 4.1/1-4 To satisfy demands for low power consumption and low-voltage operation in consumer-orientated ASIC (application-specific integrated circuit) applications, an EPROM (erasable programmable read-only memory) with a novel cell structure and circuit configuration has been developed. It offers a wide operating voltage range, from 2.7 to 5.5 V, and low power consumption of about several hundred I~W when applied to a 4-bit microcontroller. (5 refs.) Configurable EEPROMs for ASICs B CARNEY, E LUCERO, R MENDEL, H REITER (Nat. Semicond. Corp., Santa Clara, CA, USA) Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (Cat. No. 88CH2584-1), Rochester, NY, USA, 16-19 May 1988(New York, NY, USA: I EEE 1988), pp. 4.2/1-4 A 5-V, variable-size EEPROM (electrically erasable programmable read-only memory) is discussed. A test chip providing 256xS-bit memory is described, as well as the methodology used to implement it. Certain special nonvolatile memory circuits are investigated. Application areas, manufacturing issues, and testing techniques are also considered. (4 rcfs.) Transparent-refresh DRAM ('FRED) using dual-port DRAM cell T SAKURAI, K NOG,,~,4I, K SAWADA,T IIZUKA (Toshiba Corp., Kawasaki, Japan)

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Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (Cat. No. 88CH2584-1), Rochester, NY, USA, 16-19 May 1988(New York"NY, USA: IEEE 1988), pp. 4.3/1-4 ., A novel memory circuit, the traTisparent-refresh DRAM (TReD), is proposed to make a dynamic random-access memory (DRAM) virtually refreshfree, and a test device is successfully fabricated. The TReD uses dual-port dynamic RAM cells, one port of which is assigned for a refresh operation and the other port is assigned for a normal read/write operation. Using the configuration, users of the RAM are freed ~ from a cumbersome refresh control without acce~stime degradation. The TReD cell size is about 1/2.5/ffa 4-transistor SRAM (static RAM) cell. so that it can provide very-high-density RAM macros, which is functionally static. As a dual-port memory, the proposed dual-port DRAM cell size is 1/5 of the dual-port SRAM ceil, and is suitable for large-scale dual-port memory macros in ASIC (application-specific integrated circuit) environments. (11 refs.) An experimental 2-bit/cell storage DRAM for macro cell or memory-onqogic application T FURUYAMA, T OHSAWA (Toshiba Corp., Kawasaki, Japan), Y NAGAHAMA, H TANAKA, Y WATANABE, T KIMURA, K MURAOKA, K NATORI Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (CaL No. 88CH2584:1), Rochester, NY, USA, 16-19 May 1988 (New York, NY, USA: IEEE 1988), pp. 4.4/1-4 A novel muhiple-level storage DRAM (dynamic random-access memory) technique which obtains fairly fast access time is presented. The RAM area, especially the cell-array area, which is highly defectsensitive, is reduced with this technique. Reasonable yield can thus be achieved. An experimental l-Mb DRAM has been fabricated, and the 2-bit/cell storage technique has been verified to be suitable for macro-cell or memory-on-logic application. (2 refs.) A 185 KX6 field memory for TV/VTR pictures Y MURAKAMI, T IMAI, K INOUE, K HATI'ORI, Y MATSUURA,M HAYASHI,K MIKI, YTORIMARU (Sharp. Corp., Nara, Japan) Proceedings of the IEEE 1988 Custom Integrated Circuits Conference (Cat. No. 88CH2584-1), Rochester, NY, USA, 16-19 May 1988(New York, NY, USA: IEEE 1988), pp. 4.5/1-.4 The authors describe the design and fabrication results for a 185 KX6-bit field memory which is suitable for storing TV signals. This device offers an efficient and economical architecture for storing one field of NTSC signals on a single chip. It permits 3-fsc sampling and 6-bit quantisation and contains all address-generating and refresh control circuits. Continuous read and write operation with a 60-ns cycle time, refresh-free operation, and 0.5-H jump function enhance the system performance. Standard cell design methodology is adopted to comply quickly with customer's requests. (2 refs.)