- Email: [email protected]
shaper ASIC family for universal low power applications
Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
A wide dynamic range multi-channel preamplifier/shaper ASIC family for universal low power applications M.A. Baturitskya,*, O.V. Dvornikovb, V.A. Tchekhovskib, N.I. Zamiatinc b
a The Institute of Nuclear Problems, Belarusian State University, Bobruiskaya street 11, Minsk 220050, Belarus The National Scientific and Educational Centre of Particle and High Energy Physics of the Belarusian State University, M. Bogdanovich street 153, Minsk 220040, Belarus c The Joint Institute for Nuclear Research, Dubna, Moscow district 141980, Russia
Received 3 June 2002; received in revised form 26 August 2002; accepted 27 August 2002
Abstract A universal ASIC family for intermediate energy physics detectors has been designed using a bipolar/JFET technology. The family consists of two 8-channel charge-sensitive preamplifiers (CSP) ZENIT-A2, ZENIT-A3 and a shaper ZENIT-B. The values of switched gain of both CSPs are 80 and 240 mV/pC for ZENIT-A2 and 500 and 1000 mV/pC for ZENIT-A3 with channel-to-channel non-identity not more than 75%. The CSPs can operate with input capacitance up to 300 pF for low gain and 150 pF for high gain mode. The input signal dynamic range of the shaper is matched to the outputs of both CSPs. The shaper has fast and slow outputs. The CSPs have a power consumption of 13 mW/channel; the shaper of 44 mW/channel. r 2003 Published by Elsevier Science B.V. Keywords: Charge sensitive preamplifier; Wide dynamic range; Shaper; Multi-channel ASIC
1. Introduction The main difference between front-end electronics used in Intermediate Energy Physics (IEP) and High Energy Physics (HEP) is a large input signal dynamic range of 80–100 dB, large detector capacitances of a few hundreds of picofarads, and large peaking times used to obtain low noise. The relatively small number of channels allows hybrid implementation of the IEP front-end electronics permitting to get extremely low noise values by *Corresponding author. Tel.: +375-172-208481; fax: +375172-263668. E-mail address: [email protected] (M.A. Baturitsky).
using an input discrete low-noise JFET and large value feedback resistor. However, such devices have large dimensions, and their cost is high. The increased number of channels in modern multi-detector IEP systems has accentuated the following requirements to the front-end electronics: a decrease of overall size, cost, dissipated power of preamplifiers, particularly if they are mounted on detectors placed in vacuum [1]. The best solution of the said problems is a multichannel ASIC designed for a specific detector, where optimum matching of the CSP with detector capacitance makes it possible to achieve low noise at low dissipated power, while ASIC decreases dimensions and costs. Unfortunately, any type of
0168-9002/03/$ - see front matter r 2003 Published by Elsevier Science B.V. PII: S 0 1 6 8 - 9 0 0 2 ( 0 2 ) 0 1 6 1 3 - 3
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
163
detector requires its own specific ASIC. The purpose of this work is to create a more universal and non-expensive chip family for IEP front-end electronics. For this purpose the following decisions have been made: *
*
*
*
*
*
*
The functionally completed front-end channel has been divided into two parts: a CSP (ZENIT-A) and a shaper (ZENIT-B), each ASIC containing 8 channels. Such configuration permits to place the shapers outside the detector thus decreasing its heating and to use the shapers with different preamplifiers. Two versions of the 8-channel preamplifier ASIC have been implemented, each having a step gain control and, hence, its own maximum limits of input charge, namely: 717, 750 pC for ZENIT-A2 and 74, 78 pC for ZENIT-A3. Each CSP channel has a 1 pF capacitor embedded to test operability; the test capacitors of odd and even channels are connected together with separate outputs. The shaper ASIC has slow and fast shaped signal outputs. All the ASICs can process input signals of both polarities and allow smooth adjustment of the operation mode. The shaper makes it possible to correct a signal pulse shape at the slow output due to different conditions of the pole-zero-cancellation. The ASICs have been implemented using BJTJFET technology [2], which provides good yield and low cost. Inserting of filtering capacitors and current setting resistors into the chips has reduced dramatically the number of external components required for performance of the ASICs and has decreased overall electronics channel price at PCB.
Fig. 1. The CSP simplified circuit diagram. CF1 ¼ 5 pF, CF2 ¼ 10 pF for ZENIT-A2; CF1 ¼ CF2 ¼ 1 pF for ZENIT-A3.
designed taking into account the following two conditions: *
*
The pJFET is selected as the input transistor J1. Its channel width to length ratio is 800/1.5, drain current in operation mode is ID ¼ 1:2 mA, transconductance gM ¼ 2:6 mA/V. This choice has been made due to following reasons: *
2. Schematics 2.1. The charge sensitive preamplifiers A simplified diagram of one channel of the circuit is shown in Fig. 1. The CSP is an inverting voltage amplifier with frequency dependent negative feedback (RF ; CF1 ; CF2 ). The CSP was
Operation in spectrometric channels with peaking time TP ¼ ð0:521:5Þ ms. A reduced power and increased speed compared with LeCroy’s 8-channel preamplifiers HQV802-M, HQV810, HQV820 [3].
The decrease of the parallel equivalent noise charge (ENC) caused by input bias current of the input stage (IBIAS ) for peaking time TP ¼ ð0:521:5Þ ms is possible only by using the input FET because the RC-CR shaper parallel noise component equals [4]: e pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qTP IBIAS ENCIBIAS ¼ ð1Þ 2q where e ¼ 2:718; q is the electron charge.
164 *
*
*
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
JFETs have substantially less flicker noise compared with MOSFETs. The contribution of flicker noise component to total noise becomes particularly significant at a large detector capacitance. Usually nJFET’s transconductance is larger than that of pJFET because the mobility of electrons is higher than the one of holes. However, pJFET has good compatibility with bipolar technology [2] and does not increase the IC cost. The increase of pJFET area and operation current ID causes the increase of maximal transconductance and the decrease of series ENC caused by JFET drain current shot noise [4]: e ENCGM ¼ ðCD þ CF þ CI Þ q sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffi kT IDMAX ð2Þ 3TP gMMAX ID where CD is detector capacitance; CF ; CI are feedback and input capacitance of CSP, respectively; k is the Boltzmann constant; T is the absolute temperature; IDMAX is the maximum drain current, gMMAX is the maximum transconductance at ID ¼ IDMAX :
Minimization of series ENC for the specific detector capacitance is possible by matching the CSP input capacitance to the one of the detector, but since the aim was to create an universal CSP operating with both small and relatively large detector capacitances up to 300 pF, the main criterion for choosing the input pJFET area and operation drain current was to provide high speed at a relatively small dissipated power. The input stage is made as a single ended folded cascode J1, J2, Q1, R2 loaded by the cascode current source R4, Q2, J4. The folded cascode makes it possible to use a power supply voltage range more efficiently than an ordinary common source stage, thus providing a wider dynamic range. Combined with the active cascode load, the folded cascode provides a greater open loop voltage gain and maintains CSP gain at a larger detector capacitance. The cascode current source R4, Q2, J4 provides reproducible equality of
currents of the Q1 collector and J4 drain at acceptable pJFET-parameter technology dispersion with using reference voltage sources (designated Ref 1 and Ref 2 in Fig. 1) located in the bias block. By connecting external resistors we can set currents of the active load (the J4 drain) and the output follower U1 in the range of 20–600 mA. The drain current of the input transistor J1 consists of two components: the current flowing through R1 and the J2 source current given by the base potential of Q1 and R2. Such a choice makes it possible to set DC operation mode independently for the input transistor and the active load thus simplifying the CSP parametric optimization. Switching of an input signal admissible mode (gain) is carried out by the switch J3, R3, Q3, which inserts the CF2 into the feedback loop depending on the voltage level at the Q3 base (the SW bus), CF2 ¼ 10 pF, CF1 ¼ 5 pF for the CSP ‘‘ZENITA2’’, CF2 ¼ CF1 ¼ 1 pF for the CSP ‘‘ZENITA3’’. At 75 V power supply the CSPs available output voltage swing is 74 V, providing the following input signal conversion ability: *
*
717 pC (mode 1) and 750 pC (mode 2) for the CSP ‘‘ZENIT-A2’’; 74 pC (mode 1) and 78 pC (mode 2) for the CSP ‘‘ZENIT-A3’’.
When dealing with lower gain and/or single polarity of input signal we can decrease the negative voltage supply to 2.7 V and obtain a 30% decrease of power consumption. The feedback resistor RF was chosen to be 500 kO. Such a large value is needed to decrease the parallel noise component sffiffiffiffiffiffiffiffiffiffiffiffiffiffi e 2kTTP ENCRF ¼ ð3Þ 2q RF and to provide a signal decay time long enough to permit signal shaping with maximum peaking time TP ¼ 1:5 ms. However, the increase of RF value causes a substantial increase of the chip area and a decrease of the gain due to stray capacitances of the resistor. Implemented with 550 O/square p-base sheet resistance, the 500 kO resistor area is about 2.5 times greater than the total area of pJFETs J1 and J2.
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
Integrated pn-junction capacitors have a strong capacitance vs. voltage dependence [5], causing gain non-linearity in a wide dynamic range and substantial batch-to-batch gain dispersion due to dispersion of quiescent voltages. In order to operate in a wide dynamic range, one should use MOS capacitors having no capacitance vs. voltage dependence. However, MOS capacitors have smaller specific capacitance compared to pnjunction ones, therefore they occupy larger die area and have larger stray capacitance between semiconductor plate and the isolating well. The MOS-capacitor semiconductor plate is a p-type region located in the n-well. To provide electrical isolation the well is connected to the highest potential of the circuit [6]. The stray pn-junction is shown in Fig. 2 as the diode DSTR : The real capacitor CF forms a capacitance divider with capacitance CSTR of the reverse biased diode, 1:93CF CSTR ¼ 0:33 1 þ VD =VJO
ð4Þ
where VD is the voltage drop of the reverse biased diode DSTR ; VJO E0:8 V is pn-junction built-in potential; 1.93 is a coefficient showing the ratio between the specific pn-junction and MOS structure capacitance. At total capacitance CF1 þ CF2 ¼ 15 pF, 5 V power supply, and 1.6 V input quiescent voltage
165
the stray capacitance value is 16.7 pF. The large stray capacitance of integrated MOS capacitors used in the feedback loop of multi-channel CSPs can cause an increase of crosstalk, gain dispersion, and a decrease of tolerance to parasitic oscillation due to uncontrollable phase shift. In the process of the IC design these drawbacks have been eliminated by proper choice of a metal plate connection node (designated by square in the scheme) and partial compensation of MOS-capacitor straycapacitance influence on signal shape (Fig. 2). For this purpose two additional elements are used: a large value resistor RBIAS providing reverse bias at the DSTR ; and the MOS capacitor CADD of small but reproducible value, connected in series to the DSTR : For the operation mode 2 this method decreases the stray capacitance influence at high frequency part of the input signal (f > 6:4 MHz) by 30 times. The CSP output stage is a voltage follower. It can drive a capacitive load up to 250 pF for output signals of both polarities. The 1 pF capacitor CCLB connected to the input is needed for testing or calibration of the electronics channel with an error not more than 1%. The test capacitors of even and odd channels are joined together. 2.2. The shaper ZENIT-B consists of a CR-RC5 shaper in the slow channel and CR-RC in the fast one. The CR-RCn shaper step response is expressed by the following equation [7]: 1 t n ðt=RCÞ e ð5Þ VOUT ðtÞ ¼ K n! RC where n is the number of RC sections used in the shaper; K is the voltage gain. The peaking time of the pulse is given by TP ¼ nRC:
Fig. 2. The stray capacitance cancellation circuit.
ð6Þ
The output pulse can be approached to the ideal Gaussian shape by increasing n; thus providing the best signal-to-noise ratio, but at the cost of an increase of power consumption. The optimum number of RC sections with regard to signal-tonoise enhancement and power dissipation is n ¼ 4 [7]. However, to provide greater tolerance to
166
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
Fig. 3. The shaper one channel simplified circuit.
parasitic oscillation it would be useful to invert the output signal as referred to the input. For this purpose, as well as to increase the signal-to-noise ratio, a CR-RC5 shaping has been chosen in the slow channel. The input signal of the shaper from the CSP output enters the differentiation circuit C1R4 (Fig. 3) with a pole-zero-cancellation, PZC, consisting of R1–R3, with R5 switched by Q1 and Q2. Their external base-control signals come from the bonding pads A1 and A2, allowing to carry out both discrete and smooth adjustment of the PZC for CSPs having different feedback-loop timeconstants. After differentiation the signal passes sequentially through the five cascaded low-pass filters, U1–U5, and the output follower, U6. Each U1–U5 element is a single stage inverting voltage amplifier with identical layout on the chip. This amplifier (Fig. 4) has an input low-signal pJFET J1, a cascode npn Q2, an active load in the form of a combined stage R3, J2, Q3, and an output emitter follower, R2, Q4, Q5. The value of quiescent mode DC current is identical for all the channels and stages and is set through three buses (designated
Ref 1 and Ref 2 in Fig. 4), and VSS : The use of pJFET at the input simplifies cascading of the filter stages, since the DC voltage shift between stages is insignificant. This shift is produced by J1 gate leakage current (a few tens of pA) and depends on the values of interstage and feedback resistors, with the total resistance not exceeding 100 kO. In comparison with the slow channel described, the fast channel is much simpler; it consists of only one amplifier stage, U7, with approximately 50 ns integration time.
3. Measurement results To measure the main characteristics of the chips we connected a 10 ms pulse with 0.25 ns leading edge from a pulse generator through the 16 pF calibration capacitor to the input of the amplifier. Its output was connected to the input of the shaper. The output signals were registered by a digital scope. Summary characteristics of the multi-channel preamplifier/shaper chip family at 75 V power
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
167
Table 1 Parameters of the CSP Parameters
ZENIT-A2
Number of channels Power supply
8 VCC ¼ þ3 to +7 V VEE ¼ 3 to 5 V 13 mW/channel Positive, negative 150 pF (mode 1) 300 pF (mode 2) 717, 750 pC (74, 7 8 pC for ZENITA3) 74 V
Power consumption (75 V) Input signal polarity Maximum input capacitance Maximum input charge
Maximum output voltage swing Output signal rise time
Output signal decay time constant Output signal polarity Gain at CD ¼ 27 pF
Fig. 4. The shaper typical inverting amplifier circuit.
supply are presented in Tables 1 and 2. Circuit and layout characteristics of the chips made it possible to decrease channel-to-channel gain variations in a single amplifier chip to 70.7% and 72.0% for a shaper one, while the wafer-to-wafer gain variations are not larger than 75.0%. One of the most important CSP features is the dependence of the output signal amplitude and rise time on input capacitance, which can prevent following signal shaping with required peaking time. It can also decrease the overall gain. Therefore we have determined maximum input capacitance by a 10–15% decrease of the gain and the similar increase of the signal rise time, which are considered to be acceptable for practical applications because they do not modify signal substantially after shaping with TP ¼ 0:5 ms. In operation mode 1 the ZENIT-A2 can operate with detector capacitance up to 150 pF: rise time is increased up to 25 ns and gain is decreased by 11.3% (Figs. 5
Integral non-linearity, typical Package
4.5+0.14 ns per pF of input capacitance (mode 1) 20+0.07 ns per pF of input capacitance (mode 2) 2.5, 7.5 ms (0.5, 1.0 ms for ZENIT-A3) Inverting 0.24 V/pC7 5%, 0.08 V/ pC75% (1 V/pC7 5%, 0.5 V/pC 75% for ZENIT-A3) 1.5% for the 4 to 4 V output signal swing 24/28-Pin, planar, doubleside
Table 2 Parameters of the shaper Parameter
Value
Number of channels
8, each has two outputs: fast and slow VCC ¼ þ5 to + 7 V VEE ¼ 5 to 7 V 44 mW/ channel 74 V 73 V 0.7575% 1.575% >0.5 ms >50 ns Step and smooth control by voltage Smooth control by voltage 42/48-Pin, planar, quad-side
Power supply Power consumption (75 V) Maximum input voltage Maximum output voltage Slow output voltage gain Fast output voltage gain Slow output peaking time Fast output peaking time PZC adjustment Output base line adjustment Package
168
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
Fig. 5. The ZENIT-A2 rise time vs. detector capacitance. Mode 1, QINP ¼ 8 pC.
Fig. 7. Output signals of the shaper during PZC mode changing. Mode 1, CD ¼ 27 pF, QINP ¼ þ4 pC. Input signal (curve 1) comes from ZENIT-A2. Curve 2: the switch Q1 is off (A1=OFF), the switch Q2 is on (A2=ON) (see Fig. 3). Curve 3: A1=ON, A2=OFF. Curve 4: A1=OFF, A2=OFF.
Fig. 6. The ZENIT-A2 conversion gain vs. detector capacitance. Mode 1, QINP ¼ 8 pC.
and 6), and in operation mode 2—up to 300 pF, with 10% gain degradation and 41 ns rise time. Output signals of the shaper following the CSP operating in modes 1 and 2 are shown in Figs. 7 and 8, respectively, for different PZC conditions. The ratio of resistors switched by switches Q1 and Q2 is 4:1. To minimize the negative overshoot in mode 1 Q1 must be switched on (A1=ON) with Q2 switched off (A2=OFF), and inversely for mode 2. When the two switches are OFF, it is possible to provide PZC for preamplifiers with feedback loop time constant 1.5 ms. The circuit provides smooth adjustment of PZC. In this case the transistors Q1 and Q2 operate in a linear mode.
Fig. 8. Output signals of the shaper during PZC mode changing. Mode 2, CD ¼ 27 pF, QINP ¼ þ12 pC. Input signal (curve 1) comes from ZENIT-A2. Curve 2: the switch Q1 is off (A1=OFF), the switch Q2 is on (A2=ON) (see Fig. 3). Curve 3: A1=ON, A2=OFF. Curve 4: A1=OFF, A2=OFF.
Crosstalks have been measured for the ASIC preamplifier-shaper channel. The chips have been mounted in metal-ceramic packages with pin pitch 1.25 mm for the amplifiers and 1.0 mm for the shapers. The ASICs were placed on the PCB with the ground backside. Preamplifier inputs were connected to 30 mm metal lines simulating detector connection wiring. Length of lines from preamplifier outputs to shaper inputs was 50 mm.
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
169
Fig. 9. The input charge/output voltage conversion for the ASIC channel (preamplifier Zenit-A2, operating at mode 1, and the shaper) at detector capacitance 150 pF and VCC ¼ þ7 V, VEE ¼ 5 V.
The 8 pC test signal charge was applied to the preamplifier input through a 15 pF capacitor. Crosstalk levels measured at adjacent output pins of the shaper were 52 dB at zero input capacitance and 56 dB at 150 pF. Such small crosstalks are explained by special measures undertaken in layout of the chips [8,9]. A deviation of the input charge-to-output voltage conversion from linearity has been measured using a precision-amplitude generator, a stable 15 pF calibration capacitor and a digital oscilloscope providing 0.2% total error of the charge/voltage conversion. The detector capacitance was 150 pF, VCC ¼ þ7 V, VEE ¼ 5 V. The conversion curve for the ASIC channel (preamplifier Zenit-A2 operating in mode 1 and the shaper Zenit-B) is shown in Fig. 9. Fig. 10 shows the deviation of the conversion linearity. The linearity deviation is less than 0.3% up to 10 pC input charge and varies to 7% at 16 pC. The performances of the ZENIT ASIC family are illustrated in Figs. 11–13. Fig. 11 presents a test bench used to investigate operation of the ASICs connected to a real detector. The Zenit-A2 CSP with 0.24 V/pC gain was connected to a silicon detector (20 20 0.4 mm3 dimensions, 120 pF capacitance; 12 nA leakage current at reverse voltage bias 120 V at room temperature and normal pressure), irradiated by a-particles
Fig. 10. The charge–voltage conversion deviation from linearity for the ASIC channel at the conditions of Fig. 9.
Fig. 11. The ASIC test bench with a silicon detector. Preamplifier gain 0.24 V/pC. Two shaper options (TP ¼ 500 ns): (1) CAMAC with voltage gain K ¼ 22:5 dB and (2) ZENIT-B with K ¼ 2:5 dB.
170
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
Fig. 12. The energy spectrum of 226Ra measured using the silicon detector 20 20 0.4 mm3 with the ASICs ZENIT-A2 and CAMAC amplifier/shaper. TP ¼ 0:5 ms, K ¼ 22:5 dB.
Fig. 13. The energy spectrum of 226Ra measured using the silicon detector 20 20 0.4 mm3 with the ASIC channel (ZENIT-A2 and ZENIT-B). TP ¼ 0:5 ms, K ¼ 2:5 dB.
from 226Ra placed directly on the front side (p+ contact) of the detector. The CSP output signal was shaped by a commercially available CAMAC shaper with TP ¼ 0:5 ms and voltage gain K ¼ 22:5 dB (the spectrum in Fig. 12) or the Zenit-B shaper with the same peaking time and K ¼ 2:5 dB (the spectrum in Fig. 13). A 12-bit ADC digitized the shaper output signal. The total energy resolution determined at the 7.69 MeV peak (Fig. 12) is D5=38 keV (FWHM). It depends on detector and preamplifier noises, external interferences, and the a-source/detector geometry as well. The right-hand peak in Fig. 12 corresponds to a calibration pulse equivalent to 9.44 MeV particle energy with DTEST ¼ 28 keV. The contribution of the detector noise and the measurement geometry can be estimated as qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi DD ¼ D25 D2TEST E26 keV. Fig. 13 shows the spectrum of the same isotope measured using the front-end channel made of
fully ASICs. For 120 pF detector capacitance the noise performance is quite well for practical purposes taking into account the large dynamic range (from 4 to 9 MeV) and 73 V power supply. The increase of DTEST from 28 keV in Fig. 12 to 59 keV in Fig. 13 is explained by uncontrolled electromagnetic interference added to less amplified signal (the CAMAC shaper has the 20 dB gain while Zenit-B has 2.5 dB) rather than the intrinsic noise of Zenit-B. 4. Conclusions The 8-channel charge sensitive preamplifiers ZENIT-A2, ZENIT-A3 and the 8-channel shaper ZENIT-B ASICs have been designed for front-end electronics used in Intermediate Energy Physics. In order to extend the number of applications a gain control circuit is embedded into the preamplifiers; a tuneable PZC circuit is used in the shaper. The
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
preamplifiers can operate at detector capacitance up to 300 pF (with 10% gain degradation) and maximum input charge up to 750 pC. The CRRC5 shaper provides B600 ns peaking time. The ASICs can drive a large capacitive load providing maximal amplitude of output signal not less than 74 V for the preamplifiers and 73 V for the shaper. The ASIC family described seems to cover a large part of IEP applications.
References [1] N. Randazzo, et al., Nucl. Instr. and Meth. A 420 (1999) 279.
171
[2] M.A. Baturitsky, et al., Nucl. Instr. and Meth. A 378 (1996) 570. [3] LeCroy Research Systems, 1996 Catalog. [4] M.A. Baturitsky, O.V. Dvornikov, Nucl. Instr. and Meth. A 378 (1996) 564. [5] S.M. Sze, Physics of Semiconductor Devices, 2nd Edition, Wiley-Interscience Publication, New York, 1981. [6] M.A. Baturitsky, O.V. Dvornikov, Nucl. Instr. and Meth. A 398 (1997) 308. [7] P.D. Walker, M.M. Green, IEEE J. Solid-State Circ. 31 (6) (1996) 850. [8] M.A. Baturitsky, O.V. Dvornikov, Nucl. Instr. and Meth. A 398 (1997) 308. [9] G.D. Alexeev, et al., Nucl. Instr. and Meth. A 462 (2001) 494.
A wide dynamic range multi-channel preamplifier/shaper ASIC family for universal low power applications M.A. Baturitskya,*, O.V. Dvornikovb, V.A. Tchekhovskib, N.I. Zamiatinc b
a The Institute of Nuclear Problems, Belarusian State University, Bobruiskaya street 11, Minsk 220050, Belarus The National Scientific and Educational Centre of Particle and High Energy Physics of the Belarusian State University, M. Bogdanovich street 153, Minsk 220040, Belarus c The Joint Institute for Nuclear Research, Dubna, Moscow district 141980, Russia
Received 3 June 2002; received in revised form 26 August 2002; accepted 27 August 2002
Abstract A universal ASIC family for intermediate energy physics detectors has been designed using a bipolar/JFET technology. The family consists of two 8-channel charge-sensitive preamplifiers (CSP) ZENIT-A2, ZENIT-A3 and a shaper ZENIT-B. The values of switched gain of both CSPs are 80 and 240 mV/pC for ZENIT-A2 and 500 and 1000 mV/pC for ZENIT-A3 with channel-to-channel non-identity not more than 75%. The CSPs can operate with input capacitance up to 300 pF for low gain and 150 pF for high gain mode. The input signal dynamic range of the shaper is matched to the outputs of both CSPs. The shaper has fast and slow outputs. The CSPs have a power consumption of 13 mW/channel; the shaper of 44 mW/channel. r 2003 Published by Elsevier Science B.V. Keywords: Charge sensitive preamplifier; Wide dynamic range; Shaper; Multi-channel ASIC
1. Introduction The main difference between front-end electronics used in Intermediate Energy Physics (IEP) and High Energy Physics (HEP) is a large input signal dynamic range of 80–100 dB, large detector capacitances of a few hundreds of picofarads, and large peaking times used to obtain low noise. The relatively small number of channels allows hybrid implementation of the IEP front-end electronics permitting to get extremely low noise values by *Corresponding author. Tel.: +375-172-208481; fax: +375172-263668. E-mail address: [email protected] (M.A. Baturitsky).
using an input discrete low-noise JFET and large value feedback resistor. However, such devices have large dimensions, and their cost is high. The increased number of channels in modern multi-detector IEP systems has accentuated the following requirements to the front-end electronics: a decrease of overall size, cost, dissipated power of preamplifiers, particularly if they are mounted on detectors placed in vacuum [1]. The best solution of the said problems is a multichannel ASIC designed for a specific detector, where optimum matching of the CSP with detector capacitance makes it possible to achieve low noise at low dissipated power, while ASIC decreases dimensions and costs. Unfortunately, any type of
0168-9002/03/$ - see front matter r 2003 Published by Elsevier Science B.V. PII: S 0 1 6 8 - 9 0 0 2 ( 0 2 ) 0 1 6 1 3 - 3
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
163
detector requires its own specific ASIC. The purpose of this work is to create a more universal and non-expensive chip family for IEP front-end electronics. For this purpose the following decisions have been made: *
*
*
*
*
*
*
The functionally completed front-end channel has been divided into two parts: a CSP (ZENIT-A) and a shaper (ZENIT-B), each ASIC containing 8 channels. Such configuration permits to place the shapers outside the detector thus decreasing its heating and to use the shapers with different preamplifiers. Two versions of the 8-channel preamplifier ASIC have been implemented, each having a step gain control and, hence, its own maximum limits of input charge, namely: 717, 750 pC for ZENIT-A2 and 74, 78 pC for ZENIT-A3. Each CSP channel has a 1 pF capacitor embedded to test operability; the test capacitors of odd and even channels are connected together with separate outputs. The shaper ASIC has slow and fast shaped signal outputs. All the ASICs can process input signals of both polarities and allow smooth adjustment of the operation mode. The shaper makes it possible to correct a signal pulse shape at the slow output due to different conditions of the pole-zero-cancellation. The ASICs have been implemented using BJTJFET technology [2], which provides good yield and low cost. Inserting of filtering capacitors and current setting resistors into the chips has reduced dramatically the number of external components required for performance of the ASICs and has decreased overall electronics channel price at PCB.
Fig. 1. The CSP simplified circuit diagram. CF1 ¼ 5 pF, CF2 ¼ 10 pF for ZENIT-A2; CF1 ¼ CF2 ¼ 1 pF for ZENIT-A3.
designed taking into account the following two conditions: *
*
The pJFET is selected as the input transistor J1. Its channel width to length ratio is 800/1.5, drain current in operation mode is ID ¼ 1:2 mA, transconductance gM ¼ 2:6 mA/V. This choice has been made due to following reasons: *
2. Schematics 2.1. The charge sensitive preamplifiers A simplified diagram of one channel of the circuit is shown in Fig. 1. The CSP is an inverting voltage amplifier with frequency dependent negative feedback (RF ; CF1 ; CF2 ). The CSP was
Operation in spectrometric channels with peaking time TP ¼ ð0:521:5Þ ms. A reduced power and increased speed compared with LeCroy’s 8-channel preamplifiers HQV802-M, HQV810, HQV820 [3].
The decrease of the parallel equivalent noise charge (ENC) caused by input bias current of the input stage (IBIAS ) for peaking time TP ¼ ð0:521:5Þ ms is possible only by using the input FET because the RC-CR shaper parallel noise component equals [4]: e pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qTP IBIAS ENCIBIAS ¼ ð1Þ 2q where e ¼ 2:718; q is the electron charge.
164 *
*
*
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
JFETs have substantially less flicker noise compared with MOSFETs. The contribution of flicker noise component to total noise becomes particularly significant at a large detector capacitance. Usually nJFET’s transconductance is larger than that of pJFET because the mobility of electrons is higher than the one of holes. However, pJFET has good compatibility with bipolar technology [2] and does not increase the IC cost. The increase of pJFET area and operation current ID causes the increase of maximal transconductance and the decrease of series ENC caused by JFET drain current shot noise [4]: e ENCGM ¼ ðCD þ CF þ CI Þ q sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffi kT IDMAX ð2Þ 3TP gMMAX ID where CD is detector capacitance; CF ; CI are feedback and input capacitance of CSP, respectively; k is the Boltzmann constant; T is the absolute temperature; IDMAX is the maximum drain current, gMMAX is the maximum transconductance at ID ¼ IDMAX :
Minimization of series ENC for the specific detector capacitance is possible by matching the CSP input capacitance to the one of the detector, but since the aim was to create an universal CSP operating with both small and relatively large detector capacitances up to 300 pF, the main criterion for choosing the input pJFET area and operation drain current was to provide high speed at a relatively small dissipated power. The input stage is made as a single ended folded cascode J1, J2, Q1, R2 loaded by the cascode current source R4, Q2, J4. The folded cascode makes it possible to use a power supply voltage range more efficiently than an ordinary common source stage, thus providing a wider dynamic range. Combined with the active cascode load, the folded cascode provides a greater open loop voltage gain and maintains CSP gain at a larger detector capacitance. The cascode current source R4, Q2, J4 provides reproducible equality of
currents of the Q1 collector and J4 drain at acceptable pJFET-parameter technology dispersion with using reference voltage sources (designated Ref 1 and Ref 2 in Fig. 1) located in the bias block. By connecting external resistors we can set currents of the active load (the J4 drain) and the output follower U1 in the range of 20–600 mA. The drain current of the input transistor J1 consists of two components: the current flowing through R1 and the J2 source current given by the base potential of Q1 and R2. Such a choice makes it possible to set DC operation mode independently for the input transistor and the active load thus simplifying the CSP parametric optimization. Switching of an input signal admissible mode (gain) is carried out by the switch J3, R3, Q3, which inserts the CF2 into the feedback loop depending on the voltage level at the Q3 base (the SW bus), CF2 ¼ 10 pF, CF1 ¼ 5 pF for the CSP ‘‘ZENITA2’’, CF2 ¼ CF1 ¼ 1 pF for the CSP ‘‘ZENITA3’’. At 75 V power supply the CSPs available output voltage swing is 74 V, providing the following input signal conversion ability: *
*
717 pC (mode 1) and 750 pC (mode 2) for the CSP ‘‘ZENIT-A2’’; 74 pC (mode 1) and 78 pC (mode 2) for the CSP ‘‘ZENIT-A3’’.
When dealing with lower gain and/or single polarity of input signal we can decrease the negative voltage supply to 2.7 V and obtain a 30% decrease of power consumption. The feedback resistor RF was chosen to be 500 kO. Such a large value is needed to decrease the parallel noise component sffiffiffiffiffiffiffiffiffiffiffiffiffiffi e 2kTTP ENCRF ¼ ð3Þ 2q RF and to provide a signal decay time long enough to permit signal shaping with maximum peaking time TP ¼ 1:5 ms. However, the increase of RF value causes a substantial increase of the chip area and a decrease of the gain due to stray capacitances of the resistor. Implemented with 550 O/square p-base sheet resistance, the 500 kO resistor area is about 2.5 times greater than the total area of pJFETs J1 and J2.
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
Integrated pn-junction capacitors have a strong capacitance vs. voltage dependence [5], causing gain non-linearity in a wide dynamic range and substantial batch-to-batch gain dispersion due to dispersion of quiescent voltages. In order to operate in a wide dynamic range, one should use MOS capacitors having no capacitance vs. voltage dependence. However, MOS capacitors have smaller specific capacitance compared to pnjunction ones, therefore they occupy larger die area and have larger stray capacitance between semiconductor plate and the isolating well. The MOS-capacitor semiconductor plate is a p-type region located in the n-well. To provide electrical isolation the well is connected to the highest potential of the circuit [6]. The stray pn-junction is shown in Fig. 2 as the diode DSTR : The real capacitor CF forms a capacitance divider with capacitance CSTR of the reverse biased diode, 1:93CF CSTR ¼ 0:33 1 þ VD =VJO
ð4Þ
where VD is the voltage drop of the reverse biased diode DSTR ; VJO E0:8 V is pn-junction built-in potential; 1.93 is a coefficient showing the ratio between the specific pn-junction and MOS structure capacitance. At total capacitance CF1 þ CF2 ¼ 15 pF, 5 V power supply, and 1.6 V input quiescent voltage
165
the stray capacitance value is 16.7 pF. The large stray capacitance of integrated MOS capacitors used in the feedback loop of multi-channel CSPs can cause an increase of crosstalk, gain dispersion, and a decrease of tolerance to parasitic oscillation due to uncontrollable phase shift. In the process of the IC design these drawbacks have been eliminated by proper choice of a metal plate connection node (designated by square in the scheme) and partial compensation of MOS-capacitor straycapacitance influence on signal shape (Fig. 2). For this purpose two additional elements are used: a large value resistor RBIAS providing reverse bias at the DSTR ; and the MOS capacitor CADD of small but reproducible value, connected in series to the DSTR : For the operation mode 2 this method decreases the stray capacitance influence at high frequency part of the input signal (f > 6:4 MHz) by 30 times. The CSP output stage is a voltage follower. It can drive a capacitive load up to 250 pF for output signals of both polarities. The 1 pF capacitor CCLB connected to the input is needed for testing or calibration of the electronics channel with an error not more than 1%. The test capacitors of even and odd channels are joined together. 2.2. The shaper ZENIT-B consists of a CR-RC5 shaper in the slow channel and CR-RC in the fast one. The CR-RCn shaper step response is expressed by the following equation [7]: 1 t n ðt=RCÞ e ð5Þ VOUT ðtÞ ¼ K n! RC where n is the number of RC sections used in the shaper; K is the voltage gain. The peaking time of the pulse is given by TP ¼ nRC:
Fig. 2. The stray capacitance cancellation circuit.
ð6Þ
The output pulse can be approached to the ideal Gaussian shape by increasing n; thus providing the best signal-to-noise ratio, but at the cost of an increase of power consumption. The optimum number of RC sections with regard to signal-tonoise enhancement and power dissipation is n ¼ 4 [7]. However, to provide greater tolerance to
166
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
Fig. 3. The shaper one channel simplified circuit.
parasitic oscillation it would be useful to invert the output signal as referred to the input. For this purpose, as well as to increase the signal-to-noise ratio, a CR-RC5 shaping has been chosen in the slow channel. The input signal of the shaper from the CSP output enters the differentiation circuit C1R4 (Fig. 3) with a pole-zero-cancellation, PZC, consisting of R1–R3, with R5 switched by Q1 and Q2. Their external base-control signals come from the bonding pads A1 and A2, allowing to carry out both discrete and smooth adjustment of the PZC for CSPs having different feedback-loop timeconstants. After differentiation the signal passes sequentially through the five cascaded low-pass filters, U1–U5, and the output follower, U6. Each U1–U5 element is a single stage inverting voltage amplifier with identical layout on the chip. This amplifier (Fig. 4) has an input low-signal pJFET J1, a cascode npn Q2, an active load in the form of a combined stage R3, J2, Q3, and an output emitter follower, R2, Q4, Q5. The value of quiescent mode DC current is identical for all the channels and stages and is set through three buses (designated
Ref 1 and Ref 2 in Fig. 4), and VSS : The use of pJFET at the input simplifies cascading of the filter stages, since the DC voltage shift between stages is insignificant. This shift is produced by J1 gate leakage current (a few tens of pA) and depends on the values of interstage and feedback resistors, with the total resistance not exceeding 100 kO. In comparison with the slow channel described, the fast channel is much simpler; it consists of only one amplifier stage, U7, with approximately 50 ns integration time.
3. Measurement results To measure the main characteristics of the chips we connected a 10 ms pulse with 0.25 ns leading edge from a pulse generator through the 16 pF calibration capacitor to the input of the amplifier. Its output was connected to the input of the shaper. The output signals were registered by a digital scope. Summary characteristics of the multi-channel preamplifier/shaper chip family at 75 V power
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
167
Table 1 Parameters of the CSP Parameters
ZENIT-A2
Number of channels Power supply
8 VCC ¼ þ3 to +7 V VEE ¼ 3 to 5 V 13 mW/channel Positive, negative 150 pF (mode 1) 300 pF (mode 2) 717, 750 pC (74, 7 8 pC for ZENITA3) 74 V
Power consumption (75 V) Input signal polarity Maximum input capacitance Maximum input charge
Maximum output voltage swing Output signal rise time
Output signal decay time constant Output signal polarity Gain at CD ¼ 27 pF
Fig. 4. The shaper typical inverting amplifier circuit.
supply are presented in Tables 1 and 2. Circuit and layout characteristics of the chips made it possible to decrease channel-to-channel gain variations in a single amplifier chip to 70.7% and 72.0% for a shaper one, while the wafer-to-wafer gain variations are not larger than 75.0%. One of the most important CSP features is the dependence of the output signal amplitude and rise time on input capacitance, which can prevent following signal shaping with required peaking time. It can also decrease the overall gain. Therefore we have determined maximum input capacitance by a 10–15% decrease of the gain and the similar increase of the signal rise time, which are considered to be acceptable for practical applications because they do not modify signal substantially after shaping with TP ¼ 0:5 ms. In operation mode 1 the ZENIT-A2 can operate with detector capacitance up to 150 pF: rise time is increased up to 25 ns and gain is decreased by 11.3% (Figs. 5
Integral non-linearity, typical Package
4.5+0.14 ns per pF of input capacitance (mode 1) 20+0.07 ns per pF of input capacitance (mode 2) 2.5, 7.5 ms (0.5, 1.0 ms for ZENIT-A3) Inverting 0.24 V/pC7 5%, 0.08 V/ pC75% (1 V/pC7 5%, 0.5 V/pC 75% for ZENIT-A3) 1.5% for the 4 to 4 V output signal swing 24/28-Pin, planar, doubleside
Table 2 Parameters of the shaper Parameter
Value
Number of channels
8, each has two outputs: fast and slow VCC ¼ þ5 to + 7 V VEE ¼ 5 to 7 V 44 mW/ channel 74 V 73 V 0.7575% 1.575% >0.5 ms >50 ns Step and smooth control by voltage Smooth control by voltage 42/48-Pin, planar, quad-side
Power supply Power consumption (75 V) Maximum input voltage Maximum output voltage Slow output voltage gain Fast output voltage gain Slow output peaking time Fast output peaking time PZC adjustment Output base line adjustment Package
168
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
Fig. 5. The ZENIT-A2 rise time vs. detector capacitance. Mode 1, QINP ¼ 8 pC.
Fig. 7. Output signals of the shaper during PZC mode changing. Mode 1, CD ¼ 27 pF, QINP ¼ þ4 pC. Input signal (curve 1) comes from ZENIT-A2. Curve 2: the switch Q1 is off (A1=OFF), the switch Q2 is on (A2=ON) (see Fig. 3). Curve 3: A1=ON, A2=OFF. Curve 4: A1=OFF, A2=OFF.
Fig. 6. The ZENIT-A2 conversion gain vs. detector capacitance. Mode 1, QINP ¼ 8 pC.
and 6), and in operation mode 2—up to 300 pF, with 10% gain degradation and 41 ns rise time. Output signals of the shaper following the CSP operating in modes 1 and 2 are shown in Figs. 7 and 8, respectively, for different PZC conditions. The ratio of resistors switched by switches Q1 and Q2 is 4:1. To minimize the negative overshoot in mode 1 Q1 must be switched on (A1=ON) with Q2 switched off (A2=OFF), and inversely for mode 2. When the two switches are OFF, it is possible to provide PZC for preamplifiers with feedback loop time constant 1.5 ms. The circuit provides smooth adjustment of PZC. In this case the transistors Q1 and Q2 operate in a linear mode.
Fig. 8. Output signals of the shaper during PZC mode changing. Mode 2, CD ¼ 27 pF, QINP ¼ þ12 pC. Input signal (curve 1) comes from ZENIT-A2. Curve 2: the switch Q1 is off (A1=OFF), the switch Q2 is on (A2=ON) (see Fig. 3). Curve 3: A1=ON, A2=OFF. Curve 4: A1=OFF, A2=OFF.
Crosstalks have been measured for the ASIC preamplifier-shaper channel. The chips have been mounted in metal-ceramic packages with pin pitch 1.25 mm for the amplifiers and 1.0 mm for the shapers. The ASICs were placed on the PCB with the ground backside. Preamplifier inputs were connected to 30 mm metal lines simulating detector connection wiring. Length of lines from preamplifier outputs to shaper inputs was 50 mm.
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
169
Fig. 9. The input charge/output voltage conversion for the ASIC channel (preamplifier Zenit-A2, operating at mode 1, and the shaper) at detector capacitance 150 pF and VCC ¼ þ7 V, VEE ¼ 5 V.
The 8 pC test signal charge was applied to the preamplifier input through a 15 pF capacitor. Crosstalk levels measured at adjacent output pins of the shaper were 52 dB at zero input capacitance and 56 dB at 150 pF. Such small crosstalks are explained by special measures undertaken in layout of the chips [8,9]. A deviation of the input charge-to-output voltage conversion from linearity has been measured using a precision-amplitude generator, a stable 15 pF calibration capacitor and a digital oscilloscope providing 0.2% total error of the charge/voltage conversion. The detector capacitance was 150 pF, VCC ¼ þ7 V, VEE ¼ 5 V. The conversion curve for the ASIC channel (preamplifier Zenit-A2 operating in mode 1 and the shaper Zenit-B) is shown in Fig. 9. Fig. 10 shows the deviation of the conversion linearity. The linearity deviation is less than 0.3% up to 10 pC input charge and varies to 7% at 16 pC. The performances of the ZENIT ASIC family are illustrated in Figs. 11–13. Fig. 11 presents a test bench used to investigate operation of the ASICs connected to a real detector. The Zenit-A2 CSP with 0.24 V/pC gain was connected to a silicon detector (20 20 0.4 mm3 dimensions, 120 pF capacitance; 12 nA leakage current at reverse voltage bias 120 V at room temperature and normal pressure), irradiated by a-particles
Fig. 10. The charge–voltage conversion deviation from linearity for the ASIC channel at the conditions of Fig. 9.
Fig. 11. The ASIC test bench with a silicon detector. Preamplifier gain 0.24 V/pC. Two shaper options (TP ¼ 500 ns): (1) CAMAC with voltage gain K ¼ 22:5 dB and (2) ZENIT-B with K ¼ 2:5 dB.
170
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
Fig. 12. The energy spectrum of 226Ra measured using the silicon detector 20 20 0.4 mm3 with the ASICs ZENIT-A2 and CAMAC amplifier/shaper. TP ¼ 0:5 ms, K ¼ 22:5 dB.
Fig. 13. The energy spectrum of 226Ra measured using the silicon detector 20 20 0.4 mm3 with the ASIC channel (ZENIT-A2 and ZENIT-B). TP ¼ 0:5 ms, K ¼ 2:5 dB.
from 226Ra placed directly on the front side (p+ contact) of the detector. The CSP output signal was shaped by a commercially available CAMAC shaper with TP ¼ 0:5 ms and voltage gain K ¼ 22:5 dB (the spectrum in Fig. 12) or the Zenit-B shaper with the same peaking time and K ¼ 2:5 dB (the spectrum in Fig. 13). A 12-bit ADC digitized the shaper output signal. The total energy resolution determined at the 7.69 MeV peak (Fig. 12) is D5=38 keV (FWHM). It depends on detector and preamplifier noises, external interferences, and the a-source/detector geometry as well. The right-hand peak in Fig. 12 corresponds to a calibration pulse equivalent to 9.44 MeV particle energy with DTEST ¼ 28 keV. The contribution of the detector noise and the measurement geometry can be estimated as qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi DD ¼ D25 D2TEST E26 keV. Fig. 13 shows the spectrum of the same isotope measured using the front-end channel made of
fully ASICs. For 120 pF detector capacitance the noise performance is quite well for practical purposes taking into account the large dynamic range (from 4 to 9 MeV) and 73 V power supply. The increase of DTEST from 28 keV in Fig. 12 to 59 keV in Fig. 13 is explained by uncontrolled electromagnetic interference added to less amplified signal (the CAMAC shaper has the 20 dB gain while Zenit-B has 2.5 dB) rather than the intrinsic noise of Zenit-B. 4. Conclusions The 8-channel charge sensitive preamplifiers ZENIT-A2, ZENIT-A3 and the 8-channel shaper ZENIT-B ASICs have been designed for front-end electronics used in Intermediate Energy Physics. In order to extend the number of applications a gain control circuit is embedded into the preamplifiers; a tuneable PZC circuit is used in the shaper. The
M.A. Baturitsky et al. / Nuclear Instruments and Methods in Physics Research A 496 (2003) 162–171
preamplifiers can operate at detector capacitance up to 300 pF (with 10% gain degradation) and maximum input charge up to 750 pC. The CRRC5 shaper provides B600 ns peaking time. The ASICs can drive a large capacitive load providing maximal amplitude of output signal not less than 74 V for the preamplifiers and 73 V for the shaper. The ASIC family described seems to cover a large part of IEP applications.
References [1] N. Randazzo, et al., Nucl. Instr. and Meth. A 420 (1999) 279.
171
[2] M.A. Baturitsky, et al., Nucl. Instr. and Meth. A 378 (1996) 570. [3] LeCroy Research Systems, 1996 Catalog. [4] M.A. Baturitsky, O.V. Dvornikov, Nucl. Instr. and Meth. A 378 (1996) 564. [5] S.M. Sze, Physics of Semiconductor Devices, 2nd Edition, Wiley-Interscience Publication, New York, 1981. [6] M.A. Baturitsky, O.V. Dvornikov, Nucl. Instr. and Meth. A 398 (1997) 308. [7] P.D. Walker, M.M. Green, IEEE J. Solid-State Circ. 31 (6) (1996) 850. [8] M.A. Baturitsky, O.V. Dvornikov, Nucl. Instr. and Meth. A 398 (1997) 308. [9] G.D. Alexeev, et al., Nucl. Instr. and Meth. A 462 (2001) 494.