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subtractor with control input using semiconductor optical amplifiers
Optik 125 (2014) 6183–6188
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Optik journal homepage: www.elsevier.de/ijleo
Frequency encoded optical four-bit adder/subtractor with control input using semiconductor optical amplifiers Kousik Mukherjee Department of Physics (UG & PG), B.B. College, Asansol, West Bengal, India
a r t i c l e
i n f o
Article history: Received 6 July 2013 Accepted 4 June 2014 Keywords: Semiconductor optical amplifier Optical computation Four wave mixing Frequency encoding
a b s t r a c t Optical adder/subtractor for two four-bit frequency encoded binary numbers are proposed and designed based on four wave mixing, add drop multiplexing and frequency conversion in semiconductor optical amplifier. The input bits and the control input are intensity-modulated signal of two specific frequencies suitable for optical communication in the C band of wavelength. The device can distinguish negative and positive results and controlled operation are most promising in this proposal. The use of semiconductor optical amplifiers along with frequency encoding makes the system very fast and useful for future optical communication and computation systems. © 2014 Elsevier GmbH. All rights reserved.
1. Introduction The demand of high speed processing of huge data is possible only in optical domain because the speed of electronic processors has almost reached the saturation. The basic element of an optical logic processor is the optical switch. An optical switch works on the principles of intensity switching [1–5], polarization switching [6–8], phase switching [9,10] or frequency switching [11–22]. Frequency is a fundamental property of light, it does not alter during propagation but can be changed by non-linear properties of different materials and devices. So the technique of frequency switching has become popular among researchers in present days [11–22]. In frequency switching technique, the states of information are represented by signal of different frequencies [23–25]. This is called frequency encoding of states. In the work by Jorgensen [23], three different frequencies of the primary light signals blue, red and green are used to represent the states of information. In the work by Hill et al. [24,25], the complementary states of information are represented by two different wavelengths. One of the most important device for implementing optical devices is semiconductor optical amplifier (SOA) which shows different types of non-linearity like cross gain modulation (XGM), cross phase modulation (XPM), four wave mixing (FWM), etc. [26,27]. SOA is also important because of its high-speed capability, low noise, less operating power and integration ability and is very popular in present day optical computation and communication research.
E-mail address: [email protected] http://dx.doi.org/10.1016/j.ijleo.2014.06.041 0030-4026/© 2014 Elsevier GmbH. All rights reserved.
Full adder and full subtractor are basic building block for optical logic processors for computation and communication systems in future. In last decade, a few proposals have been found on these devices [28–31]. Most of these are using intensity encoding and proposals based on frequency encoding are very few [15,32,21]. Frequency encoded simultaneous adder–subtractor is least in number [15], which is based on polarization rotation based switching along with add drop multiplexer (ADM) and is complex in hardware. In this communication, SOA based four wave mixing (FWM) is used for the implementation of the adder/subtractor unit. The unit can be used as adder and subtractor by using a control input, which is also frequency-encoded signal. When the control input is low, the unit works as an adder and when the control is high, the unit subtract in two’s complement format. 2. Basic building blocks and working principles of the adder/subtractor unit In digital electronics it is well known that two four bit numbers can be added using four full adders and the two’s complement of any four bit number is found by flipping each bits of the number i.e. one’s complement and then adding ‘1’ to the one’s complement of the number. So to achieve two’s complement in controlled way we have to use X-OR gates and full adders. For the implementation of the full adders AND, OR and X-OR logic gates are required. So the basic building blocks for the implementation of the proposed optical four bit two’s complement adder/subtractor unit is OR, AND, and X-OR gates only. All the logic gates used in this communication are frequency encoded all optical logic gates based on ADM, FWM in SOA and frequency conversion in reflective semiconductor optical
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K. Mukherjee / Optik 125 (2014) 6183–6188 Pump1
Pump2 TM
pump2
Signal Signal
Θ
Converted TE
Pump1
υs
υ2
υ1
υ 1 + υ 2 – υs
Frequency
Fig. 1. Polarization independent four wave mixing.
MQW
C
υ1, υ2, υ3
Reflected
Grating filter
υ1
υ2, υ3
Fig. 4. Frequency encoded NOT gate. Table 1 Truth table of the logic gates OR, AND and X-OR gate.
Dropped signal υ1 Fig. 2. Tunable SOA filter ADD/DROP multiplexer.
amplifiers (RSOA). Based on these mechanisms in SOA, all optical frequency encoded logic gates [12] and full adder [32] was already proposed. The FWM used to implement the logic gates and devices is polarization independent dual pump configuration with orthogonal polarization of the pump signals [33] is shown in Fig. 1. The two pumps interact with the input data signal in the SOA and generate a new conjugate signal at another frequency. This newly generated frequency is multiplexed and converted to get different output at two different frequencies as required by the frequency encoding and different logic gates are implemented. The frequency multiplexing is done by the add drop multiplexer (Fig. 2) as described in [34]. The frequency conversion to get the desired output of the gates is done by reflective semiconductor optical amplifier (Fig. 3) based on the principle described in [35]. 2.1. Logic gates and the full adder for the implementation of the adder/subtractor The logic gates used in this communication are described in details in the work [12]. The NOT gate is the modified NOR gate which is achieved by making two inputs of the NOR gate same. In frequency encoding the low (0) state is represented by a signal of frequency 1 and high (1) state is represented by another signal of frequency 2 . This type of encoding has several advantages compared to other conventional encoding systems [11–25,32]. The working of the gates is described below very in short. 2.1.1. NOT gate When A is a signal of frequency 1 (low) the FWM generated output is a signal of frequency 21 –s and is converted to a signal of frequency 2 by RSOA 1 in Fig. 4. Similarly when A is a signal of frequency 2 (high) the FWM generated output is a signal of
A
B
OR
AND
X-OR
1(0) 1(0) 2(1) 2(1)
1(0) 2(1) 1(0) 2(1)
1(0) 2(1) 2(1) 2(1)
1(0) 1(0) 1(0) 2(1)
1(0) 2(1) 2(1) 1(0)
frequency 22 –s and is converted to a signal of frequency 1 by RSOA 2. So the unit in Fig. 4 works like a NOT gate. 2.1.2. OR gate When any one of the inputs A and B is a signal of frequency 2 , the output is a signal of frequency 2 i.e. high. If both the inputs are signals of frequency 1 , the output is a signal of frequency 1 (low). 2.1.3. AND gate When any one of the inputs A and B is a signal of frequency 1 , the output is a signal of frequency 1 (high). If both the inputs are signals of frequency 2 , the output is a signal of frequency 2 (high). 2.1.4. X-OR gate When A and B is signals of different frequencies, the output is high. If they are of it output is low. The truth table of the logic gates is shown in Table 1. The working of the full adder is described in Table 2. The implementation of the full adder for two 2-bit numbers is described in [32]. 3. Implementation of the adder/subtractor unit and the algorithm of the operation Using the logic gates and full adder described in Section 2.1 of this communication an adder–subtractor unit can be easily designed as shown in Fig. 5. The first stage is an array of four X-OR gate are used to flip each bits of a four bit number in a controlled way depending on the control input C, the second stage is an array of four single bit full adder. The first two stages are used to generate result of operation of the addition and subtraction depending on Table 2 Operating conditions and outputs of the full adder.
Weak signal υ1
Inputs
SOA High power input υ2 Ultra low reflecting coating Converted output
υ2 Fig. 3. Reflective SOA.
Highly reflecting coating
Outputs
An
Bn
Cn−1
Sum
Carry
1 1 1 1 2 2 2 2
1 1 2 2 1 1 2 2
1 2 1 2 1 2 1 2
1 2 2 1 2 1 1 2
1 1 1 2 1 2 2 2
K. Mukherjee / Optik 125 (2014) 6183–6188
Fig. 5. Frequency encoded all optical four-bit adder/subtractor unit.
the control input C = 0, and C = 1, respectively. The result of addition comes out to be in binary simple form. But the result of subtraction comes out to be in two’s complement form. This result is either positive or negative. When the result of subtraction is positive the carry bit is discarded in the final output. But when the result is negative we need to make two’s complement of the result to get it in simple binary form. To control this we need another control input and this second control bit is the AND – ed version of the control C and inverted version of the carry CF of the full adder FA3 and is used as one of the input in the X-OR gates of the second X-OR gate array. In the full adders FA4 to FA7, one input is always made low (L). This also means that they are working as half adders. But we here proposed to use two four-bit full adder chips, one consisting of FA0 to FA3 and another FA4 to FA7. The controlled operation of the proposed unit is described in Table 3. In Fig. 5, A = A3 A2 A1 A0 is a four bit number and B3 B2 B1 B0 is another four bit number to be added or subtracted depending on the control input C = 0, or 1 respectively. In doing this, it is kept in mind that subtraction is nothing but addition of the negative of the subtrahend. So two’s complement of the subtrahend is generated when C = 1 for subtraction operation. Normal operation of addition is performed when C = 0, and no two’s complement is generated. All operations are performed using frequency encoding of binary bits. 3.1. Operation of the device using frequency encoding of the states of information Let us explain the operation of the device considering frequency encoding of the states of information. As mentioned earlier, in Table 3 Operating condition of the adder/subtractor unit. C
CF
Operation of the unit
1 (0) 1 (0) 2 (1)
1 (0) 2 (1) 1 (0)
2 (1)
2 (1)
Addition with no carry [CFinal = 1 (0)] Addition with carry one[CFinal = 2 (1)] Subtraction with no carry [CFinal = 1 (0)], the result is negative and two’s complementation is required Subtraction with carry one but carry discarded [CFinal = 1 (0)], the result is positive
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frequency encoding technique the state ‘0’ is represented by a signal of frequency 1 and the state ‘1’ is represented by another signal of frequency 2 preferably in the C band of communication. So all the inputs, i.e. two four bit numbers A and B, control input C are represented by frequencies of particular values. When the control signal is a signal of frequency 1 (C = 0), each bit of the number B = B3 B2 B1 B0 after the X – OR gates (Array 1) remains unaltered or no complements happen. Each bit of this number is added to the corresponding bits of the number A = A3 A2 A1 A0 . Addition of A0 and B0 taking C as previous stage carry generates sum bit S0 and a carry for the next adder FA1. In this adder A1 and B1 are added and carry for the FA2 is generated. This adder results sum bit S1 . In this way the sum bits S2 and S3 are also generated from FA2 and FA3 respectively. The final carry of the adder is generated from FA3 and it is extracted as carry of the first stage of adder as CF . The Sum generated by the adders FA0 to FA3 is again passed through the X-OR array 2, and remains unaltered since the other input to the ˜ F = 0 (in frequency encoded format this is a signal X-OR gate is CC ˜ F = 0, the full adders FA4 to FA7 of frequency 1 ). Again since CC do not make any change to the corresponding sum bits S0 , S1 , S2 and S3 . So during addition by the system the outputs of FA0 to FA3 proceed unaltered and give the final sum of the addition. The carry ˜ F. So the result of operof the operation is generated by CFinal = CC ation of addition of A and B is given by the bit stream, CFinal S3F S2F S1F S0F . For subtraction we need to generate two’s complement of the number B3 B2 B1 B0 . For this each bit of this number is first flipped by the X-OR gates array 1, and this become possible when the control input C = 1 (in frequency encoded format this is a signal of frequency 2 ). This control input is now added to the flipped ˜3 B ˜2 B ˜1 B ˜ 0 by the full adders FA0 to FA3. The output of number B these adders are difference D3 D 2 D1 D0 . The result may be positive or negative. This can be distinguished by observing CF . If CF is high (signal of frequency 2 ), the result is positive and the final output S3F S2F S1F S0F is unaltered version of D3 D 2 D1 D0 . When CF is low (signal of frequency 1 ), the result D3 D 2 D1 D0 is negative. So the final result is two’s complement of the bit stream D3 D 2 D1 D0 . To confirm this controlled operation of subtraction, the AND ˜ F and C(CC ˜ F as shown in Fig. 5) is used as second ed version of C input bit along with the bits D3 D 2 D1 D0 in the respective X-OR gates of the array 2 and as the carry input to the adder FA4. The final result is given byCFinal D3F D 2F D1F D0F . Let us perform the operation of addition of the number A and B in frequency-encoded format using the adder/subtractor unit of Fig. 5 for different cases as described in Table 3 with specific examples. For addition of two numbers, result of which is less than 15 (maximum number in decimal represented by four bit binary) we have to make control input C low i.e. a signal of frequency 1 is applied to the control port. This signal of frequency 1 serves as the input to each of the X-OR gates of X-OR arrays 1 and also as carry input to the full adders FA0. For a specific example, let us consider A = 7 (decimal) and B = 5 (decimal). The result is 12 in decimal, which is a four-bit number, i.e. the carry bit is zero or a signal of frequency 1 in frequency encoded binary. The binary equivalent of 7 is A = A3 A2 A1 A0 = 1 2 2 2 and that of 5 is B = B3 B2 B1 B0 = 1 2 1 2 in frequency encoded format. Since control input C is low (signal of frequency 1 ) the X-OR gates behave like simple transmission gates. So all the bits of the number B (Addend) remains unaltered. In this situation the inputs and outputs of the full adders FA0 to FA3 are listed below based on Table 2.
FA0: Input bits A0 = 2 , B0 = 2 and input carry C = 1 . The corresponding outputs are sum S0 = 1 and carry which propagate to the full adder FA1 is 2 .
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FA1: Input bits A1 = 2 , B1 = 1 and input carry = 2 from FA1. The corresponding outputs are sum S1 = 1 and carry which propagate to the full adder FA2 is 2 . FA2: Input bits A2 = 2 , B2 = 2 and input carry = 2 from FA1. The corresponding outputs are sum S2 = 2 and carry which propagate to the full adder FA2 is 2 . FA3: input bits A3 = 1 , B3 = 1 and input carry = 2 from FA2. The corresponding outputs are sum S3 = 2 and carry which propagate to the final carry output CF is 1 . These SUM outputs propagate the next X-OR gate array 2, where ˜ F = 0 (signal of frequency 1 in frethe other input of each gate is CC quency encoded format) in this condition. So the X-OR gates in the array 2 transmit the SUM inputs S0 , S1 , S2 , and S3 without inversion. So the unmodified versions of these SUM inputs S0 , S1 , S2 , and S3 are the inputs to the corresponding full Adders FA4, FA5, FA6, and FA7 respectively. The other input (L) of each full adder of this group is a signal of frequency 1 , i.e. low in this case. Thus X-OR gate array only transmit the bits without inversion. In this situation, the inputs and outputs of the full adders FA4 to FA7 are listed below based on Table 2: ˜ F = 1 . The corresponding FA4: Input bits S0 = 1 , L = 1 and carry CC outputs are final sum S0F = 1 and carry, which propagate to the full adder FA5 is 1 . FA5: Input bits S1 = 1 , L = 1 and input carry from output of FA4 = 1 . The corresponding outputs are final sum S1F = 1 and carry, which propagate to the full adder FA6 is 1 . FA6: Input bits S2 = 2 , L = 1 and input carry = 1 . The corresponding outputs are final sum S2F = 2 and carry, which propagate to the full adder FA7 is 1 . FA3: input bits S3 = 2 , L = 1 and input carry = 1 from the output of FA6. The corresponding outputs are final sum S3F = 2 and carry output, CF = 1 . ˜ F = 1 , i.e. low. So the In this situation the final carry CFinal is CC result of addition of the numbers A (7 in decimal) and B (5 in decimal) is CFinal S3F S2F S1F S0F = 1 2 2 1 1 , which is five bit result of the addition and represents 12 in frequency encoded binary format. So the above circuit just add two four-bit number in frequency encoded format when the control input is low (C = 0 or signal of frequency 1 ) and corresponds to the first row of Table 3. Keeping the control input C low, the addition of two four- bit numbers giving result more than fifteen can be done if the carry CF of the FA3 is high, ˜ F is i.e. a signal of frequency 2 in frequency encoded format. So CC low, i.e. a signal of frequency 1 . So again no change in the bits S0 , S1 , S2 , and S3 happens and they are transmitted through X-OR gate ˜ F is a signal of array 2 without alternation. The final carry CFinal = CC ˜ are high in this case. Let us frequency 2 , i.e. high as both CF and C consider specifically the addition of 7 and 9 in frequency encoded format using the unit of Fig. 5. In frequency encoded format, A = A3 A2 A1 A0 = 1 2 2 2 (7 in decimal), and B = B3 B2 B1 B0 = 2 1 1 2 (9 in decimal). The result of operation is 16 and is given by CFinal S3F S2F S1F S0F = 2 1 1 1 1 in frequency encoded format. We shall now consider bit-wise operation: FA0: Input bits A0 = 2 , B0 = 2 and input carry C = 1 . The corresponding outputs are sum S0 = 1 and carry which propagate to the full adder FA1 is 2 . FA1: Input bits A1 = 2 , B1 = 1 and input carry = 2 from FA1. The corresponding outputs are sum S1 = 1 and carry which propagate to the full adder FA2 is 2 . FA2: Input bits A2 = 2 , B2 = 1 and input carry = 2 from FA1. The corresponding outputs are sum S2 = 1 and carry which propagate to the full adder FA2 is 2 .
FA3: input bits A3 = 1 , B3 = 2 and input carry = 2 from FA2. The corresponding outputs are sum S3 = 1 and carry which propagate to the final carry output CF is 2 .
These SUM outputs propagate the next X-OR gate array 2, where ˜ F = 0 (signal of frequency 1 in frethe other input of each gate is CC quency encoded format) in this condition. So the X-OR gates in the array 2 transmit the SUM inputs S0 , S1 , S2 , and S3 without inversion. So the unmodified versions of these SUM inputs S0 , S1 , S2 , and S3 are the inputs to the corresponding Full Adders FA4, FA5, FA6, and FA7 respectively. The other input (L) of each full adder of this group is a signal of frequency 1 , i.e. low (it is always low as mentioned earlier). Thus X-OR gate array only transmit the bits without ˜ F is a signal of frequency 2 i.e. inversion. The final carry CFinal = CC ˜ are high in this case. Thus the result of operhigh as both CF and C ation is obtained as CFinal S3F S2F S1F S0F = 2 1 1 1 1 , i.e. 16 in frequency encoded format as expected. So it is established that the device in Fig. 5 can perform addition of two binary four bit numbers in frequency encoded format and generate a five bit result in frequency encoded format in controlled way. Now we consider specific examples of subtraction for two cases. At first we subtract 5 from 7, and the result is 2. In frequency encoded format the representation of these numbers are A = A3 A2 A1 A0 = 1 2 2 2 , (7), B = B3 B2 B1 B0 = 1 2 1 2 (5) and result = CFinal D3F D2F D1F D0F = 1 1 1 2 1 (2). For this the control input C is a signal of frequency 2 ,i.e. high. This high control input C confirms the flipping of each bit of B in the X-OR gate array-1 and also addition of a high bit to the flipped version of B by the full adders FA0 to FA3 generating two’s complement. Let us see whether the device in Fig. 5 can perform this operation or not. The operation is described bit-wise as below:
FA0: Input bits A0 = 2 and input carry C = 2 . The output of the cor˜ 0 = 1 which is the input of the full adder responding X-OR gate is B FA0 along with A0 = 2 . The corresponding outputs are D0 = 1 and carry, which propagate to the full adder FA1 is 2 . FA1: Input bits A1 = 2 and input carry = 2 from FA0. The output of ˜ 1 = 2 which is the input of the the corresponding X-OR gate is B full adder FA1 along with A1 = 2 . The corresponding outputs are D1 = 2 and carry, which propagate to the full adder FA2 is 2 . FA2: Input bits A2 = 2 and input carry = 2 from FA1. The output of ˜ 2 = 1 which is the input of the the corresponding X-OR gate is B full adder FA2 along with A2 = 2 . The corresponding outputs are D2 = 1 and carry, which propagate to the full adder FA3 is 2 . FA3: input bits A3 = 1 and input carry = 2 from FA2. The output of ˜ 3 = 2 which is the input of the the corresponding X-OR gate is B full adder FA3 along with A3 = 1 . The corresponding outputs are D3 = 1 and carry, which propagate to the final carry output CF is 2 .
The carry CF = 2 (1) indicates that the result is positive. So no two’s complementation is required. So the output from the full adders stage FA0 to FA4 can be written as CF D3 D2 D1 D0 = 2 1 1 2 1 . Discarding the carry, the result is positive and final result is a four bit number 1 1 2 1 (2) or in five bit representation, CFinal D3F D2F D1F D0F = 1 1 1 2 1 . So no two’s complementation is required for this case and CF = 2 should be converted to CFinal = 1 keeping ˜ F = 1 . other bits unaltered. This is achieved by making CFinal = CC ˜ F = 1 is inserted as carry bit to the full adder FA4. Another input CC One input of the full adders FA4, FA5, FA6, and FA7 is low (L = 1 ) ˜ 0, D ˜ 1, D ˜ 2 , and D ˜ 3 respectively. In this and the other inputs are D situation, the input conditions of the full adders FA4 to FA7 is as follows:
K. Mukherjee / Optik 125 (2014) 6183–6188
˜ 0 = 1 , L = 1 and carry input CC ˜ F = 1 . The corFA4: Input bits D responding outputs are final difference D0F = 1 and carry which propagate to the full adder FA5 is 1 . ˜ 1 = 1 , L = 1 and input carry from output of FA5: Input bits D FA4 = 1 . The corresponding outputs are final difference D1F = 1 and carry which propagate to the full adder FA6 is 1 . ˜ 2 = 2 , L = 1 and input carry = 1 . The correspondFA6: Input bits D ing outputs are final difference D2F = 2 and carry which propagate to the full adder FA7 is 1 . ˜ 3 = 1 , L = 1 and input carry = 1 from the output FA7: input bits D ˜ 3F = 1 and of FA6. The corresponding outputs are final difference D carry output 1 which is not utilized. So the output of the unit is given by CFinal D3F D2F D1F D0F = 1 1 1 2 1 , which is frequency encoded five bit representation of the number 2. Let us perform the operation of subtraction of a larger number from a smaller one. For example, 8 from 5 in frequency encoded format. In frequency encoded format the representation of the numbers A = 5 and B = 8 are A = A3 A2 A1 A0 = 1 2 1 2 , (5), B = B3 B2 B1 B0 = 2 1 1 1 (8) and result = CFinal D3F D2F D1F D0F = 1 1 1 2 2 (3). For this the control input C is a signal of frequency 2 ,i.e. high. This high control input C confirms the flipping of each bit of B in the X-OR gate array-1 and also addition of a high bit to each bit of the flipped version of B in the full adders FA0 to FA3 generating two’s complement. The bit stream corresponding to B = B3 B2 ˜2 B ˜1 B ˜ 0 = 1 2 2 2 . ˜ =B ˜3 B B1 B0 = 2 1 1 1 becomes B Let us see whether the device in Fig. 5 can perform the operation of subtraction or not. The operation is described bit-wise as below: FA0: Input bits A0 = 2 and input carry C = 2 . The output of the cor˜ 0 = 2 which is the input of the full adder responding X-OR gate is B FA0 along with A0 = 2 . The corresponding outputs are D0 = 2 and carry, which propagate to the full adder FA1 is 2 . FA1: Input bits A1 = 1 and input carry = 2 from FA0. The output of ˜ 1 = 2 which is the input of the the corresponding X-OR gate is B full adder FA1 along with A1 = 1 . The corresponding outputs are D1 = 1 and carry, which propagate to the full adder FA2 is 2 . FA2: Input bits A2 = 2 and input carry = 2 from FA1. The output of ˜ 2 = 2 which is the input of the the corresponding X-OR gate is B full adder FA2 along with A2 = 2 . The corresponding outputs are D2 = 2 and carry, which propagate to the full adder FA3 is 2 . FA3: input bits A3 = 1 and input carry = 2 from FA2. The output of ˜ 3 = 1 which is the input of the the corresponding X-OR gate is B full adder FA3 along with A3 = 1 . The corresponding outputs are D3 = 2 and carry, which propagate to the final carry output CF is 1 . So the output from the full adders stage FA0 to FA4 can be written as CF D3 D2 D1 D0 = 1 2 2 1 2 . CF = 1 indicates that the result is negative and final result is obtained by discarding carry (i.e. by making CFinal = 1 ) and making two’s complement of the four bit number given by the bit stream D3 D2 D1 D0 = 2 2 1 2 . The two’s complement is automatically generated by the X-OR gate array 2 and full adders FA4 to FA7 as described below. ˜ F = 2 One input of each X-OR gate of the X-OR gate array-2 is CC (as C = 2 and CF = 1 ) ensures NOT operation of the X-OR gates and flipping of the other input bits of the X-OR gates. So after the XOR gate array-2, the bit stream D3 D2 D1 D0 = 2 2 1 2 becomes ˜0D ˜1D ˜2D ˜ 3 = 1 1 2 1 . In this case CF should be converted to D ˜ F = 1 . One input CFinal = 1 . This is achieved by making CFinal = CC is L = 1 to the full adders FA4, FA5, FA6, and FA7 and the other ˜ 0, D ˜ 1, D ˜ 2 , and D ˜ 3 respectively. The carry input to the full input is D ˜ F = 2 , i.e. high. This ensures two’s adder FA4 in this condition is CC
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complementation. In this situation, the input conditions of the full adders FA4 to FA7 is as follows: ˜ 0 = 1 , L = 1 and CC ˜ F = 2 . The corresponding FA4: Input bits D outputs are final difference D0F = 2 and carry, which propagate to the full adder FA5 is 1 . ˜ 1 = 2 , L = 1 and input carry from output of FA5: Input bits D FA4 = 1 . The corresponding outputs are final difference D1F = 2 and carry, which propagate to the full adder FA6 is 1 . ˜ 2 = 1 , L = 1 and input carry = 1 . The correspondFA6: Input bits D ing outputs are final difference D2F = 1 and carry, which propagate to the full adder FA7 is 1 . ˜ 3 = 1 , L = 1 and input carry = 1 from the output FA7: input bits D ˜ 3F = 1 and of FA6. The corresponding outputs are final difference D carry output 1 which is not utilized. So the output of the unit is given by CFinal D3F D2F D1F D0F = 1 1 1 2 2 , which is frequency encoded five bit representation of the number 3. So the result of subtraction of 8 from 5 can well performed by this device as shown in Fig. 5. 4. Conclusions Frequency encoded all optical adder/subtractor unit is proposed and the algorithm is explained with suitable numerical examples. The unit can perform addition with and without carry giving five-bit result. It can subtract a smaller four-bit number from a bigger one and a bigger four-bit number from a smaller one. The proposal is based on semiconductor optical amplifier based non-linearity; four wave mixing and cross gain modulation. The device is proposed first time in frequency encoded format as far as the authors knowledge goes, and can be the building block of future all optical communication systems. The novelty of the proposal lies in the fact that SOA based polarization independent FWM with frequency encoding is used and controlled generation of result. The device can distinguish negative and positive results also. For proper operation of the proposed device the driving currents should be 200 mA for SOAs used to generate FWM. The input power of the pumps is 4–10 dBm and that of probe beam is −4 to −10 dBm. Up and down conversions done by RSOAs because of their higher conversion efficiency [35]. References [1] T. Durhuus, B. Fernier, P. Garabedian, F. Leblond, J.L. Lafragette, B. Mikkelsen, C.G. Joergensen, K.E. Stubkjaer, High speed alloptical gating using two-section semiconductor optical amplifier structure, in: Proc. CLEO’92, Anaheim, CA, 1992, pp. 552–554. [2] B. Glance, J.M. Wiesenfeld, U. Koren, A.H. Gnauck, H.M. Presby, A. Jourdan, High performance optical wavelength shifter, Electron. Lett. 28 (August (18)) (1992) 1714–1715. [3] A. Jourdan, L. Berthelon, P. Bonno, F. Bruyére, M. Chbat, C. Coeurjolly, J.Y. Emery, P. Gavignet, E. Grard, C. Janz, A. Noury, G. Soulage, T. Zami, Fully reconfigurable WDM optical crossconnect: feasibility validation and preparation of prototype crossconnect for ACTS ‘OPEN’ field trials, in: Proc. ECOC’97, vol. 3, Edinburgh, UK, September 1997, pp. 55–58. [4] R.E. Wagner, R.C. Alferness, A.A.M. Saleh, M.S. Goodman, MONET: multiwavelength optical networking (invited paper), J. Lightwave Technol. 14 (June) (1996) 1349–1355. [5] M. Berger, M. Chbat, P. Demeester, P. Godsvang, B. Hein, M. Huber, A. Jourdan, A. Leclert, R. Marz, T. Olsen, M. Sotom, G. Tobolka, B. Van Caenegem, T. Broeck, PanEuropean optical networking using wavelength division multiplexing, IEEE Commun. Mag. 35 (April) (1997) 82–89. [6] C. Taraphdar, T. Chattopadhyay, J.N. Roy, Designing of an all optical scheme for single input ternary logical operations, Optik 122 (1) (2011) 33–36. [7] T. Chattopadhyay, J.N. Roy, Polarization encoded TOAD based all optical quaternary literals, Optik 121 (7) (2008) 617–622. [8] J.N. Roy, T. Chattopadhyay, S. Manna, G.K. Maity, Polarization encoded TOAD based quaternary max gate, in: PHOTONICS, IIT Delhi, India, 2008, pp. 1–4. [9] B. Chakarborty, S. Mukhophahyay, All-optical method of implementing half and full subtractor by the use of phase encoding principle, Optik 122 (24) (2011) 2207–2210.
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[10] S.K. Chandra, S. Mukhopadhyay, An all-optical approach of implementing a different kind of phase encoded XOR and XNOR logic operations with the help of four wave mixing in SOA, Optik 124 (6) (2013) 505–507. [11] K. Mukherjee, P. Ghosh, A novel frequency encoded all optical CNOT gate exploiting difference frequency generation and implementation of fast binary adders using frequency encoding and non-linear dielectric films, Optik 121 (24) (2010) 2195–2197. [12] K. Mukherjee, A novel frequency encoded all optical logic gates exploiting polarization insensitive four wave mixing in semiconductor optical amplifier, filtering property of add/drop multiplexer and non linearity of reflective semiconductor amplifier, Optik 122 (10) (2011) 891–895. [13] K. Mukherjee, P. Ghosh, D. Kumbhakar, A.K. Meikep, A method of optical implementation of frequency encoded all optical logic gates based on multiphoton processes in non linear material, Opt. Quantum Electron. 42 (2) (2010) 121–128. [14] K. Mukherjee, A.K. Meikap, D. Kumbhakar, Frequency encoded all optical single bit memory unit using difference frequency generation alone, Opt. Quantum Electron. 43 (2012) 101–107. [15] P. Ghosh, D. Kumbhakar, A.K. Mukherjee, K. Mukherjee, An all optical method of implementing a wavelength encoded simultaneous binary full adder full subtractor unit exploiting non linear polarization rotation in semiconductor optical amplifier, Optik 122 (19) (2011) 1757–1763. [16] K. Mukherjee, On the method of implementation of frequency encoded all optical reconfigurable logic gates based on total reflectional switch at the interface, Opt. Photonics Lett. 4 (2011) 25–34. [17] K. Mukherjee, Alternative approach to optical frequency encoded flip flops by utilizing semiconductor optical amplifier non linearity, J. Opt. 41 (1) (2012) 16–24. [18] S.K. Garain, S. Mukhopadhyay, Method of implementing frequency encoded multiplexer and demultiplexer systems using non linear semiconductor optical amplifiers, Opt. Laser Technol. 41 (8) (2009) 972–976. [19] P. Ghosh, S.K. Garain, A novel all optical method of implementing an n-bit wavelength encoded complete digital data comparator using nonlinear semiconductor optical amplifiers, Optik 122 (17) (2011) 1544–1551, http://dx.doi.org/10.1016/j.ijleo.2010.05.037. [20] S. Dutta, S. Mukhopadhyay, An all optical approach of frequency encoded NOT based latch using semiconductor optical amplifier, J. Opt. 39 (2010) 39–45. [21] S.K. Garai, A novel all-optical frequency-encoded method to develop arithmetic and logic unit (ALU) using semiconductor optical amplifiers, J. Lightwave Technol. 29 (23) (2011) 3506–3514.
[22] A. Pal, S. Mukhopadhyay, An alternative approach of developing a frequency encoded tri-state multiplexer with broad area semiconductor optical amplifier (BSOA), Opt. Laser Technol. 44 (1) (2012) 281–284. [23] P.O. Jorgensen, Frequency encoded logic devices, US Patent, No 4706299, Nov 10, 1987. www.freepatentsonline.com [24] M.T. Hill, H. de Waardt, G.D. Khoe, H.J.S. Dorrren, All-optical flip-flop based on coupled laser diodes, IEEE J. Quantum Electron. 37 (3) (2001) 405–413. [25] M.T. Hill, H. de Waardt, G.D. Khoe, H.J.S. Dorren, Fast optical flip-flop by use of Mach–Zehnder interferometers, Microw. Opt. Technol. Lett. 31 (2001) 411–415. [26] A.J. Poustie, K.J. Blow, A.E. Kelly, R.J. Manning, All optical full adder with bit differential delay, Opt. Commun. 168 (1999) 89–93. [27] S. Kim, S. Lee, S.H. Kim, S. Lee, J. Park, All optical binary full adder using SLALOMs, in: OECC/IOOC 2001 Conf. Incorporating ACOFT, PPS-3, 2001, pp. 444–445. [28] J.H. Kim, B.C. Kim, Y.T. Byun, Y.M. John, S. Lee, D.H. Woo, S.H. Kim, All-optical full adder using semiconductor optical amplifiers, in: Proc. ECOC, 2003, pp. 345–349, Paper We 4.P75. [29] M. Scaffardi, P. Ghelfi, et al., Photonic processing for digital comparison and full addition based on semiconductor optical amplifiers, IEEE J. Select. Top. Quantum Electron. 14 (May/June (3)) (2008) 826–833. [30] K. Roy Chowdhury, S. Mukhopadhyay, An all-optical scheme of signed digit binary addition based on optical nonlinear material, Optoelectron. Lett. 6 (November (1)) (2008) 447–451. [31] S. Kaur, R.S. Kaler, All optical integrated full adder–subtractor and demultiplexer using SOA-based Mach–Zehnder interferometer, Int. J. Eng. Sci. Technol. 4 (1) (2012) 303–310. [32] K. Mukherjee, Methods of implementation of frequency encoded all optical Half adder, Half subtractor and full adder based on semiconductor optical amplifiers and add drop multiplexers, Optik 122 (13) (2011) 1188–1194, http://dx.doi.org/10.1016/j.ijleo.2010.07.026. [33] J.P.R. Lacey, M.A. Summerfield, S.J. Madden, Tunability of polarizationinsensitive wavelength converters based on four wave mixing in semiconductor optical amplifiers, J. Lightwave Technol. 16 (1998) 2419–2427. [34] G. Raybon, U. Koren, B.I. Miller et-al, A wavelength-tunable semiconductor amplifier/filter for add/drop multiplexing in WDM networks, IEEE Photon. Technol. Lett. 9 (1997) 40–42. [35] L.Q. Guo, M.J. Connelly, A novel approach to all optical wavelength conversion by utilizing a reflective semiconductor optical amplifier in a co-propagation scheme, Opt. Commun. 281 (2008) 4470–4473.
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Frequency encoded optical four-bit adder/subtractor with control input using semiconductor optical amplifiers Kousik Mukherjee Department of Physics (UG & PG), B.B. College, Asansol, West Bengal, India
a r t i c l e
i n f o
Article history: Received 6 July 2013 Accepted 4 June 2014 Keywords: Semiconductor optical amplifier Optical computation Four wave mixing Frequency encoding
a b s t r a c t Optical adder/subtractor for two four-bit frequency encoded binary numbers are proposed and designed based on four wave mixing, add drop multiplexing and frequency conversion in semiconductor optical amplifier. The input bits and the control input are intensity-modulated signal of two specific frequencies suitable for optical communication in the C band of wavelength. The device can distinguish negative and positive results and controlled operation are most promising in this proposal. The use of semiconductor optical amplifiers along with frequency encoding makes the system very fast and useful for future optical communication and computation systems. © 2014 Elsevier GmbH. All rights reserved.
1. Introduction The demand of high speed processing of huge data is possible only in optical domain because the speed of electronic processors has almost reached the saturation. The basic element of an optical logic processor is the optical switch. An optical switch works on the principles of intensity switching [1–5], polarization switching [6–8], phase switching [9,10] or frequency switching [11–22]. Frequency is a fundamental property of light, it does not alter during propagation but can be changed by non-linear properties of different materials and devices. So the technique of frequency switching has become popular among researchers in present days [11–22]. In frequency switching technique, the states of information are represented by signal of different frequencies [23–25]. This is called frequency encoding of states. In the work by Jorgensen [23], three different frequencies of the primary light signals blue, red and green are used to represent the states of information. In the work by Hill et al. [24,25], the complementary states of information are represented by two different wavelengths. One of the most important device for implementing optical devices is semiconductor optical amplifier (SOA) which shows different types of non-linearity like cross gain modulation (XGM), cross phase modulation (XPM), four wave mixing (FWM), etc. [26,27]. SOA is also important because of its high-speed capability, low noise, less operating power and integration ability and is very popular in present day optical computation and communication research.
E-mail address: [email protected] http://dx.doi.org/10.1016/j.ijleo.2014.06.041 0030-4026/© 2014 Elsevier GmbH. All rights reserved.
Full adder and full subtractor are basic building block for optical logic processors for computation and communication systems in future. In last decade, a few proposals have been found on these devices [28–31]. Most of these are using intensity encoding and proposals based on frequency encoding are very few [15,32,21]. Frequency encoded simultaneous adder–subtractor is least in number [15], which is based on polarization rotation based switching along with add drop multiplexer (ADM) and is complex in hardware. In this communication, SOA based four wave mixing (FWM) is used for the implementation of the adder/subtractor unit. The unit can be used as adder and subtractor by using a control input, which is also frequency-encoded signal. When the control input is low, the unit works as an adder and when the control is high, the unit subtract in two’s complement format. 2. Basic building blocks and working principles of the adder/subtractor unit In digital electronics it is well known that two four bit numbers can be added using four full adders and the two’s complement of any four bit number is found by flipping each bits of the number i.e. one’s complement and then adding ‘1’ to the one’s complement of the number. So to achieve two’s complement in controlled way we have to use X-OR gates and full adders. For the implementation of the full adders AND, OR and X-OR logic gates are required. So the basic building blocks for the implementation of the proposed optical four bit two’s complement adder/subtractor unit is OR, AND, and X-OR gates only. All the logic gates used in this communication are frequency encoded all optical logic gates based on ADM, FWM in SOA and frequency conversion in reflective semiconductor optical
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Pump2 TM
pump2
Signal Signal
Θ
Converted TE
Pump1
υs
υ2
υ1
υ 1 + υ 2 – υs
Frequency
Fig. 1. Polarization independent four wave mixing.
MQW
C
υ1, υ2, υ3
Reflected
Grating filter
υ1
υ2, υ3
Fig. 4. Frequency encoded NOT gate. Table 1 Truth table of the logic gates OR, AND and X-OR gate.
Dropped signal υ1 Fig. 2. Tunable SOA filter ADD/DROP multiplexer.
amplifiers (RSOA). Based on these mechanisms in SOA, all optical frequency encoded logic gates [12] and full adder [32] was already proposed. The FWM used to implement the logic gates and devices is polarization independent dual pump configuration with orthogonal polarization of the pump signals [33] is shown in Fig. 1. The two pumps interact with the input data signal in the SOA and generate a new conjugate signal at another frequency. This newly generated frequency is multiplexed and converted to get different output at two different frequencies as required by the frequency encoding and different logic gates are implemented. The frequency multiplexing is done by the add drop multiplexer (Fig. 2) as described in [34]. The frequency conversion to get the desired output of the gates is done by reflective semiconductor optical amplifier (Fig. 3) based on the principle described in [35]. 2.1. Logic gates and the full adder for the implementation of the adder/subtractor The logic gates used in this communication are described in details in the work [12]. The NOT gate is the modified NOR gate which is achieved by making two inputs of the NOR gate same. In frequency encoding the low (0) state is represented by a signal of frequency 1 and high (1) state is represented by another signal of frequency 2 . This type of encoding has several advantages compared to other conventional encoding systems [11–25,32]. The working of the gates is described below very in short. 2.1.1. NOT gate When A is a signal of frequency 1 (low) the FWM generated output is a signal of frequency 21 –s and is converted to a signal of frequency 2 by RSOA 1 in Fig. 4. Similarly when A is a signal of frequency 2 (high) the FWM generated output is a signal of
A
B
OR
AND
X-OR
1(0) 1(0) 2(1) 2(1)
1(0) 2(1) 1(0) 2(1)
1(0) 2(1) 2(1) 2(1)
1(0) 1(0) 1(0) 2(1)
1(0) 2(1) 2(1) 1(0)
frequency 22 –s and is converted to a signal of frequency 1 by RSOA 2. So the unit in Fig. 4 works like a NOT gate. 2.1.2. OR gate When any one of the inputs A and B is a signal of frequency 2 , the output is a signal of frequency 2 i.e. high. If both the inputs are signals of frequency 1 , the output is a signal of frequency 1 (low). 2.1.3. AND gate When any one of the inputs A and B is a signal of frequency 1 , the output is a signal of frequency 1 (high). If both the inputs are signals of frequency 2 , the output is a signal of frequency 2 (high). 2.1.4. X-OR gate When A and B is signals of different frequencies, the output is high. If they are of it output is low. The truth table of the logic gates is shown in Table 1. The working of the full adder is described in Table 2. The implementation of the full adder for two 2-bit numbers is described in [32]. 3. Implementation of the adder/subtractor unit and the algorithm of the operation Using the logic gates and full adder described in Section 2.1 of this communication an adder–subtractor unit can be easily designed as shown in Fig. 5. The first stage is an array of four X-OR gate are used to flip each bits of a four bit number in a controlled way depending on the control input C, the second stage is an array of four single bit full adder. The first two stages are used to generate result of operation of the addition and subtraction depending on Table 2 Operating conditions and outputs of the full adder.
Weak signal υ1
Inputs
SOA High power input υ2 Ultra low reflecting coating Converted output
υ2 Fig. 3. Reflective SOA.
Highly reflecting coating
Outputs
An
Bn
Cn−1
Sum
Carry
1 1 1 1 2 2 2 2
1 1 2 2 1 1 2 2
1 2 1 2 1 2 1 2
1 2 2 1 2 1 1 2
1 1 1 2 1 2 2 2
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Fig. 5. Frequency encoded all optical four-bit adder/subtractor unit.
the control input C = 0, and C = 1, respectively. The result of addition comes out to be in binary simple form. But the result of subtraction comes out to be in two’s complement form. This result is either positive or negative. When the result of subtraction is positive the carry bit is discarded in the final output. But when the result is negative we need to make two’s complement of the result to get it in simple binary form. To control this we need another control input and this second control bit is the AND – ed version of the control C and inverted version of the carry CF of the full adder FA3 and is used as one of the input in the X-OR gates of the second X-OR gate array. In the full adders FA4 to FA7, one input is always made low (L). This also means that they are working as half adders. But we here proposed to use two four-bit full adder chips, one consisting of FA0 to FA3 and another FA4 to FA7. The controlled operation of the proposed unit is described in Table 3. In Fig. 5, A = A3 A2 A1 A0 is a four bit number and B3 B2 B1 B0 is another four bit number to be added or subtracted depending on the control input C = 0, or 1 respectively. In doing this, it is kept in mind that subtraction is nothing but addition of the negative of the subtrahend. So two’s complement of the subtrahend is generated when C = 1 for subtraction operation. Normal operation of addition is performed when C = 0, and no two’s complement is generated. All operations are performed using frequency encoding of binary bits. 3.1. Operation of the device using frequency encoding of the states of information Let us explain the operation of the device considering frequency encoding of the states of information. As mentioned earlier, in Table 3 Operating condition of the adder/subtractor unit. C
CF
Operation of the unit
1 (0) 1 (0) 2 (1)
1 (0) 2 (1) 1 (0)
2 (1)
2 (1)
Addition with no carry [CFinal = 1 (0)] Addition with carry one[CFinal = 2 (1)] Subtraction with no carry [CFinal = 1 (0)], the result is negative and two’s complementation is required Subtraction with carry one but carry discarded [CFinal = 1 (0)], the result is positive
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frequency encoding technique the state ‘0’ is represented by a signal of frequency 1 and the state ‘1’ is represented by another signal of frequency 2 preferably in the C band of communication. So all the inputs, i.e. two four bit numbers A and B, control input C are represented by frequencies of particular values. When the control signal is a signal of frequency 1 (C = 0), each bit of the number B = B3 B2 B1 B0 after the X – OR gates (Array 1) remains unaltered or no complements happen. Each bit of this number is added to the corresponding bits of the number A = A3 A2 A1 A0 . Addition of A0 and B0 taking C as previous stage carry generates sum bit S0 and a carry for the next adder FA1. In this adder A1 and B1 are added and carry for the FA2 is generated. This adder results sum bit S1 . In this way the sum bits S2 and S3 are also generated from FA2 and FA3 respectively. The final carry of the adder is generated from FA3 and it is extracted as carry of the first stage of adder as CF . The Sum generated by the adders FA0 to FA3 is again passed through the X-OR array 2, and remains unaltered since the other input to the ˜ F = 0 (in frequency encoded format this is a signal X-OR gate is CC ˜ F = 0, the full adders FA4 to FA7 of frequency 1 ). Again since CC do not make any change to the corresponding sum bits S0 , S1 , S2 and S3 . So during addition by the system the outputs of FA0 to FA3 proceed unaltered and give the final sum of the addition. The carry ˜ F. So the result of operof the operation is generated by CFinal = CC ation of addition of A and B is given by the bit stream, CFinal S3F S2F S1F S0F . For subtraction we need to generate two’s complement of the number B3 B2 B1 B0 . For this each bit of this number is first flipped by the X-OR gates array 1, and this become possible when the control input C = 1 (in frequency encoded format this is a signal of frequency 2 ). This control input is now added to the flipped ˜3 B ˜2 B ˜1 B ˜ 0 by the full adders FA0 to FA3. The output of number B these adders are difference D3 D 2 D1 D0 . The result may be positive or negative. This can be distinguished by observing CF . If CF is high (signal of frequency 2 ), the result is positive and the final output S3F S2F S1F S0F is unaltered version of D3 D 2 D1 D0 . When CF is low (signal of frequency 1 ), the result D3 D 2 D1 D0 is negative. So the final result is two’s complement of the bit stream D3 D 2 D1 D0 . To confirm this controlled operation of subtraction, the AND ˜ F and C(CC ˜ F as shown in Fig. 5) is used as second ed version of C input bit along with the bits D3 D 2 D1 D0 in the respective X-OR gates of the array 2 and as the carry input to the adder FA4. The final result is given byCFinal D3F D 2F D1F D0F . Let us perform the operation of addition of the number A and B in frequency-encoded format using the adder/subtractor unit of Fig. 5 for different cases as described in Table 3 with specific examples. For addition of two numbers, result of which is less than 15 (maximum number in decimal represented by four bit binary) we have to make control input C low i.e. a signal of frequency 1 is applied to the control port. This signal of frequency 1 serves as the input to each of the X-OR gates of X-OR arrays 1 and also as carry input to the full adders FA0. For a specific example, let us consider A = 7 (decimal) and B = 5 (decimal). The result is 12 in decimal, which is a four-bit number, i.e. the carry bit is zero or a signal of frequency 1 in frequency encoded binary. The binary equivalent of 7 is A = A3 A2 A1 A0 = 1 2 2 2 and that of 5 is B = B3 B2 B1 B0 = 1 2 1 2 in frequency encoded format. Since control input C is low (signal of frequency 1 ) the X-OR gates behave like simple transmission gates. So all the bits of the number B (Addend) remains unaltered. In this situation the inputs and outputs of the full adders FA0 to FA3 are listed below based on Table 2.
FA0: Input bits A0 = 2 , B0 = 2 and input carry C = 1 . The corresponding outputs are sum S0 = 1 and carry which propagate to the full adder FA1 is 2 .
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FA1: Input bits A1 = 2 , B1 = 1 and input carry = 2 from FA1. The corresponding outputs are sum S1 = 1 and carry which propagate to the full adder FA2 is 2 . FA2: Input bits A2 = 2 , B2 = 2 and input carry = 2 from FA1. The corresponding outputs are sum S2 = 2 and carry which propagate to the full adder FA2 is 2 . FA3: input bits A3 = 1 , B3 = 1 and input carry = 2 from FA2. The corresponding outputs are sum S3 = 2 and carry which propagate to the final carry output CF is 1 . These SUM outputs propagate the next X-OR gate array 2, where ˜ F = 0 (signal of frequency 1 in frethe other input of each gate is CC quency encoded format) in this condition. So the X-OR gates in the array 2 transmit the SUM inputs S0 , S1 , S2 , and S3 without inversion. So the unmodified versions of these SUM inputs S0 , S1 , S2 , and S3 are the inputs to the corresponding full Adders FA4, FA5, FA6, and FA7 respectively. The other input (L) of each full adder of this group is a signal of frequency 1 , i.e. low in this case. Thus X-OR gate array only transmit the bits without inversion. In this situation, the inputs and outputs of the full adders FA4 to FA7 are listed below based on Table 2: ˜ F = 1 . The corresponding FA4: Input bits S0 = 1 , L = 1 and carry CC outputs are final sum S0F = 1 and carry, which propagate to the full adder FA5 is 1 . FA5: Input bits S1 = 1 , L = 1 and input carry from output of FA4 = 1 . The corresponding outputs are final sum S1F = 1 and carry, which propagate to the full adder FA6 is 1 . FA6: Input bits S2 = 2 , L = 1 and input carry = 1 . The corresponding outputs are final sum S2F = 2 and carry, which propagate to the full adder FA7 is 1 . FA3: input bits S3 = 2 , L = 1 and input carry = 1 from the output of FA6. The corresponding outputs are final sum S3F = 2 and carry output, CF = 1 . ˜ F = 1 , i.e. low. So the In this situation the final carry CFinal is CC result of addition of the numbers A (7 in decimal) and B (5 in decimal) is CFinal S3F S2F S1F S0F = 1 2 2 1 1 , which is five bit result of the addition and represents 12 in frequency encoded binary format. So the above circuit just add two four-bit number in frequency encoded format when the control input is low (C = 0 or signal of frequency 1 ) and corresponds to the first row of Table 3. Keeping the control input C low, the addition of two four- bit numbers giving result more than fifteen can be done if the carry CF of the FA3 is high, ˜ F is i.e. a signal of frequency 2 in frequency encoded format. So CC low, i.e. a signal of frequency 1 . So again no change in the bits S0 , S1 , S2 , and S3 happens and they are transmitted through X-OR gate ˜ F is a signal of array 2 without alternation. The final carry CFinal = CC ˜ are high in this case. Let us frequency 2 , i.e. high as both CF and C consider specifically the addition of 7 and 9 in frequency encoded format using the unit of Fig. 5. In frequency encoded format, A = A3 A2 A1 A0 = 1 2 2 2 (7 in decimal), and B = B3 B2 B1 B0 = 2 1 1 2 (9 in decimal). The result of operation is 16 and is given by CFinal S3F S2F S1F S0F = 2 1 1 1 1 in frequency encoded format. We shall now consider bit-wise operation: FA0: Input bits A0 = 2 , B0 = 2 and input carry C = 1 . The corresponding outputs are sum S0 = 1 and carry which propagate to the full adder FA1 is 2 . FA1: Input bits A1 = 2 , B1 = 1 and input carry = 2 from FA1. The corresponding outputs are sum S1 = 1 and carry which propagate to the full adder FA2 is 2 . FA2: Input bits A2 = 2 , B2 = 1 and input carry = 2 from FA1. The corresponding outputs are sum S2 = 1 and carry which propagate to the full adder FA2 is 2 .
FA3: input bits A3 = 1 , B3 = 2 and input carry = 2 from FA2. The corresponding outputs are sum S3 = 1 and carry which propagate to the final carry output CF is 2 .
These SUM outputs propagate the next X-OR gate array 2, where ˜ F = 0 (signal of frequency 1 in frethe other input of each gate is CC quency encoded format) in this condition. So the X-OR gates in the array 2 transmit the SUM inputs S0 , S1 , S2 , and S3 without inversion. So the unmodified versions of these SUM inputs S0 , S1 , S2 , and S3 are the inputs to the corresponding Full Adders FA4, FA5, FA6, and FA7 respectively. The other input (L) of each full adder of this group is a signal of frequency 1 , i.e. low (it is always low as mentioned earlier). Thus X-OR gate array only transmit the bits without ˜ F is a signal of frequency 2 i.e. inversion. The final carry CFinal = CC ˜ are high in this case. Thus the result of operhigh as both CF and C ation is obtained as CFinal S3F S2F S1F S0F = 2 1 1 1 1 , i.e. 16 in frequency encoded format as expected. So it is established that the device in Fig. 5 can perform addition of two binary four bit numbers in frequency encoded format and generate a five bit result in frequency encoded format in controlled way. Now we consider specific examples of subtraction for two cases. At first we subtract 5 from 7, and the result is 2. In frequency encoded format the representation of these numbers are A = A3 A2 A1 A0 = 1 2 2 2 , (7), B = B3 B2 B1 B0 = 1 2 1 2 (5) and result = CFinal D3F D2F D1F D0F = 1 1 1 2 1 (2). For this the control input C is a signal of frequency 2 ,i.e. high. This high control input C confirms the flipping of each bit of B in the X-OR gate array-1 and also addition of a high bit to the flipped version of B by the full adders FA0 to FA3 generating two’s complement. Let us see whether the device in Fig. 5 can perform this operation or not. The operation is described bit-wise as below:
FA0: Input bits A0 = 2 and input carry C = 2 . The output of the cor˜ 0 = 1 which is the input of the full adder responding X-OR gate is B FA0 along with A0 = 2 . The corresponding outputs are D0 = 1 and carry, which propagate to the full adder FA1 is 2 . FA1: Input bits A1 = 2 and input carry = 2 from FA0. The output of ˜ 1 = 2 which is the input of the the corresponding X-OR gate is B full adder FA1 along with A1 = 2 . The corresponding outputs are D1 = 2 and carry, which propagate to the full adder FA2 is 2 . FA2: Input bits A2 = 2 and input carry = 2 from FA1. The output of ˜ 2 = 1 which is the input of the the corresponding X-OR gate is B full adder FA2 along with A2 = 2 . The corresponding outputs are D2 = 1 and carry, which propagate to the full adder FA3 is 2 . FA3: input bits A3 = 1 and input carry = 2 from FA2. The output of ˜ 3 = 2 which is the input of the the corresponding X-OR gate is B full adder FA3 along with A3 = 1 . The corresponding outputs are D3 = 1 and carry, which propagate to the final carry output CF is 2 .
The carry CF = 2 (1) indicates that the result is positive. So no two’s complementation is required. So the output from the full adders stage FA0 to FA4 can be written as CF D3 D2 D1 D0 = 2 1 1 2 1 . Discarding the carry, the result is positive and final result is a four bit number 1 1 2 1 (2) or in five bit representation, CFinal D3F D2F D1F D0F = 1 1 1 2 1 . So no two’s complementation is required for this case and CF = 2 should be converted to CFinal = 1 keeping ˜ F = 1 . other bits unaltered. This is achieved by making CFinal = CC ˜ F = 1 is inserted as carry bit to the full adder FA4. Another input CC One input of the full adders FA4, FA5, FA6, and FA7 is low (L = 1 ) ˜ 0, D ˜ 1, D ˜ 2 , and D ˜ 3 respectively. In this and the other inputs are D situation, the input conditions of the full adders FA4 to FA7 is as follows:
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˜ 0 = 1 , L = 1 and carry input CC ˜ F = 1 . The corFA4: Input bits D responding outputs are final difference D0F = 1 and carry which propagate to the full adder FA5 is 1 . ˜ 1 = 1 , L = 1 and input carry from output of FA5: Input bits D FA4 = 1 . The corresponding outputs are final difference D1F = 1 and carry which propagate to the full adder FA6 is 1 . ˜ 2 = 2 , L = 1 and input carry = 1 . The correspondFA6: Input bits D ing outputs are final difference D2F = 2 and carry which propagate to the full adder FA7 is 1 . ˜ 3 = 1 , L = 1 and input carry = 1 from the output FA7: input bits D ˜ 3F = 1 and of FA6. The corresponding outputs are final difference D carry output 1 which is not utilized. So the output of the unit is given by CFinal D3F D2F D1F D0F = 1 1 1 2 1 , which is frequency encoded five bit representation of the number 2. Let us perform the operation of subtraction of a larger number from a smaller one. For example, 8 from 5 in frequency encoded format. In frequency encoded format the representation of the numbers A = 5 and B = 8 are A = A3 A2 A1 A0 = 1 2 1 2 , (5), B = B3 B2 B1 B0 = 2 1 1 1 (8) and result = CFinal D3F D2F D1F D0F = 1 1 1 2 2 (3). For this the control input C is a signal of frequency 2 ,i.e. high. This high control input C confirms the flipping of each bit of B in the X-OR gate array-1 and also addition of a high bit to each bit of the flipped version of B in the full adders FA0 to FA3 generating two’s complement. The bit stream corresponding to B = B3 B2 ˜2 B ˜1 B ˜ 0 = 1 2 2 2 . ˜ =B ˜3 B B1 B0 = 2 1 1 1 becomes B Let us see whether the device in Fig. 5 can perform the operation of subtraction or not. The operation is described bit-wise as below: FA0: Input bits A0 = 2 and input carry C = 2 . The output of the cor˜ 0 = 2 which is the input of the full adder responding X-OR gate is B FA0 along with A0 = 2 . The corresponding outputs are D0 = 2 and carry, which propagate to the full adder FA1 is 2 . FA1: Input bits A1 = 1 and input carry = 2 from FA0. The output of ˜ 1 = 2 which is the input of the the corresponding X-OR gate is B full adder FA1 along with A1 = 1 . The corresponding outputs are D1 = 1 and carry, which propagate to the full adder FA2 is 2 . FA2: Input bits A2 = 2 and input carry = 2 from FA1. The output of ˜ 2 = 2 which is the input of the the corresponding X-OR gate is B full adder FA2 along with A2 = 2 . The corresponding outputs are D2 = 2 and carry, which propagate to the full adder FA3 is 2 . FA3: input bits A3 = 1 and input carry = 2 from FA2. The output of ˜ 3 = 1 which is the input of the the corresponding X-OR gate is B full adder FA3 along with A3 = 1 . The corresponding outputs are D3 = 2 and carry, which propagate to the final carry output CF is 1 . So the output from the full adders stage FA0 to FA4 can be written as CF D3 D2 D1 D0 = 1 2 2 1 2 . CF = 1 indicates that the result is negative and final result is obtained by discarding carry (i.e. by making CFinal = 1 ) and making two’s complement of the four bit number given by the bit stream D3 D2 D1 D0 = 2 2 1 2 . The two’s complement is automatically generated by the X-OR gate array 2 and full adders FA4 to FA7 as described below. ˜ F = 2 One input of each X-OR gate of the X-OR gate array-2 is CC (as C = 2 and CF = 1 ) ensures NOT operation of the X-OR gates and flipping of the other input bits of the X-OR gates. So after the XOR gate array-2, the bit stream D3 D2 D1 D0 = 2 2 1 2 becomes ˜0D ˜1D ˜2D ˜ 3 = 1 1 2 1 . In this case CF should be converted to D ˜ F = 1 . One input CFinal = 1 . This is achieved by making CFinal = CC is L = 1 to the full adders FA4, FA5, FA6, and FA7 and the other ˜ 0, D ˜ 1, D ˜ 2 , and D ˜ 3 respectively. The carry input to the full input is D ˜ F = 2 , i.e. high. This ensures two’s adder FA4 in this condition is CC
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complementation. In this situation, the input conditions of the full adders FA4 to FA7 is as follows: ˜ 0 = 1 , L = 1 and CC ˜ F = 2 . The corresponding FA4: Input bits D outputs are final difference D0F = 2 and carry, which propagate to the full adder FA5 is 1 . ˜ 1 = 2 , L = 1 and input carry from output of FA5: Input bits D FA4 = 1 . The corresponding outputs are final difference D1F = 2 and carry, which propagate to the full adder FA6 is 1 . ˜ 2 = 1 , L = 1 and input carry = 1 . The correspondFA6: Input bits D ing outputs are final difference D2F = 1 and carry, which propagate to the full adder FA7 is 1 . ˜ 3 = 1 , L = 1 and input carry = 1 from the output FA7: input bits D ˜ 3F = 1 and of FA6. The corresponding outputs are final difference D carry output 1 which is not utilized. So the output of the unit is given by CFinal D3F D2F D1F D0F = 1 1 1 2 2 , which is frequency encoded five bit representation of the number 3. So the result of subtraction of 8 from 5 can well performed by this device as shown in Fig. 5. 4. Conclusions Frequency encoded all optical adder/subtractor unit is proposed and the algorithm is explained with suitable numerical examples. The unit can perform addition with and without carry giving five-bit result. It can subtract a smaller four-bit number from a bigger one and a bigger four-bit number from a smaller one. The proposal is based on semiconductor optical amplifier based non-linearity; four wave mixing and cross gain modulation. The device is proposed first time in frequency encoded format as far as the authors knowledge goes, and can be the building block of future all optical communication systems. The novelty of the proposal lies in the fact that SOA based polarization independent FWM with frequency encoding is used and controlled generation of result. The device can distinguish negative and positive results also. For proper operation of the proposed device the driving currents should be 200 mA for SOAs used to generate FWM. The input power of the pumps is 4–10 dBm and that of probe beam is −4 to −10 dBm. Up and down conversions done by RSOAs because of their higher conversion efficiency [35]. References [1] T. Durhuus, B. Fernier, P. Garabedian, F. Leblond, J.L. Lafragette, B. Mikkelsen, C.G. Joergensen, K.E. Stubkjaer, High speed alloptical gating using two-section semiconductor optical amplifier structure, in: Proc. CLEO’92, Anaheim, CA, 1992, pp. 552–554. [2] B. Glance, J.M. Wiesenfeld, U. Koren, A.H. Gnauck, H.M. Presby, A. Jourdan, High performance optical wavelength shifter, Electron. Lett. 28 (August (18)) (1992) 1714–1715. [3] A. Jourdan, L. Berthelon, P. Bonno, F. Bruyére, M. Chbat, C. Coeurjolly, J.Y. Emery, P. Gavignet, E. Grard, C. Janz, A. Noury, G. Soulage, T. Zami, Fully reconfigurable WDM optical crossconnect: feasibility validation and preparation of prototype crossconnect for ACTS ‘OPEN’ field trials, in: Proc. ECOC’97, vol. 3, Edinburgh, UK, September 1997, pp. 55–58. [4] R.E. Wagner, R.C. Alferness, A.A.M. Saleh, M.S. Goodman, MONET: multiwavelength optical networking (invited paper), J. Lightwave Technol. 14 (June) (1996) 1349–1355. [5] M. Berger, M. Chbat, P. Demeester, P. Godsvang, B. Hein, M. Huber, A. Jourdan, A. Leclert, R. Marz, T. Olsen, M. Sotom, G. Tobolka, B. Van Caenegem, T. Broeck, PanEuropean optical networking using wavelength division multiplexing, IEEE Commun. Mag. 35 (April) (1997) 82–89. [6] C. Taraphdar, T. Chattopadhyay, J.N. Roy, Designing of an all optical scheme for single input ternary logical operations, Optik 122 (1) (2011) 33–36. [7] T. Chattopadhyay, J.N. Roy, Polarization encoded TOAD based all optical quaternary literals, Optik 121 (7) (2008) 617–622. [8] J.N. Roy, T. Chattopadhyay, S. Manna, G.K. Maity, Polarization encoded TOAD based quaternary max gate, in: PHOTONICS, IIT Delhi, India, 2008, pp. 1–4. [9] B. Chakarborty, S. Mukhophahyay, All-optical method of implementing half and full subtractor by the use of phase encoding principle, Optik 122 (24) (2011) 2207–2210.
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