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Gallium arsenide. A new generation of integrated circuits
World Abstracts on Microelectronics and Reliability a flexible tool in the fabrication of individual nanostructure devices for q u a n t u m transport studies in mesoscopic devices smaller than an electron phase-coherence length.
Design rules for microstrip capacitance. ER1C BOGAT1N.IEEE Trans. Comport. Hybrids mfg Technol. C H M T - 1 1 , 2 5 3 (1988). Interconnect capacitance between junctions; on a chip, on a hybrid substrate, or on a printed circuit board substrate, strongly impacts digital circuit performance. Confidence in the design rule which translates the geometry and materials into capacitance per length is necessary to have confidence in any simulation model or even a rough calculation. This paper reviews those popular closed-form analytical models for microstrip geometry suitable for calculation in a spread sheet. With a few exceptions, they all agree with each other to better than 10 percent. A combination of the models of Schneider and Wheeler offer the best, simple model to estimate design tradeoffs of fabrication capability and electrical performance. A few features of this model are demonstrated. Performance limits of electrical interconnections to a highspeed chip. ATTILIOJ. RAINAL. IEEE Trans. Compon. Hybrids mfg Technol. CHMT-11, 260 (1988). An electrical model is presented to characterize the transmission path from a printed wiring board to a high-speed chip. The model accounts for the important constraint of inductive noise. The parameter values of the transmission path depend critically on the physical design of the electrical interconnections. For various input signal rise times (i.e. 0.1 ns), the following results are presented: The Reflected Waveform, the Energy of the Reflected Waveform, and the Waveform Received at the Chip. These results lead to definite performance limits (e.g. bit rate) for the electrical interconnections from a printed wiring board to a high-speed chip. For advanced physical designs, tolerable pulse waveform degradation occurs for bit rates of a few gigabits per second. However, for much higher bit rates serious pulse degradation can occur. The model can
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S ,
Design trade-offs between organic polymer-on-metal PWB's and ceramic thick-film PWB's for high-density operation using leadless ceramic chip carriers. FOSTER L. GRAY, THOMAS D. PETROVICH, JOHN K. PYLANT and JON S. PROKOP. IEEE Trans. Comport. Hybrids m(,,q Technol. C H M T - 1 1 , 2 9 8 (1988). This paper will describe the physical characteristics of a standard 1750A computer card when designing for the following parameters: 50 to 100f~ impedance, card size of 6.58 × 5.88 in, cards on 0.5in centers, and target module weight of one pound (1 lb). The construction chosen for each design will be described. Linewidths and spaces will be selected which describe a standard design. The impedance is calculated for each design and compared to the desired values. A thermomechanical analysis of the composite structure is shown to achieve a composite module coefficient of thermal expansion of 8.0 to 8.5 ppm/°C. A thermal analysis will be described to achieve m a x i m u m device junction temperatures of 105°C. The resulting polymer-on-metal and ceramic-on-metal interconnect structures are then compared based on resulting card thickness, achievable card-to-card centers, substrate weight and volume, and total card weight. Microprocessor architecture and design for GaAs technology. VELIKO M1LUTINOVIC. Microelectron. J. 19(4), 51 (1988). GaAs technology has reached the VLSI level of integration. At the same power consumption, it is up to about half an order of magnitude faster than silicon technology, and up to
1101
also be used to analyze high-speed connectors and general chip packages.
Silicon trench etching made easy. MICHAEL AMEEN, MICHAEL MONFILS and ZIA HASAN. Semiconductor int., 122 (September 1988). This isolation technique can be very effective, but extremely difficult to do on today's crowded chips. Here's how to take much of the uncertainty out of the process. Etch silicon dioxide with high selectivity and low polymer formation. C. Z. YIN, M. BEN-DOR, R. MUNDT, M. S. CHANG and R. RAFINEJAD. Semiconductor int., l l0 (September 1988). Plasma etch with a low frequency discharge, clamping, and helium cooling in a single wafer etcher and obtain high SiO z to polysilicon selectivity with minimal polymer formation. Matching vacuum pumps to processes. PETER H. SINGER. Semiconductor int., 70 (September 1988). Today's dry pumps will handle some of the most corrosive, particulate laden processes you can imagine--including metal etch and nitride CVD. Gallium arsenide. A new generation of integrated circuits. D.V. MORGAN. lEE Rev., 315 (September 1988). Silicon chips are old news. Everyone is talking about gallium arsenide. But what can it do, that silicon can't? How to automate analog IC designs. L. RICHARDCARLEYand ROB A. RUTENBAR. IEEE Spectrum, 26 (August 1988). Knowledge-based systems are relieving the labor-intensive bottlenecks usually associated with such building blocks as op amps and voltage references. Watch your vacuums and RF by PC to make your process repeatable. BRIAN CHAPMAN, DAVID GRAY, DAVID DRAGE and JOHN MOHR. Semiconductor int., 88 (September 1988). You can diagnose variations in gas flows and pressures with in-line microcomputer-based techniques.
SYSTEMS
AND
EQUIPMENTS
several orders of magnitude more radiation hard. However, it imposes radical changes in the area of computer architecture and computer designs. This paper explains several processor design strategies for GaAs technology, and emphasizes the RISC strategy. It discusses the impacts of GaAs technology on the design of C P U resources (adder, register file, etc.), system resources (cache, coprocessing, etc.), and system software resources (code optimization, hardwareto-software migration, etc. t. It summarizes the essence of one 32-bit GaAs microprocessor design, and reviews the lessons learned. Finally, it concentrates on the synergism methodology for GaAs microprocessor design; actually, on its most promising aspect: catalytic migration.
Lateral pin diodes for silicon-on-insulator monolithic microwave integrated circuits. S. Wu, T.J. LETAVlC, R.J. GUTMANN and E.W. MABY. Solid-St. Electron. 31, 1397 (1988). Surface-oriented lateral mesa PIN diodes have been fabricated for the purpose of evaluating the feasibility of a silicon-on-insulator technology for microwave applications. For these devices, heavily doped p and n regions are formed from ion-implanted polysilicon diffusion sources which abut opposite sides of an intrinsic rectangular-shaped mesa, and electrical contact to the injecting contacts can be made with low parasitic series resistance. Devices for process evaluation were fabricated using a single-crystal silicon substrate (as opposed to recrystallized silicon-on-insulator films). Both d.c. and 3 G H z electrical characteristics indicate the desired conductivity modulation of the intrinsic region under
Design rules for microstrip capacitance. ER1C BOGAT1N.IEEE Trans. Comport. Hybrids mfg Technol. C H M T - 1 1 , 2 5 3 (1988). Interconnect capacitance between junctions; on a chip, on a hybrid substrate, or on a printed circuit board substrate, strongly impacts digital circuit performance. Confidence in the design rule which translates the geometry and materials into capacitance per length is necessary to have confidence in any simulation model or even a rough calculation. This paper reviews those popular closed-form analytical models for microstrip geometry suitable for calculation in a spread sheet. With a few exceptions, they all agree with each other to better than 10 percent. A combination of the models of Schneider and Wheeler offer the best, simple model to estimate design tradeoffs of fabrication capability and electrical performance. A few features of this model are demonstrated. Performance limits of electrical interconnections to a highspeed chip. ATTILIOJ. RAINAL. IEEE Trans. Compon. Hybrids mfg Technol. CHMT-11, 260 (1988). An electrical model is presented to characterize the transmission path from a printed wiring board to a high-speed chip. The model accounts for the important constraint of inductive noise. The parameter values of the transmission path depend critically on the physical design of the electrical interconnections. For various input signal rise times (i.e. 0.1 ns), the following results are presented: The Reflected Waveform, the Energy of the Reflected Waveform, and the Waveform Received at the Chip. These results lead to definite performance limits (e.g. bit rate) for the electrical interconnections from a printed wiring board to a high-speed chip. For advanced physical designs, tolerable pulse waveform degradation occurs for bit rates of a few gigabits per second. However, for much higher bit rates serious pulse degradation can occur. The model can
6. M I C R O E L E C T R O N I C S - - C O M P O N E N T S ,
Design trade-offs between organic polymer-on-metal PWB's and ceramic thick-film PWB's for high-density operation using leadless ceramic chip carriers. FOSTER L. GRAY, THOMAS D. PETROVICH, JOHN K. PYLANT and JON S. PROKOP. IEEE Trans. Comport. Hybrids m(,,q Technol. C H M T - 1 1 , 2 9 8 (1988). This paper will describe the physical characteristics of a standard 1750A computer card when designing for the following parameters: 50 to 100f~ impedance, card size of 6.58 × 5.88 in, cards on 0.5in centers, and target module weight of one pound (1 lb). The construction chosen for each design will be described. Linewidths and spaces will be selected which describe a standard design. The impedance is calculated for each design and compared to the desired values. A thermomechanical analysis of the composite structure is shown to achieve a composite module coefficient of thermal expansion of 8.0 to 8.5 ppm/°C. A thermal analysis will be described to achieve m a x i m u m device junction temperatures of 105°C. The resulting polymer-on-metal and ceramic-on-metal interconnect structures are then compared based on resulting card thickness, achievable card-to-card centers, substrate weight and volume, and total card weight. Microprocessor architecture and design for GaAs technology. VELIKO M1LUTINOVIC. Microelectron. J. 19(4), 51 (1988). GaAs technology has reached the VLSI level of integration. At the same power consumption, it is up to about half an order of magnitude faster than silicon technology, and up to
1101
also be used to analyze high-speed connectors and general chip packages.
Silicon trench etching made easy. MICHAEL AMEEN, MICHAEL MONFILS and ZIA HASAN. Semiconductor int., 122 (September 1988). This isolation technique can be very effective, but extremely difficult to do on today's crowded chips. Here's how to take much of the uncertainty out of the process. Etch silicon dioxide with high selectivity and low polymer formation. C. Z. YIN, M. BEN-DOR, R. MUNDT, M. S. CHANG and R. RAFINEJAD. Semiconductor int., l l0 (September 1988). Plasma etch with a low frequency discharge, clamping, and helium cooling in a single wafer etcher and obtain high SiO z to polysilicon selectivity with minimal polymer formation. Matching vacuum pumps to processes. PETER H. SINGER. Semiconductor int., 70 (September 1988). Today's dry pumps will handle some of the most corrosive, particulate laden processes you can imagine--including metal etch and nitride CVD. Gallium arsenide. A new generation of integrated circuits. D.V. MORGAN. lEE Rev., 315 (September 1988). Silicon chips are old news. Everyone is talking about gallium arsenide. But what can it do, that silicon can't? How to automate analog IC designs. L. RICHARDCARLEYand ROB A. RUTENBAR. IEEE Spectrum, 26 (August 1988). Knowledge-based systems are relieving the labor-intensive bottlenecks usually associated with such building blocks as op amps and voltage references. Watch your vacuums and RF by PC to make your process repeatable. BRIAN CHAPMAN, DAVID GRAY, DAVID DRAGE and JOHN MOHR. Semiconductor int., 88 (September 1988). You can diagnose variations in gas flows and pressures with in-line microcomputer-based techniques.
SYSTEMS
AND
EQUIPMENTS
several orders of magnitude more radiation hard. However, it imposes radical changes in the area of computer architecture and computer designs. This paper explains several processor design strategies for GaAs technology, and emphasizes the RISC strategy. It discusses the impacts of GaAs technology on the design of C P U resources (adder, register file, etc.), system resources (cache, coprocessing, etc.), and system software resources (code optimization, hardwareto-software migration, etc. t. It summarizes the essence of one 32-bit GaAs microprocessor design, and reviews the lessons learned. Finally, it concentrates on the synergism methodology for GaAs microprocessor design; actually, on its most promising aspect: catalytic migration.
Lateral pin diodes for silicon-on-insulator monolithic microwave integrated circuits. S. Wu, T.J. LETAVlC, R.J. GUTMANN and E.W. MABY. Solid-St. Electron. 31, 1397 (1988). Surface-oriented lateral mesa PIN diodes have been fabricated for the purpose of evaluating the feasibility of a silicon-on-insulator technology for microwave applications. For these devices, heavily doped p and n regions are formed from ion-implanted polysilicon diffusion sources which abut opposite sides of an intrinsic rectangular-shaped mesa, and electrical contact to the injecting contacts can be made with low parasitic series resistance. Devices for process evaluation were fabricated using a single-crystal silicon substrate (as opposed to recrystallized silicon-on-insulator films). Both d.c. and 3 G H z electrical characteristics indicate the desired conductivity modulation of the intrinsic region under