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Gallium arsenide digital integrated circuits for applications above one gigahertz
1192
World Abstracts on Microelectronics and Reliability
impact noise detection (PIND) test in which a sensitive acoustic transducer listens for loose particles inside a package while the package is vibrated and shocked. Prior to instituting new assembly procedures, P I N D test yields were as low as 20 percent. We have used scanning electron microscopy (SEM) and energy dispersive analysis X-rays (EDAX) [1] to identify the particles that caused P I N D test failures and have developed and are now using assembly procedures that result in a low reject rate at P I N D testing. With these procedures, 3099 packages have been P I N D tested with 155 failures noted, resulting in yields that exceed 94 percent. The assemblies consisted o f a 1 K random access memory (RAM) die with dimensions of 3.5 x 6.1 x 0.031 m m thick which is attached with gold/silicon eutectic to a 24-pin leadless hermetic package. Packages were solder sealed in a belt furnace with a gold-tin eutectic alloy preform and a nickel and gold plated Kovar lid. The major particle type which caused P I N D test failures was determined to be gold-tin spheres from the gold-tin preform. To a much lesser degree, other particles such as calcium silicate, gold, and silicone were noted. The effect of furnace temperature, furnace ambient, and package orientation on the number of gold-tin solder balls detected in the sealed package were studied.
Wafer annealing systems. RON ISCOFF. Semicond. Int., 69 (November 1981). Conventional diffusion furnaces are the industry standard for use in wafer annealing to repair the damaged lattice structure produced when the wafer is run through the ion implant step. Other wafer annealing technologies are still climbing the learning curve, and have been confined to laboratory and research use.
Gallium arsenide digital integrated circuits for applications above one gigahertz. M. ROCHI and M. GAVANT. Acta dectron. 23 (3), 243 (1980), (in French). Gallium arsenide logic approaches are compared about their static and dynamic performances. Their respective range of applications are then clearly defined. Frequency dividers by 2 to be used as test circuits for a high speed technology are thoroughly analyzed. The design, optimization and experimental evaluation of 2 diodes-BFL (Buffered FET logic) frequency dividers by 2 and 8 are then presented. C A D tool for GaAs digital integrated circuits. M. ROCHI. Acta electron. 23 (3), 223 (1980), (in French). M E S F E T and planar Schottky diode models to be used in a C A D (computer aided design) tool for GaAs integrated circuits are presented. The physical and electrical parameters that account for the operation of these devices are thoroughly analysed. The importance of the lay-out parasitic capacitances is shown up. C A D optimisation results of a binary frequency divider by 2 are compared with the experimental performances obtained on fabricated circuits.
Duplicateur de masques a rayons X pour lithographic submicronique. B. FAY. Revue tech. Thomson-CSF 13 (3), 541 (1981), (in French). X-ray replication is a lithographic technique well adapted for applications requiring the utmost resolution. T h e practical application of this new masking technique to submicron lithography results in the realization of an X-ray replication system which is described in this paper. This system has the capability to replicate features of minim u m dimensions as small as 0.2 lam as well as to superpose successive masks with an accuracy of 0.05 p.m. After a review of some particular aspects of X-ray lithography, we describe the system realized and present some preliminary results.
A new technique for the evaluation of the temperatures arising from some geometries which commonly occur in microelectronics. D. J. DEAN. Int. J. Numerical Methods Enyng 17, 1069 (1981). This paper presents a series s u m m a t i o n computation method for calculating temperatures arising from
some geometries which commonly occur in microelectronics. The method, which is suitable for use with pocket calculators, involves an exchange of terms with those of a known series. At each stage of the summation a state of convergence (SOC) is calculated in terms of the m a x i m u m possible error, thus enabling the calculation to be terminated as soon as the required accuracy has been obtained.
C-MOS support logic helps build unified, high-speed systems. KEN KARAKOTSIOSand LARRY WAKEMAN. Electronics, 137 (December 15, 1981). High-speed process gives gates lowpower Schottky T T L speed while retaining the advantages of metal-gate C - M O S units. C P / M - - A route to cheap software. 1. N. PARKER. Microelectron. Reliab. 21 (3), 323 11981 ). C P / M is a well proven disk based operating system for 8080 and Z80 based microcomputers. It is highly popular amongst computer hobbyists, and this paper will show that it can also be of great use to professionals. Besides being very flexible, it provides easy access to an extensive software library.
An improved architecture for advanced universal microprocessor development systems. ROGER MATON~ Microelectron. Reliab. 21 (3), 315 (1981). Taken fiom the standpoint of a microprocessor systern developer's needs, rather than known solutions, the current techniques of in circuit emulation are explored as they meet and fail to meet developers growing demands. Support requirements are addressed in terms of the separate and concurrent requests of the system software and hardware developers as a target system is developed. A development system designed to meet these current needs is discussed and a look is taken at the characteristics of today's development systems that will be important for their viability in the future.
Dopant profiles on thin layer silicon structures with the spreading resistance technique. R. G. MAZUR and G. A. GRUBER. Solid St. Teclmol., 64 (November 1981). Recent improvements in spreading resistance measurements are detailed. It is shown that combining the use of controlled low penetration probes with diamond bevelling and improved data correction procedures permits detailed profiles on in-process silicon structures with spatial resolution below 1000 A.
Silicon epitaxy for high performance integrated circuits. G. R. SRINIVASAN. Solid St. Technol., 101 (November 1981). The continuing evolution towards VLSIC and VHSIC technologies has placed exacting demands on the silicon epitaxial process in terms of reduced film thickness, minimized autodoping, low epitaxial temperatures, very low defect levels, and good film uniformities. These challenges have produced innovative approaches to epitaxial processes and also have generated good understanding of the process basics and the interplay between the process and device parameters. This paper discusses some of these advances, with an emphasis on device applications. A focus on the CVD epitaxial technique is chosen in view of its vast technological importance.
Liquid nitrogen and wafer fabrication problems. MINGKWANG LEE. Solid St. Technol., 94 (December 1981 ). Contamination in liquid nitrogen handling equipment is considered to be one of the factors resulting in engineering problems in older wafer fabrication plants. Installation of liquid nitrogen filters and gas purifiers is recommended for eliminating these problems. An in-line gas analyzer is also suggested for monitoring the gas assay.
Lift-off techniques for fine line metal patterning. J. M. FRARY and P. SEESE. Semicond. Int., 72 (December 1981). Understanding and developing lift-off techniques for wafer processing offers fabricators the potential of obtaining excellent metal pattern line width control in the micron and submicron realms. The lift-off technique is a viable and valuable technique for fine line metal patterning.
World Abstracts on Microelectronics and Reliability
impact noise detection (PIND) test in which a sensitive acoustic transducer listens for loose particles inside a package while the package is vibrated and shocked. Prior to instituting new assembly procedures, P I N D test yields were as low as 20 percent. We have used scanning electron microscopy (SEM) and energy dispersive analysis X-rays (EDAX) [1] to identify the particles that caused P I N D test failures and have developed and are now using assembly procedures that result in a low reject rate at P I N D testing. With these procedures, 3099 packages have been P I N D tested with 155 failures noted, resulting in yields that exceed 94 percent. The assemblies consisted o f a 1 K random access memory (RAM) die with dimensions of 3.5 x 6.1 x 0.031 m m thick which is attached with gold/silicon eutectic to a 24-pin leadless hermetic package. Packages were solder sealed in a belt furnace with a gold-tin eutectic alloy preform and a nickel and gold plated Kovar lid. The major particle type which caused P I N D test failures was determined to be gold-tin spheres from the gold-tin preform. To a much lesser degree, other particles such as calcium silicate, gold, and silicone were noted. The effect of furnace temperature, furnace ambient, and package orientation on the number of gold-tin solder balls detected in the sealed package were studied.
Wafer annealing systems. RON ISCOFF. Semicond. Int., 69 (November 1981). Conventional diffusion furnaces are the industry standard for use in wafer annealing to repair the damaged lattice structure produced when the wafer is run through the ion implant step. Other wafer annealing technologies are still climbing the learning curve, and have been confined to laboratory and research use.
Gallium arsenide digital integrated circuits for applications above one gigahertz. M. ROCHI and M. GAVANT. Acta dectron. 23 (3), 243 (1980), (in French). Gallium arsenide logic approaches are compared about their static and dynamic performances. Their respective range of applications are then clearly defined. Frequency dividers by 2 to be used as test circuits for a high speed technology are thoroughly analyzed. The design, optimization and experimental evaluation of 2 diodes-BFL (Buffered FET logic) frequency dividers by 2 and 8 are then presented. C A D tool for GaAs digital integrated circuits. M. ROCHI. Acta electron. 23 (3), 223 (1980), (in French). M E S F E T and planar Schottky diode models to be used in a C A D (computer aided design) tool for GaAs integrated circuits are presented. The physical and electrical parameters that account for the operation of these devices are thoroughly analysed. The importance of the lay-out parasitic capacitances is shown up. C A D optimisation results of a binary frequency divider by 2 are compared with the experimental performances obtained on fabricated circuits.
Duplicateur de masques a rayons X pour lithographic submicronique. B. FAY. Revue tech. Thomson-CSF 13 (3), 541 (1981), (in French). X-ray replication is a lithographic technique well adapted for applications requiring the utmost resolution. T h e practical application of this new masking technique to submicron lithography results in the realization of an X-ray replication system which is described in this paper. This system has the capability to replicate features of minim u m dimensions as small as 0.2 lam as well as to superpose successive masks with an accuracy of 0.05 p.m. After a review of some particular aspects of X-ray lithography, we describe the system realized and present some preliminary results.
A new technique for the evaluation of the temperatures arising from some geometries which commonly occur in microelectronics. D. J. DEAN. Int. J. Numerical Methods Enyng 17, 1069 (1981). This paper presents a series s u m m a t i o n computation method for calculating temperatures arising from
some geometries which commonly occur in microelectronics. The method, which is suitable for use with pocket calculators, involves an exchange of terms with those of a known series. At each stage of the summation a state of convergence (SOC) is calculated in terms of the m a x i m u m possible error, thus enabling the calculation to be terminated as soon as the required accuracy has been obtained.
C-MOS support logic helps build unified, high-speed systems. KEN KARAKOTSIOSand LARRY WAKEMAN. Electronics, 137 (December 15, 1981). High-speed process gives gates lowpower Schottky T T L speed while retaining the advantages of metal-gate C - M O S units. C P / M - - A route to cheap software. 1. N. PARKER. Microelectron. Reliab. 21 (3), 323 11981 ). C P / M is a well proven disk based operating system for 8080 and Z80 based microcomputers. It is highly popular amongst computer hobbyists, and this paper will show that it can also be of great use to professionals. Besides being very flexible, it provides easy access to an extensive software library.
An improved architecture for advanced universal microprocessor development systems. ROGER MATON~ Microelectron. Reliab. 21 (3), 315 (1981). Taken fiom the standpoint of a microprocessor systern developer's needs, rather than known solutions, the current techniques of in circuit emulation are explored as they meet and fail to meet developers growing demands. Support requirements are addressed in terms of the separate and concurrent requests of the system software and hardware developers as a target system is developed. A development system designed to meet these current needs is discussed and a look is taken at the characteristics of today's development systems that will be important for their viability in the future.
Dopant profiles on thin layer silicon structures with the spreading resistance technique. R. G. MAZUR and G. A. GRUBER. Solid St. Teclmol., 64 (November 1981). Recent improvements in spreading resistance measurements are detailed. It is shown that combining the use of controlled low penetration probes with diamond bevelling and improved data correction procedures permits detailed profiles on in-process silicon structures with spatial resolution below 1000 A.
Silicon epitaxy for high performance integrated circuits. G. R. SRINIVASAN. Solid St. Technol., 101 (November 1981). The continuing evolution towards VLSIC and VHSIC technologies has placed exacting demands on the silicon epitaxial process in terms of reduced film thickness, minimized autodoping, low epitaxial temperatures, very low defect levels, and good film uniformities. These challenges have produced innovative approaches to epitaxial processes and also have generated good understanding of the process basics and the interplay between the process and device parameters. This paper discusses some of these advances, with an emphasis on device applications. A focus on the CVD epitaxial technique is chosen in view of its vast technological importance.
Liquid nitrogen and wafer fabrication problems. MINGKWANG LEE. Solid St. Technol., 94 (December 1981 ). Contamination in liquid nitrogen handling equipment is considered to be one of the factors resulting in engineering problems in older wafer fabrication plants. Installation of liquid nitrogen filters and gas purifiers is recommended for eliminating these problems. An in-line gas analyzer is also suggested for monitoring the gas assay.
Lift-off techniques for fine line metal patterning. J. M. FRARY and P. SEESE. Semicond. Int., 72 (December 1981). Understanding and developing lift-off techniques for wafer processing offers fabricators the potential of obtaining excellent metal pattern line width control in the micron and submicron realms. The lift-off technique is a viable and valuable technique for fine line metal patterning.