Ge+ ion implantation — a competing technology?

......... CRYSTAL OROWTH

ELSEVIER

Journal of Crystal Growth 157 (1995) 147-160

Ge ÷ ion implantation - a competing technology? P.L.F. H e m m e n t a. * , F. Cristiano a, A. Nejim a S° L o m b a r d o b, K.K. Larssen b F. Priolo b R.C. Barklie ~ Department of Electronic and Electrical Engineering, University of Surrey, Guildford, Surrey, GU2 5XH, UK b University of Catania, Catania, Italy c Trinity College, Dublin, Ireland

Abstract

Difficulties with the incorporation of SiGe epitaxial growth technologies into established silicon whole wafer processes are delaying the commercialisation of SiGe technology. In this paper the possibility of using an alternative, well proven technology, namely ion implantation, is considered. Experiments reported in the literature suggest that both strained and relaxed device worthy SiGe layers, with graded interfaces, can be synthesised by Ge + ion implantation followed by a two step thermal anneal to achieve solid phase epitaxial growth and annihilation of electrically active defects. It is concluded that for specific device architectures both heterojunction bipolar and MOS devices could be commercially realised whilst other applications, such as buried SiGe waveguides and devices incorporating compositionally graded layers, may also be viable. The technology warrants further investigation.

1. Introduction

Epitaxial deposition techniques were developed during the 1960s and 1970s and applied, in particular, to I I I - V materials both to realise advanced device structures incorporating abrupt interfaces and to grow high purity materials. For the group IV semiconductors, bandstructure engineering, conceptually proposed during the 1950s [1], was realised during the 1980s when MBE was used to grow SiGe/Si heterostructures. At that time MBE materials were of an inadequate quality for production devices and considerable effort was directed to the

* Corresponding author.

development of alternative CVD approaches. Developments came fast with high quality layers being achieved and in 1987 the first SiGe HBT devices were reported. With the performance benefits confirmed by several groups, the thrust began to refine growth technologies and optimise device structures to enable SiGe to be integrated into silicon whole processes without compromising yield and whilst retaining the performance benefits reported in the research laboratories. Despite the worldwide drive to commercialise SiGe technology, industry is frustrated by problems which are delaying the realisation of volume production. These production problems arise from the difficulties of scaling epitaxial deposition processes, especially when the requirement is to process large wafers (6", 8" and eventually larger) on which low defect density layers are to be grown with good

0022-0248/95/$09.50 © 1995 Elsevier Science B.V. All rights reserved SSD1 0022-0248(95)00418- 1

P.L.F. Hemment et al./Journal of Crystal Growth 157 (1995) 147-160

148

uniformity of thickness and composition and consistency from wafer to wafer and batch to batch. History shows that the process engineering community is conservative, being more willing to accept evolutionary changes in processing technologies rather than revolutionary changes. This is especially true in microelectronics where steady refinements of the processing technologies have led to the year on year growth in circuit performance, functionality and volume production. Because of the successes of this evolutionary approach and due to current problems of commercialising SiGe, it is appropriate to explore an alternative, well proven, route to achieve the SiGe layered structures required for the next generation of silicon based devices. In this paper the prospects for ion beam processing (IBP), specifically ion implantation of Ge ÷ into silicon, to achieve SiGe/Si heterostructures is considered in terms of its ability to realise device worthy structures in a volume production environment. To do so we shall consider some aspects of the underlying physics, discuss recent experimental results and present examples of test structures and devices that have been fabricated and measured electrically. It will be seen that synthesis of SiGe layers is necessarily a two step process, namely (i) ion implantation plus (ii) thermal processing to achieve solid phase epitaxial growth (SPEG) and defect annihilation.

2. Ion beam processing 2.1. The benefits

in silicon

technology

First we must consider the strengths of silicon technology which are (i) a huge worldwide investment which creates its own commercial and technological momentum, (ii) the low cost/high reliability of silicon devices, and (iii) the availability of large area high quality substrates (6", 8" and, shortly, larger). These strengths should not be compromised by the introduction of a new process step. The move to all dry vacuum compatible processing has been made possible thanks to the successful development of plasma and ion beam technologies where doping by ion implantation is a critical enabling technology for the realisation of small geometry, high density circuits. The strengths of ion im-

plantation, especially in the present context, are many and include: Compatibility

with silicon processing.

- energy and dose can be readily adjusted to achieve specific concentration - depth profiles. • Non-equilibrium process - all chemical species can be implanted and buried layers achieved without recourse to thermodynamics (diffusion). • Low contamination - isotopically pure beams are available. • D i r e c t e d b e a m s - self alignment can be achieved. • Isotropic i m p l a n t s - plasma emission methods enable conformal doping to be achieved. • S c a l a b l e - t h e process is scalable and can be modelled. • Reproducibility - concentration depth profiles are predictable and reproducible. Either a buried double Gaussian [2] or a surface layer (sputter limited) can be found. Ion implanted depth profiles inevitably have graded interfaces due to the random nature of the fast ion energy loss processes. Additionally, deposition rates, as defined by the build up of the areal density of implanted ions (cm -2 s-1), are low. For example, the mass transport of Ge in an ion beam of current density 100 ~ A cm-2 has an associated growth rate of about 1 A s-l, assuming bulk properties and no sputtering, however, to achieve this high arrival rate the power loading of the wafer will be high, namely, 7 W c m - 2 for a 100 ~A c m - 2 beam at 70 keV. Thus beam heating will be significant unless active cooling is employed [3]. Fast ions come to rest in the target (wafer) by transferring their kinetic energy to the lattice atoms which leads to Frenkel pair production ( E a typically 12-15 eV) and, thus, the damage which accumulates must be annealed if the crystal perfection of the semiconductor target is to be recovered. In passing, it is noted that under conditions where compounds are synthesised by ion implantation, for example by the implantation of O ÷ or Co + ions into silicon to form SiO 2 o r C o S i 2 , respectively [3], the graded interfaces may be transformed into abrupt interfaces during subsequent high temperature processing. This mass transport of the implanted species occurs through the influence of chemical and thermodynamic driving forces. This option is not availGood

control

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P.L.F. Hemment et al. / Journal of Crystal Growth 157 (1995) 147-160

able for the ion beam synthesis of Sil_xGex, or S i l _ y _ x G e x C y alloys although it is a factor to be considered during high temperature processing [4] of C ÷ implanted layers as crystalline SiC is liable to precipitate, as is touched on below. 2.2. Germanium profiles

Germanium (Ge ÷) implantation into silicon has been studied over many years as this heavy group IV element has been used to preamorphise silicon prior to dopant implantation, especially B +, as a means of avoiding concentration-depth profile broadening by ion channelling [3,5]. This application required a dose of order 1015 Ge + cm -2 to be implanted, typically at an energy of 100-200 keV. Under these conditions the peak Ge concentration is much less than 1 at%. Synthesis of a SiGe alloy layer with a sufficiently high Ge content (say 10 at%) to achieve worthwhile bandgap narrowing requires doses in the range 1016-1017 Ge + cm -2. Table 1 lists representative 70, 140 and 400 keV Ge + ion range statistics and peak volume concentrations, which for a dose of 3 X 1016 Ge + cm -2 are 11, 6.2 and 2.6 at%, respectively [2]. Fig. l a shows the computed [2] depth profiles, which can be represented by two half Gaussians [3]. Thus the alloy layer is buried and has broad, graded interfaces. Fig. lb shows a series of computed 40 keV Ge + profiles which evolve with increasing dose when sputtering is the dominant mechanism controlling the final Ge distribution. This is the case when the ion energy is low (tens of keV) and the dose is high ( > 1017 Ge + c m - 2 ) . Under these latter conditions a surface layer is formed with an almost flat topped concentration distribution close by the surface. It is evident from the literature that profiles generated by existing process models, such

Table 1 Range statistics for Ge ÷ implanted into silicon and taken from TRIM Ion Projected range, Straggle, energy .~p (.~.) &.~p ( f k ) (keV) 70 511 156 140 937 265 400 2625 634

as TRIM [2], quite closely predict the implanted profiles [6]. Experiments show that diffusional broadening is not a problem during elevated temperature implants up to 450°C [7], during a fumace anneal at 800°C for one hour [8] or rapid thermal annealing at 1100°C for ten seconds [9]. In the latter case the diffusion coefficient is about 1 X 10-14 cm 2 s-1 corresponding to a diffusion length of order 3 nm [9]. It is noted that strained and relaxed SiGe layers (with an excess of Si) exhibit different physical properties, for example regrowth (see below) and diffusion [10]. Experiments show that at temperatures < 1030°C the diffusion of Ge increases exponentially with compressive strain whilst the diffusion of B decreases [11,12]. 2.3. Damage accumulation and SPEG Damage accumulation: Build up of the Ge profile will be accompanied by an increase in the lattice damage which, in the low dose limit, will take the form of discrete point defects, small defect clusters and isolated disordered regions [3]. With increasing dose these defect regions will begin to interact, overlap and eventually coalesce to form an amorphous phase of the SiGe alloy. At ambient temperature the critical dose of 200 keV Ge + ions to form a continuous buried amorphous layer (at a depth of 1000 ,~) is about 5 x 1013 Ge + cm -2, assuming bulk Si properties and a critical energy deposition rate of 10 e V / , ~ [13]. With increasing dose the amorphous layer broadens and reaches the surface at a dose of 3 x 1014 Ge + cm -2 and achieves a total thickness of about 3000 ,~ for a dose of 6 × 1017 Ge ÷ c m - 2 . For 800 keV Ge ÷ ions the dose required to form a buried amorphous layer is 7 X 10 t3 Ge ÷ c m - 2 with the layer extending up to the surface for

peak volume concentrations (cm -3) for an implanted dose of 3 x Peak volume concentration(cm -3 ) (Dose = 3 X 1016 Ge + cm-2) 5.5 X 10 21 3.1 X 10 21 1.3 X 102.

Peak composition compositions (Ge at%) 11 6.2 2.6

1016

Ge ÷ cm 2,

Ratio of peak

1 0.56 0.24

150

P.L.F. Hemment et al. / Journal of Crystal Growth 157 (1995) 147-160

Dynamic TRIM.

A

Ge implants into Si (Dose of 3E16/cm sq).

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P.L.F. Hemment et al./Journal of Crystal Growth 157 (1995) 147-160

/

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a dose of 5 × 10 ~4 Ge ÷ cm -2 [13]. Experiments have shown that thermal annealing of radiation damage created during ion implantation is most easily achieved if the implanted layer is amorphous [3]. As self annealing during ion implantation is highly sensitive to the wafer temperature, amorphisation is best achieved by cooling the wafer during implantation. Alternatively postamorphisation by Si ÷ ion implantation can be employed as the final process step before SPEG, thus ensuring that the structure is completely amorphous [14]. A different strategy is to enhance dynamic annealing by implanting into a heated wafer [15]. SPEG: Transformation of the amorphous SiGe

layer into the crystalline phase is achieved by thermally activated SPEG, typically at a temperature in the range 550-650°C [3]. Earlier extensive studies of the SPEG of amorphous Si have shown that the regrowth is planar and can be described in terms of local bond breaking at defect sites at the amorphous/crystalline ( a / c ) interface [16]. The process is characterised by an activation energy of 2.68 eV where the regrowth rate (cm s - t ) is linear with time but dependent upon crystal orientation, growth being fastest in the (100) plane and slowest in the (111). Low concentrations of electrically active impurities increase the rate whilst impurities such as O or C have the opposite effect [3].

Fig. 1. Concentration depth profiles of Ge + ions implanted into silicon (a) buried layers typical of high energy, low dose implantation, and (b) sputter limited profiles for 40 keV Ge + into Si for doses of 3 × 10 is, 3 × 1016 and 3 × 1017 cm -2. Profiles calculated by dynamic TRIM [2].

152

P.L.F. Hemment et al. / Journal of Crystal Growth 157 (1995) 147-160

Regrowth of SiGe alloy layers on Si (100) substrates has been investigated by Paine and coworkers [6,17,18]. In their experiments silicon wafers were preamorphised to a depth of 3400 A by a prior implantation of 3 × 10 Is Si ÷ cm -2 at 170 keV [6]. Subsequently these wafers were implanted with 9.6 × 1016 Ge ÷ cm -2 at 200 keV to form a SiGe layer with graded interfaces and a peak concentration of about 14 at%. The Ge profile was contained within the preamorphised layer, thus ensuring that the initial regrowth was homoepitaxial. Cross-sectional TEM confirmed that during the initial stages of regrowth ( T = 590°C) the a / c interface was planar with a morphology characteristic of bulk silicon. Planar regrowth continued with the a / c interface advancing into the SiGe layer until it reached a position where the Ge content was ~ 10 at%, when the growth mode changed and a faceted morphology that exposed four (111) crystal surfaces developed. This produced " V " shaped features which nucleated within a band of tens of nanometers in thickness. Microtwins and stacking faults lying parallel to the facets were observed. These authors reported similar defects in other layers, including MBE grown structures with abrupt interfaces, and concluded that the faceted (111) microstructure was related to the presence of planar faults which relieve the strain. Their presence signals that the layer has relaxed and, in these particular Ge implanted layers, only about 7-10 at% Ge could be accommodated during SPEG, without relaxation occurring. Fig. 2 is a schematic of the regrowth of these heterostructures, showing the development of the observed four (111) surfaces. The authors noted also, that in Si0.TGe0.3 at about 590°C the regrowth velocity of bulk Si is 51 + 5 nm min-1, which reduces to 21 + 5 nm min-i during (relaxed) (111) faceted regrowth of the alloy. Paine et al. [17] subsequently developed a model to predict the critical Ge ÷ dose above which relaxation of the compressive strain will occur during SPEG. The model combines the critical thickness [19] and strain energy [6] concepts to determine the onset of strain relaxation in graded layer heterostructures. Three types of strain relieving defects were considered and, by defining the forces acting on a specific defect, the authors determine the dependence of the critical Ge + peak concentration upon ion energy. This dependence is shown in Fig. 3 for 60 °

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Fig. 3. Dependence upon energy of the critical peak concentration for Ge ÷ implanted into silicon. The sample with a peak Ge concentration of 13 at% contained extended defects [17].

dislocations and stacking faults bound by either 90 ° or 30° partial dislocations. The region below the three curves defines the combination of Ge concentrations and ion energies which can be employed to form a strained alloy layer. Experimental data is included in the figures for peak concentrations of 13%, 7% and 3.3% and show acceptable agreement with the calculations. Paine et al. note the absence of 609 misfit dislocations in the recrystallised layers and conclude that the regrowth temperature ( < 600°C) was too low for dislocation motion to occur in the crystalline alloy. They conclude that the .layers formed by 200 keV Ge + ion implantation ~l~7 be regrown by SPEG ( < 600°C) without the intro.'uction of defects, provided the peak concentration is less than about 7 at%, whilst a 70 keV implanted layer will regrow without relaxation up to about 10 at%. Calculations, based upon the Paine model of the critical depth of the strain relieving defects, have been made by Elliman et al. [16] who report good agreement with experimental data, as shown in Fig. 4. The epitaxial regrowth of amorphous SiGe has been investigated by Elliman et al. [16], using time resolved reflectivity (TRR), and compared with SPEG of amorphous Si and Ge layers. The regrowth rate is found to increase with increasing Ge content; however, the activation energy does not vary in a simple, monotonic manner between the values for Si (2.7 eV) and Ge (2.0 eV) but has a maximum value of about 2.9 eV at a Ge composition of 30 at% [16].

P.L.F. Hemment et al./Journal of Crystal Growth 157 (1995) 147-160

This behaviour is unexpected and is inconsistent with the bond breaking model for SPEG as the S i - G e bond is known to be weaker than the Si-Si bond. Similar TRR analyses of thin deposited SiGe layers have shown stress related variations in the regrowth rate. Elliman et al. also report regrowth of Ge ÷ implanted layers formed by doses of 8.4 × 1016 and 2.3 × 10 ]7 Ge ÷ cm -2 at 800 keV. These doses are less than and greater than the critical dose for relaxation, respectively [17]. Figs. 5a and 5b show the SPEG velocity at 600°C as a function of depth superimposed upon the Ge distributions in the two above mentioned implanted layers. For the low dose sample (Fig. 5a) the rate decreases monotonically from the homoepitaxial rate for Si at this temperature as the a / c interface moves through the alloy region. Similar values are initially recorded for the high dose sample (Fig. 5b) but a sudden decrease to a minim u m occurs as regrowth sweeps through the alloy layer. Near the centre of the layer the rate increases and assumes a near constant value as it approaches the free surface. Elliman et al. have successfully correlated this TRR data with measured values of the strain, using X-ray diffraction, and the specific depths at which strain relaxation occurs during regrowth, as defined by the nucleation and growth of extended defects observed by TEM, has been determined.

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as a

function of depth for samples implanted with 800 keV Ge + ions and annealed at 600°C (a) 8.4X 1016 Ge + cm -~, and (b) 2.3× 1017 Ge + cm -2 [16].

They conclude that the reduction in the SPEG rate at the depth of 600 nm (Fig. 5b) is strain related and that upon relaxation, which commences when the a / c interface is at a depth of about 500 nm, the rate increases to a near constant value as further regrowth of the relaxed alloy proceeds. In summary, it is found that fully strained SiGe layers can be synthesised by Ge ion implantation and subsequent SPEG (for example, see Fig. 7) provided that the Ge dose (and hence peak Ge content) is below the energy dependent critical value. For higher doses relaxation occurs through the nucleation and growth of extended defects. The measured data is in good agreement with the critical depth predicted by the model proposed by Paine et al. [ 17] and shown in Fig. 4. This behaviour is in marked contrast to MBE and CVD alloys, which can be grown as metastable layers with thicknesses exceeding their critical thicknesses [19].

3. Implantation strategies

Concentration

Fig. 4. Critical thickness calculation by Elliman et al. [16] for 800 keV Ge + implanted into silicon. Calculations are for stacking faults and 90° partial dislocations using the theory of Paine et al. [6].

A number of different implantation strategies have been investigated in an endeavour to achieve greater control over the Ge and defect distributions. The methods are shown schematically in Fig. 6 and are

154

P.L.F. Hemment et al./ Journal of Crystal Growth 157 (1995) 147-160

ImplantationStrategies (IBS) C "~

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Fig. 6. Schematic showing implantation strategies as described in the text.

(a) Ge ÷ implantation into silicon, (b) coincident Ge ÷ and C ÷ implantation profiles to control strain through the incorporation of the smaller carbon atoms on substitutional sites [20], (c) postamorphisation (EPIFAB [14]) to render the complete structure amorphous to a depth much greater than the Ge profile, and (d) co-implantation of Ge ÷ and C + where the carbon profile is centred at the a / c interface and is designed to inhibit the formation of end of range (EOR) defects during annealing [21]. Fig. 7b shows an example of the successful synthesis of

an alloy layer (strategy a) with a peak Ge concentration of 2.5 at% (400 keV, 3 × 1016 Ge ÷ cm -2, 700°C) where only EOR defects are observed [14] at the depth of the original a / c interface (Fig. 7a). Fig. 7c illustrates an application of the EPIFAB concept (strategy c) where the EOR defects now occur at a depth of about 1 /~m, and potentially have use as proximity gettering centres. Figs. 8a and 8b show cross-sectional and plan view TEM micrographs of EOR defects whilst Fig. 8c confirms annihilation of these defects by a subsequent C ÷ implantation (strategy d) prior to annealing. Much interest has been shown in strategy b because of the potential for independent control of the composition and strain in the synthesised layer [21-23], which opens the way for novel bandstructure engineering. Theoretical studies by Soref [24] suggest that lattice matching to Si can be achieved by the addition of C to about 10% of the Ge concentration. Compensation of the (Ge) compressive strain in CVD SiGe layers by C ÷ implantation into preamorphised layers has been demonstrated by Strane et al. [25]. Implanted C ÷ in Si is also known to act as a sink for excess interstitials [26], which is beneficial for the control of

Fig. 7. Cross-sectional TEM micrographs showing the microstructure of synthesized structures using strategies (a) and (c), def'med in Fig. 6

[14.1.

P.L.F. Hemment et al. /Journal of Crystal Growth 157 (1995) 147-160

Fig. 8. TEM micrographs of silicon implanted with 70 keV Ge ÷ ions to a dose of 2.5× 1016 cm -2 ( ~ 13 at%) after SPEG, (a) cross-section showing a buried layer of defects, (b) plan view of defects identified as extrinsic dislocation loops, (c) Co-implantation with 30 keV C ÷ ions to a dose of 3 × 10 j5 cm -2 inhibited the formation of observable defects [9].

155

Additional strategies include Ge + implantation into heated substrates, over the temperature range, ambient to 500°C, which has been investigated by Chen et al. [15]. In these experiments samples were subsequently annealed at 950°C for one hour. During low temperature implantation, from ambient to 100°C, an amorphous layer, with a broad band of damage beneath, was formed. During high temperature implantation (200-500°C) dynamic annealing inhibited amorphisation but upon subsequent annealing (950°C) a nearly defect free surface layer of thickness 150 nm was achieved. This group concluded that implantation at an elevated substrate temperature improves the crystallinity of the surface layer and inhibits the formation of EOR defects. Several groups [27,28] have reported the epitaxial (MBE) growth of SiGe on silicon on insulator (SO1) structures, again with the objective of accommodating strain and reducing the defect density. Recently, Hollander et al. [29] have reported Ge ÷ implantation to synthesise strain relieved SiGe layers on SIMOX/SOI substrates. Particular experiments involved implantation of 3 × 1017 Ge + cm -2 into the silicon overlayer of a SO1 substrate at 450°C. During subsequent RTA at 1290°C the crystalline quality of the layer recovered and Ge redistribution occurred to form a homogeneous, strain relieved layer, which in this case had a composition Si0.87Ge0.13. An abrupt alloy/oxide interface resulted, which HRTEM showed is within a few monolayers thickness, as the buried oxide acts as an efficient diffusional barrier. Exploratory ion-beam-induced epitaxial crystallisation (IBIEC) of Ge and Ge + C implanted layers has been reported [16,20]. Whilst this approach has some novel features and allows the growth temperature to be significantly reduced, it is reported by Elliman et al. [16] that both random and epitaxial crystallisation can occur in thin layers and in layers with a high Ge content, thus degrading the quality.

4. Device structures

4.1. Bipolar extended defects [3], however, the thermal budget and maximum temperature during annealing must be tightly controlled to avoid precipitation of SiC [4].

The formation of Ge + implanted SiGe/Si heterostructures for device applications has been reported by Fukami and coworkers in a number of

156

P.L.F. Hemment et al./ Journal of Crystal Growth 157 (1995) 147-160

publications [22,30-32]. The justification given by the authors is the compatibility of the Ge ÷ implantation process with VLSI processing and the potential for selected area synthesis. In these experiments Ge ÷ was implanted into an epitaxial Si layer to form a graded bandgap HBT structure, this being an extra step in an otherwise established Si bipolar (BJT) process [30]. The dose was 3 X 1016 Ge ÷ cm -2 at 160 keV implanted into a cooled wafer ( - 1 0 0 ° C ) through windows opened in a SiO 2 mask. Measured SIMS profiles of the Ge and simulated dopant distributions are shown in Fig. 9, where the emitter and base widths are 20 and 100 nm, respectively. The peak Ge concentration is about 7 at%, which is just less than the critical dose predicted by the model due to Paine et al. [17]. The structures were regrown at 700°C for eight hours followed by an anneal at 900°C for ten minutes to activate a n-type As ÷ implanted emitter. Fig. 10 is a schematic cross-section of the device showing that the Ge profile extends into the n - collector (see Fig. 9). Cross-section TEM showed EOR defects at the position of the original crystalline/amorphous ( c / a ) interface, however, the authors make no reference to lateral EOR defects within the p+ base. The SiGe HBT devices had a maximum gain of about 40 while reference Si BJTs on the same chip had a gain of 100. This degradation of gain was attributed to carder recombination associated with defects. A smaller difference existed in the maximum cut-off frequencies, which were measured as 8 GHz (HBT) and 11 GHz

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(BJT), where the better than expected performance was attributed to the drift field in the graded base region. In a subsequent paper [31], test structures were fabricated to simulate the base-collector ( b - c ) region of a bipolar device. The Ge ÷ ions (5 × 1016 Ge ÷ c m - 2 , 160 keV) were again implanted through a deposited SiO 2 window into the p- and n-type layers and annealed as before [30]. The Ge content was 12 at% and the distribution extended into the n-layer (mimicking the collector with a phosphorus concentration of 4 × 1016 cm-3). Two types of defect were identified by XTEM namely, near surface defects which extended to a depth of ~ 100 nm and EOR defects at a depth of about 300 nm. Samples implanted at - 100°C instead of ambient (27°C) had a much reduced density of EOR defects which was reflected in improved electrical characteristics (ideality factor and leakage currents). Other experiments [22,32] using these structures showed that co-implantation of 15 keV C ÷ to a dose of 3 × 1015 C + cm -2 substantially reduced the near surface defects with a reduction in the reverse bias leakage, but with a leakage still substantially larger than that measured in an unimplanted silicon diode. The authors concluded that the presence of Ge and C within the base increases the base resistance either through B deactivation or dopant compensation. It is noted, also, that independent studies of 1 X 1015 C + cm -2 implanted into Si samples which were annealed at 800°C show a peak C related donor concentration of order 1017 cm -3 [33]. The authors conclude that a reduction of the base resistance from the measured value of 2.9 k12 to a value comparable with the 700 fl measured

P.L.F. Hemment et aL /Journal of Crystal Growth 157 (1995) 147-160

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depth pm Fig. 11. (a) Simulated dopant depth profiles beneath the emitter of a SiGe beterojunction bipolar transistor [34]. (b) Simulated profiles used by GraJm et al. [34] to determine the sensitivity of the electrical characteristics of a SiGc hetcrojuncUon bipolar transistor to the Ge depth profile [34].

on the control Si BJTs must be achieved either by increased boron doping or more complete defect annihilation. A device simulator has been employed by Grahn et al. [34] to investigate the dependence of the electrical characteristics of a SiGe HBT upon the shape of the Ge concentration depth profile, in particular regarding the penetration of the Ge into the collector. The doping profiles beneath the emitter are shown in Fig. 1 la whilst the investigated Ge profiles, which were described by a double Gaussian, are shown in Fig. 11 b. The computed collector currents were found to be sensitive to the profile shape and in the SiGe HBTs were almost one order of magnitude higher for profiles (iii) and (iv) (Fig. 11 a) than in the reference Si BJTs. The authors concluded that for a high current gain the peak of the Ge distribution must be

157

remote from the emitter-base (e-b) junction but can be close to the b - c junction. The deep penetration of the Ge implantation tail did not appear to degrade the gain. Lombardo et al. [9] have fabricated p+-n diodes where the p+ region is Si~_xGe x or Si]_x yGexC formed by implantation of 70 keV Ge ÷ (-3 x 101~ cm -2) and 30 keV C + (3×1015 or 1.5X1015 cm -2) with a subsequent anneal at ll00°C for ten seconds (see Section 2.3). The C profile was centred at the c / a interface in order to inhibit formation of EOR defects (see Fig. 8c). Both reference Si and Si]_~Ge x diodes exhibited ideal I - V characteristics (ideality factor of 1.0). Leakage associated with EOR defects was not evident as the junction was located deeper than the defects. In contrast the diodes implanted with 3 × 1015 C + cm -2 showed high leakage currents whilst those implanted with 1.5 X 1015 C + cm -2, which was sufficient to suppress the formation of EOR defects, had I - V characteristics similar to those of the Sil_xGe~ diodes. The authors concluded that with careful process optimisation it will be possible to use C ÷ implantation to suppress defect formation without significant degradation of the electrical characteristics. In a related study by Zhang et al. [35] of the electrically active defects in regrown amorphous Si layers formed by 400 keV Ge + implantation it was noted that after SPEG at 750°C, a high concentration of excess donors existed in the vicinity of the EOR defects. The concentration of these donors was greatly reduced by a subsequent ten minute anneal at 850°C. It must be concluded that synthesis of SiGe/Si heterostructures may require a two stage anneal, namely SPEG at a low temperature ( < 600°C) to inhibit dislocation motion [17] followed by a high temperature anneal to achieve full dopant electrical activity. 4.2. MOS devices

The successful fabrication of SiGe n-channel MOSFETs using Ge ÷ implantation and SPEG was reported by Selvakumar and Hecht in 1991 [36]. The electrical characteristics of these devices, whose design was not optimised, were significantly better than those of Si control devices fabricated on the same chip. The Ge ÷ implantation step was slotted into an

158

P.L.F. Hemment et al./Journal of Crystal Growth 157 (1995) 147-160

established self-aligned Si MOSFET process and doses of 6 X 1016 Ge + cm -2 at 80 keV were implanted into cooled wafers (liquid N 2) through windows opened in photoresist alongside the Si control devices. The computed peak Ge content was 16 at%. A gate oxide of thickness 100 nm was grown at 1100°C in dry oxygen. Fig. 12a is a schematic of the processing steps for the SiGe and Si devices. Fig. 12b shows the output characteristics of the devices with drain currents substantially improved in the SiGe devices compared to the Si MOSFETs. The

authors assumed that channel lengths and gate oxide thickness were the same in both the SiGe and Si structures and concluded that the SiGe devices have a higher surface channel mobility, transconductance and drain conductance. In the absence of other physical analyses the defect distribution was unknown, however, as the implanted Ge is above the critical dose [17], it is assumed that the layers are relaxed. As these are majority carder devices we speculate that the improved performance reflects the insensitivity of these devices to extended defects.

4.3. Other applications a)

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The ability to synthesise deep (1 /zm), broad SiGe layers with graded interfaces has relevance to a number of applications. For example, compositionally graded relaxed buffer layers, with a Ge profile illustrated in Fig. lb, might be used as "virtual" substrates [37] for subsequent growth of thin strained Si layers, with improved transport properties, for p-channel MOSFETs [38]. Waveguides will be one of the building blocks for future Si based photonic circuits and SiGe guides [39], where the refractive index is controlled by the composition and strain, are attractive because of the compatibility with Si VLSI and potential to support optical emission [40]. Experiments show that low loss MBE SiGe rib waveguides can be formed [41] and calculations by Soref [24] suggest that 2 at% Ge in Si will produce a 0.3% change in the refractive index. Both of these values are compatible with current technological developments. Preliminary computer modelling [42] suggests that graded guides formed by high, multienergy Ge ÷ implantation to a dose in the range 1016-1017 cm -2 will exhibit adequate confinement to make them viable for " o n chip" optical circuits at wavelengths of 1.3-1.5 /xm. Fig. 13 shows computed Ge ÷, In +, P+ and As ÷ concentration depth profiles [2] which serve to show that doped SiGe heterostructures can be formed that are potentially suitable for HBT device (Section 4.1) fabrication and evaluation. Fig. 14 shows a schematic of a sidewall base contact structure (SICOS) [43] which not only optimises the HBT characteristics but also might provide a viable architecture for devices fabricated on synthesised SiGe layers. Here the dielectric and poly-Si layers associated with

P.L.F. Hemment et al. / Journal of Crystal Growth 157 (1995) 147-160

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fronts of the implanted amorphous layers during SPEG.

5. Conclusions Some pertinent aspects of the science, technology and applications of SiGe heterostructures formed by Ge implantation have been reviewed. It is found that strained SiGe alloy layers with graded interfaces and with a peak Ge content (say < 10 at%) can be formed by ion implantation plus SPEG. The critical Ge dose can be predicted and layers containing a lower peak concentration, which are subsequently amorphised, can be regrown thermally at temperatures between 500 and 600°C. Excess donors may

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P.L.F. Hemment et aL /Journal of Crystal Growth 157 (1995) 147-160

remain but can be annihilated by a 850°C anneal. Thick relaxed layers can readily be synthesised and the incorporation of C ÷ can compensate the strain and annihilate defects. Electrical measurements show that excess C can have detrimental effects upon the device characteristics. It is shown that device worthy Ge and dopant profiles can be realised and that particular device architectures appear to be compatible with this method of synthesising SiGe heterostructures. The technology warrants further investigation.

Acknowledgements This paper is presented under the auspices of the EU Human Capital and Mobility Network " I B O S " (CT93-0125).

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