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Gettering processes for defect control
896
World Abstracts on Microelectronics and Reliability
The technology employed today seems to provide suitable reliability for T T L Low-Power Schottky devices,
dependent, which if not taken into account, results in erroneous reliability projections.
Migration of silver from silver-loaded polyimide adhesive chip bonds at high temperatures. ROGER J. CHAFFIN. IEEE Trans. Components, Hybrids, Mfi3 Teclmol. Chmt-4, (2) p. 214 (June
Reliability of D H Gal_~AI,As LEDs for lightwave communications. C. L. ZIPEEL, A. K. CHIN, V. G. KERAMIDASand R. H. SAUL. IEEE/Proc. IRPS 124 (1981). Double heterostructure Ga~_xAlxAs LEDs operated at high current densities (3 x 103 A/cm 2) are being used as sources in lightwave communication systems, for example in optical data links. This paper discusses the reliability of these devices, distinguishing between catastrophic degradation due to Dark Line Defect (DLD) formation and gradual aging mechanisms. Two modes of D L D formation are observed: ( 1) A certain percentage of devices fail in relatively short times by D L D formation at threading dislocations. The growth of these D L D s is strongly current dependent, but independent of temperature. A 100h, 100mA burn-in eliminates all of the devices which fail by this mode. Burn-in failures can be kept as Iow as 5%. (2) Under accelerated aging as many as 257"o of the devices which passed the burn-in fail after 103h by a new mode of D L D formation. This mode is temperature dependent and related to stress at the dielectric-metal interface. Analysis shows that a 25 ",~ freak population gives ~<40 FITS at 70°C. Accelerated aging studies of clear devices are complicated by two competing processes: a slow degradation in light output and a slow increase which dominates at high temperatures. Activation energies for the two processes are 0.65 and 0.75 eV, respectively. Projected values of M T T F are 9 x 107h at 25°C and 4 × 106h at 70°C.
1981 ). A degradation mechanism found at high temperatures in a commercial silver-loaded polyimide chip adhesive is discussed. The adhesive was used to attach semiconductor diodes to headers for potential use in the geothermal well probe program. Aging the mounted devices at 300°C for 1100h resulted in a bias dependent migration of the silver out of the adhesive. This effect was accompanied by an increased series resistance and weakened bond strength.
Gettering processes for defect control. JOSEPH R. MONKOWSKL Solid-State Technology 44 (July 1981 ). As a result of the need for very low defect and contamination levels in today's silicon, many different types of gettering techniques have been established. These gettering techniques include backsurface damage, intrinsic gettering, chlorine-oxidation, diffusion, and annealing. In this article the techniques are explained, and some of the literature dealing with each technique is reviewed. In addition, an account is given of the most deleterious defects and their effects on device performance. S E M / E D A X analysis of pind test failures. J. F. DAL PORTO, D. H. LOESCHER, H. C. OLSON and P. V. PLUNKETT. IEEE/ Proc. IRPS 163 (1981). Packaged LSI and hybrid devices used in high reliability military and space applications must pass a rigorous series of screens defined by Method 5004 of Mil Standard 883B. One of these screens is the Particle Impact Noise Detection (PIND) test. This test uses a very sensitive acoustic transducer to listen for particles within the package while the package is vibrated and shocked. We have used SEM, EDAX, and optical microscopy to analyze the particles from P I N D failures. From these analyses we have identified the primary sources of P I N D failures and have developed procedures that yield a low reject rate at P1ND test. The device used in this investigation was a 1 K RAM die eutectically attached to a 24-pin leadless hermetic package (LHP). The package is solder sealed in a belt furnace with a gold-tin eutectic preform and a gold-plated cover. We have recovered the particles from P I N D test failures by placing lead tape over a punched hole in the gold plated Kovar lid. The package is then vibrated until the particles pass through the hole and are attached to the adhesive on the tape. From the analyses we have identified many sources of particles that cause P I N D test failures; the main source being the gold-tin solder preform used in the sealing process. We have investigated the effect of sealing materials, furnace temperature, furnace ambient, and package orientation on the number of gold-tin solder spheres. The best results were obtained with a nonoxidizing furnace ambient with the packages placed lid down and angled at 45 degrees during sealing. These improved assembly processes have led to P I N D test yields of better than 90 percent.
How parts fail. EDGAR A. DOYLE, JR. IEEE Spectrum 36 (October 1981). A fundamental explanation for any part failure exists, and it's up to the failure analyst to find the cause with modern sleuthing.
Temperature dependent defect level for an ionic failure mechanism. RICHARD S. HEMMERT. IEEE/Proc. IRPS 172 (1981). O n N-channel M O S F E T devices, phosphosilicate glass maintains threshold stability by gettering ionic (sodium) contaminants, typically to 250°C. However, defects can affect the phosphosilicate glass and substantially reduce its gettering ability. The defect level then becomes temperature
Electrostatic discharge failures of semiconductor devices. B. A. UNGER. IEEE/Proc. IRPS 193 (1981). ESD (Electrostatic Discharge) is a significant cause of device failures at all stages of device and equipment production, assembly, test, installation and field use. Even though device designs include protection circuitry, it is relatively easy to generate static potentials during handling and shipping that exceed the limits of the protection networks. D a m a g e from ESDs can cause either complete device failure by parametric shifts, or device weakness by locally heating, melting, or otherwise damaging oxides, junctions or device components. There are three principal sources of charge which can give rise to damaging ESD events. 1. A charged person touches a device and discharges the stored charge to or through the device to ground. 2. The device itself acting as one plate of a capacitor can store charge. Upon contact with an effective ground the discharge pulse can create damage. 3. An electrostatic field is always associated with charged objects. Under particular circumstances, a device inserted in this field can have a potential induced across an oxide that creates breakdown. All devices and technologies are susceptible to damaging ESDs. The difference is in their degree of susceptibility. MOS structures appear to be the most susceptible to ESD damage. The generation of charge varies with materials, environment, and conditions of contact. All materials can be charged, however with conductors the charge is readily dissipated by grounding. With insulators, the charge is immobile and not readily dissipated. Two basic measures for avoiding ESD damage and failures are: 1. Always wear a grounding strap when handling electronic components, 2. For transport, storage or assembly, a static-free environment must be created by selection of materials, shielding and proper grounding.
Reliability study of plastic encapsulated copper lead frame/ epoxy die attach packaging system. J. R. HOWELL. IEEE/Proc. IRPS 104 (1981). This paper presents the evaluation methods used to appraise the reliability of plastic/copper lead frame
World Abstracts on Microelectronics and Reliability
The technology employed today seems to provide suitable reliability for T T L Low-Power Schottky devices,
dependent, which if not taken into account, results in erroneous reliability projections.
Migration of silver from silver-loaded polyimide adhesive chip bonds at high temperatures. ROGER J. CHAFFIN. IEEE Trans. Components, Hybrids, Mfi3 Teclmol. Chmt-4, (2) p. 214 (June
Reliability of D H Gal_~AI,As LEDs for lightwave communications. C. L. ZIPEEL, A. K. CHIN, V. G. KERAMIDASand R. H. SAUL. IEEE/Proc. IRPS 124 (1981). Double heterostructure Ga~_xAlxAs LEDs operated at high current densities (3 x 103 A/cm 2) are being used as sources in lightwave communication systems, for example in optical data links. This paper discusses the reliability of these devices, distinguishing between catastrophic degradation due to Dark Line Defect (DLD) formation and gradual aging mechanisms. Two modes of D L D formation are observed: ( 1) A certain percentage of devices fail in relatively short times by D L D formation at threading dislocations. The growth of these D L D s is strongly current dependent, but independent of temperature. A 100h, 100mA burn-in eliminates all of the devices which fail by this mode. Burn-in failures can be kept as Iow as 5%. (2) Under accelerated aging as many as 257"o of the devices which passed the burn-in fail after 103h by a new mode of D L D formation. This mode is temperature dependent and related to stress at the dielectric-metal interface. Analysis shows that a 25 ",~ freak population gives ~<40 FITS at 70°C. Accelerated aging studies of clear devices are complicated by two competing processes: a slow degradation in light output and a slow increase which dominates at high temperatures. Activation energies for the two processes are 0.65 and 0.75 eV, respectively. Projected values of M T T F are 9 x 107h at 25°C and 4 × 106h at 70°C.
1981 ). A degradation mechanism found at high temperatures in a commercial silver-loaded polyimide chip adhesive is discussed. The adhesive was used to attach semiconductor diodes to headers for potential use in the geothermal well probe program. Aging the mounted devices at 300°C for 1100h resulted in a bias dependent migration of the silver out of the adhesive. This effect was accompanied by an increased series resistance and weakened bond strength.
Gettering processes for defect control. JOSEPH R. MONKOWSKL Solid-State Technology 44 (July 1981 ). As a result of the need for very low defect and contamination levels in today's silicon, many different types of gettering techniques have been established. These gettering techniques include backsurface damage, intrinsic gettering, chlorine-oxidation, diffusion, and annealing. In this article the techniques are explained, and some of the literature dealing with each technique is reviewed. In addition, an account is given of the most deleterious defects and their effects on device performance. S E M / E D A X analysis of pind test failures. J. F. DAL PORTO, D. H. LOESCHER, H. C. OLSON and P. V. PLUNKETT. IEEE/ Proc. IRPS 163 (1981). Packaged LSI and hybrid devices used in high reliability military and space applications must pass a rigorous series of screens defined by Method 5004 of Mil Standard 883B. One of these screens is the Particle Impact Noise Detection (PIND) test. This test uses a very sensitive acoustic transducer to listen for particles within the package while the package is vibrated and shocked. We have used SEM, EDAX, and optical microscopy to analyze the particles from P I N D failures. From these analyses we have identified the primary sources of P I N D failures and have developed procedures that yield a low reject rate at P1ND test. The device used in this investigation was a 1 K RAM die eutectically attached to a 24-pin leadless hermetic package (LHP). The package is solder sealed in a belt furnace with a gold-tin eutectic preform and a gold-plated cover. We have recovered the particles from P I N D test failures by placing lead tape over a punched hole in the gold plated Kovar lid. The package is then vibrated until the particles pass through the hole and are attached to the adhesive on the tape. From the analyses we have identified many sources of particles that cause P I N D test failures; the main source being the gold-tin solder preform used in the sealing process. We have investigated the effect of sealing materials, furnace temperature, furnace ambient, and package orientation on the number of gold-tin solder spheres. The best results were obtained with a nonoxidizing furnace ambient with the packages placed lid down and angled at 45 degrees during sealing. These improved assembly processes have led to P I N D test yields of better than 90 percent.
How parts fail. EDGAR A. DOYLE, JR. IEEE Spectrum 36 (October 1981). A fundamental explanation for any part failure exists, and it's up to the failure analyst to find the cause with modern sleuthing.
Temperature dependent defect level for an ionic failure mechanism. RICHARD S. HEMMERT. IEEE/Proc. IRPS 172 (1981). O n N-channel M O S F E T devices, phosphosilicate glass maintains threshold stability by gettering ionic (sodium) contaminants, typically to 250°C. However, defects can affect the phosphosilicate glass and substantially reduce its gettering ability. The defect level then becomes temperature
Electrostatic discharge failures of semiconductor devices. B. A. UNGER. IEEE/Proc. IRPS 193 (1981). ESD (Electrostatic Discharge) is a significant cause of device failures at all stages of device and equipment production, assembly, test, installation and field use. Even though device designs include protection circuitry, it is relatively easy to generate static potentials during handling and shipping that exceed the limits of the protection networks. D a m a g e from ESDs can cause either complete device failure by parametric shifts, or device weakness by locally heating, melting, or otherwise damaging oxides, junctions or device components. There are three principal sources of charge which can give rise to damaging ESD events. 1. A charged person touches a device and discharges the stored charge to or through the device to ground. 2. The device itself acting as one plate of a capacitor can store charge. Upon contact with an effective ground the discharge pulse can create damage. 3. An electrostatic field is always associated with charged objects. Under particular circumstances, a device inserted in this field can have a potential induced across an oxide that creates breakdown. All devices and technologies are susceptible to damaging ESDs. The difference is in their degree of susceptibility. MOS structures appear to be the most susceptible to ESD damage. The generation of charge varies with materials, environment, and conditions of contact. All materials can be charged, however with conductors the charge is readily dissipated by grounding. With insulators, the charge is immobile and not readily dissipated. Two basic measures for avoiding ESD damage and failures are: 1. Always wear a grounding strap when handling electronic components, 2. For transport, storage or assembly, a static-free environment must be created by selection of materials, shielding and proper grounding.
Reliability study of plastic encapsulated copper lead frame/ epoxy die attach packaging system. J. R. HOWELL. IEEE/Proc. IRPS 104 (1981). This paper presents the evaluation methods used to appraise the reliability of plastic/copper lead frame