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Growth of silicon carbide epitaxial layers on 150-mm-diameter wafers using a horizontal hot-wall chemical vapor deposition
Journal of Crystal Growth 381 (2013) 139–143
Contents lists available at ScienceDirect
Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Growth of silicon carbide epitaxial layers on 150-mm-diameter wafers using a horizontal hot-wall chemical vapor deposition Keiko Masumoto a,b,n, Chiaki Kudou a,c, Kentaro Tamura a,d, Johji Nishio a,e, Sachiko Ito a,b, Kazutoshi Kojima a,b, Toshiyuki Ohno a,f, Hajime Okumura a,b a
R & D Partnership for Future Power Electronics Technology, 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan National Institute of Advanced Industrial Science and Technology, Central 2 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan c Panasonic Corporation, 700 Tomonobu, Bizen-City, Okayama 705-8585, Japan d ROHM Co., Ltd., 21 Saiin Mizosaki-Cho, Ukyo, Kyoto 615-8585, Japan e Toshiba Corporation, 1 Komukai-Toshiba-cho, Saiwai, Kawasaki, Kanagawa 212-8582, Japan f Hitachi, Ltd., 1-280 Higashi-Koigakubo, Kokubunji-Shi, Tokyo 185-8601, Japan b
art ic l e i nf o
a b s t r a c t
Article history: Received 19 June 2013 Received in revised form 10 July 2013 Accepted 19 July 2013 Communicated by K.W. Benz Available online 27 July 2013
Epitaxial layers on a 150-mm-diameter silicon carbide wafer have been grown using a horizontal hotwall chemical vapor deposition system for three 150-mm-diameter wafers. We investigated the surface morphology and surface defects such as shallow pits and triangular defects of the grown epitaxial layers, as well as the thickness and carrier concentration uniformities. The shallow pit and triangular defect densities were 4.6 cm 2 and 1.6 cm 2, respectively, and the thickness and the carrier concentration uniformities were 3.9% and 47%, respectively. We focused on improving the carrier concentration distribution for practical use and concluded that the cause of the distribution was the distribution in the effective C/Si ratio in the direction of the gas flow. & 2013 Elsevier B.V. All rights reserved.
Keywords: A1. Crystal morphology A3. Chemical vapor deposition processes B1. Inorganic compounds B2. Semiconducting silicon compounds
1. Introduction Power devices are used to control various high-voltage components such as power supplies and motors so that electricity can be used efficiently. Silicon carbide (SiC) possesses certain physical properties such as a wide bandgap and high thermal conductivity that allows high-temperature operation and miniaturization of power devices, which in turn expands the range of use such power devices and creates space for other functional systems. Therefore, it is expected that SiC power devices are often used for applications such as automotive and railway electronics. SiC power devices such as Schottky barrier diodes and metal-oxide-semiconductor field-effect transistors (MOSFETs) are commercially available. However, because these devices are more expensive than common Si-based devices, it is necessary to reduce the cost of chips to further expand their use. The mainstream SiC wafer sizes are 75 and 100 mm diameter, but larger wafers will result in a reduction of the chip cost because a larger number of chips per wafer area can be fabricated. Indeed, Si wafer sizes have been enlarged to improve the productivity, and n Corresponding author at: National Institute of Advanced Industrial Science and Technology, Central 2 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan. Tel.: +81 29 861 4165; fax: +81 29 861 5434. E-mail address: [email protected] (K. Masumoto).
0022-0248/$ - see front matter & 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.jcrysgro.2013.07.025
wafers with diameters of up to 200 mm are already used for power devices. SiC wafers with a 150-mm diameter should be used from now on because such wafers are becoming standard materials in the industry. Some vendors have already released 150-mm-diameter SiC bulk wafers [1], and growth of SiC epitaxial layers on such wafers has been reported [1,2]. Burk et al. first reported SiC epitaxial layer growth on 150-mm-diameter wafers using a planetary chemical vapor deposition (CVD) system in 2012 [1]. They achieved a total defect density of 4.4 cm 2 and thickness and carrier concentration uniformities of 1.6% and 12.8%, respectively. Miyasaka et al. also reported SiC epitaxial layer growth on 150-mm-diameter wafers using a planetary CVD system, but the carrier concentration uniformity was of an undesirable level [2]. To obtain SiC epitaxial layers on 150-mm-diameter with a suitably high quality, conditions relating to the defect density and carrier concentration uniformity have not yet been satisfied. The surface morphology, shallow pits, and triangular defects of SiC layers should be investigated because they have an adverse influence on the performance of SiC-based devices [3–8]. It has been reported that a rough surface and shallow pits, which originate from threading screw dislocations, degrade the reliability of gate oxides [3,6,7]. Moreover, triangular defects have been reported to be one of the main causes of short MOS capacitor
140
K. Masumoto et al. / Journal of Crystal Growth 381 (2013) 139–143
lifetimes [8]. In addition, there are no reports on shallow pits that consider the whole wafer because it is difficult for conventional optical surface analyzers to detect shallow pits. The thickness and carrier concentration uniformities of the epitaxial layers are also important because they have a significant effect on device yields. In general, the type of growth system affects the uniformities, and therefore, the uniformities obtained with each growth system need to be investigated. We have previously grown SiC epitaxial layers with a size equivalent to 150 mm by arranging two wafers with 75-mm diameters and using a horizontal hot-wall CVD system for three 150-mm-diameter wafers, Tokyo Electron Probus-SiC [9]. We focused on the surface morphology and surface defects such as shallow pits and triangular defects of these layers and found that the C/Si ratio is an important growth parameter for improving the surface morphology and reducing the surface defect density. In this study, we grew an epitaxial layer on a 150-mm-diameter wafer using the horizontal hot-wall CVD system and investigated the surface morphology, surface defect density, and thickness and carrier concentration uniformities. To do this, we first grew epitaxial layers with an equivalent 150-mm-diameter size to optimize the growth conditions for a smooth surface and few surface defects over the whole wafer. We discuss here the origins of the carrier concentration distribution and way to improve the uniformity.
2. Experimental procedure Epitaxial growth was performed using a horizontal hot-wall CVD system, Tokyo Electron Probus-SiC. Fig. 1(a) and (b) show schematic drawings of the CVD reactor from parallel and perpendicular to gas flow directions, respectively. The fixed susceptor, which is heated by a high-frequency induction heating system, and rotary susceptor are made of graphite. A wafer holder for three 150-mm-diameter wafers is placed on the rotary susceptor during growth. A schematic drawing of the wafer holder is shown in Fig. 1(c). Open circles and dashed circles show the wafer pockets with 150 mm diameter and 75 mm diameter, respectively. The offangle direction is the same as the rotation tangential direction when wafers are put on the wafer holder as shown in this figure. Two wafers with diameters of 75 mm are arranged in the radial direction of the wafer holder to grow layers with an equivalent 150-mm-diameter size. Conventional n-type 4H-SiC Si-face wafers with a 41 off-angle toward the [11–18] direction were used as substrates after chemical-mechanical polishing treatment. In-situ H2 etching was carried out at 1605 1C and 12 kPa. The H2 flow rate was 150 slm, and the etched depth was about 55 nm. Epitaxial layers were grown for 1 h. The growth temperature was varied between 1580 and 1680 1C, and the growth pressure was varied between 6.3 and 12 kPa. N2 as a doping gas was injected at a rate of 5 sccm. The H2 and C3H8 (10% in H2) flow rates were 100 slm and 170 230 sccm,
respectively. The C/Si ratio was changed from 1.0 to 1.8 by varying the flow rate of SiH4 (10% in H2). The growth rate was about 5.5 μm/h. The thickness and carrier concentration were investigated by using conventional Fourier transform-infrared spectroscopy and mercury probe capacitance–voltage measurements, respectively. The surface morphology and surface defects were inspected by using a confocal microscope with a differential interference contrast (CDIC) system, Lasertec SICA 61. The confocal microscope system efficiently obtains signals from the surface because out-offocus signals are rejected, and using the SICA therefore enables shallow pits to be detected. Reflection loss was detected to investigate the surface morphology throughout the whole wafer and was estimated from the difference between the irradiated and reflected light intensities. Large reflection loss values mean that the reflected light intensity decreased due to a rough surface.
3. Results and discussion 3.1. Growth of SiC epitaxial layers with an equivalent 150-mm-diameter size We began by growing epitaxial layers with an equivalent 150-mm-diameter size to optimize the growth conditions for a 150-mm-diameter epitaxial layer. The surface morphology and densities of surface defects such as shallow pits and triangular defects were investigated across the whole wafer. Fig. 2 shows the dependence of the reflection loss on the C/Si ratio; the reflection loss was obtained from SICA measurements of the two 75-mm-diameter wafers. The reflection loss of a conventional epitaxial layer with an 81 off-angle, which has smooth
Fig. 2. Dependence of the reflection loss on the C/Si ratio. (Inset: CDIC image of the epitaxial layer grown at a C/Si ratio of 1.8.)
Fig. 1. Schematic drawing of the (a) CVD reactor and (b) wafer holder. The wafer pockets have diameters of 150 mm (solid lines) and 75 mm (dashed lines).
K. Masumoto et al. / Journal of Crystal Growth 381 (2013) 139–143
surface without step bunching, is also shown for comparison. Low values of the reflection loss mean that the surface is smooth, and this figure suggests that the surface morphology is improved by lowering the C/Si ratio. The reflection loss of the epitaxial layer grown at a C/Si ratio of 1.0 is almost the same as that of the conventional epitaxial layer, which indicates that the epitaxial layer has smooth surface with little step bunching. A CDIC image of the epitaxial layer grown at a C/Si ratio of 1.8 is shown in the inset of Fig. 2. We found that the whole surface was rough owing to the generation of step bunching. It has been reported that step bunching is generated due to impurity effects originating from Si or C clusters that are formed on the terraces due to an excessive supply of SiH4 or C3H8 [10]. These clusters can act as obstacles to steps movement, and thus step bunching is generated. We believe that here step bunching was generated due to C clusters formed by supplying excess C3H8 in the case of growth at a C/Si ratio of 1.8 and lowering the C/Si ratio led to the suppression of step bunching due to a decrease in the number of C clusters. Fig. 3(a) and (b) shows dependence of the shallow pit and triangular defect densities, respectively, on the C/Si ratio. Both densities decrease with a lowering of the C/Si ratio, and at C/Si ratio of 1.0, the shallow pit and triangular defect densities decreased by a factor of one hundred and five, respectively, compared to those at C/Si ratio of 1.8. It has been reported that shallow pits are generated at dislocations in the substrate [5,11], and therefore, shallow pits were likely generated through growth inhibition attributed to dislocations. In addition, we believe that
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the triangular defects were generated due to the shallow pits owing to the fact that the shallow pits are present at the starting point of almost all triangular defects [9]. Therefore, when the C/Si ratio was lowered, which has been reported to enhance step-flow growth [12,13], growth inhibition was suppressed and the shallow pit and triangular defect densities decreased. From these results, we concluded that growth at a low C/Si ratio of 1.0 was effective for improving the surface morphology and reducing the surface defect density of the epitaxial layers with an equivalent 150-mm-diameter. 3.2. Growth of a SiC epitaxial layer on a 150 mm-diameter wafer As indicated in Section 3.1, growth at a low C/Si ratio of 1.0 was effective for improving the surface morphology and reducing the surface defect density of the epitaxial layers with equivalent 150mm-diameter. We investigated the surface morphology, surface defect density, and the thickness and carrier concentration uniformities of an epitaxial layer grown on a 150-mm-diameter wafer at a C/Si ratio of 1.0. We confirmed that the reflection loss across the whole wafer was the same as that of these epitaxial layers grown with an equivalent 150-mm-diameter size at a C/Si ratio of 1.0. It means that the surface morphology of 150-mm-diameter epitaxial layer was sufficiently smooth. Fig. 4(a) and (b) shows the shallow pit and triangular defect distribution, respectively, of the 150-mm-diameter epitaxial layer.
Fig. 3. Dependence of the (a) shallow pit and (b) triangular defect densities on the C/Si ratio.
Fig. 4. Distribution of the (a) shallow pits and (b) triangular defects of the 150-mm-diameter epitaxial layer.
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We found that there were only a few surface defects, and the shallow pit and triangular defect densities were estimated to be 4.6 cm 2 and 1.6 cm 2, respectively. These results are similar to those of the epitaxial layers with an equivalent 150-mm-diameter size grown at a C/Si ratio of 1.0. This confirms that the generation of surface defects is suppressed by growing at C/Si ratio of 1.0. Fig. 5(a) and (b) shows contour maps of the thickness and carrier concentration, respectively, of the 150-mm-diameter epitaxial layer. The sides closest to the center and edge of the wafer holder are indicated in the figure. We used 137 points to measure the thickness and 56 points to measure the carrier concentration. The contours are shown for intervals of 0.1 μm in the case of the thickness and 1 1016 cm 3 in the case of the carrier concentration. The uniformity (s/mean) of the thickness was 3.9%, which is suitable for practical use. The uniformity of the carrier concentration, however, was 47%, and there is a sharp increase on the side close to the edge of the wafer holder. The carrier concentration uniformity was worse than the 150-mm-diameter epitaxial layers grown using a planetary CVD system [1] and should be improved for practical use. It will be necessary to investigate the cause of this large carrier concentration distribution in order to improve the uniformity. From these results, we were able to confirm that the epitaxial layer grown on the 150-mm-diameter wafer at a C/Si ratio of 1.0 using the horizontal hot-wall CVD system had smooth surface and low surface defect densities across the whole wafer. The uniformity of the thickness was suitable for practical use, but we found that the carrier concentration uniformity should be improved.
distribution and confirmed the reasonability of the hypothesized cause by investigating the reflection loss and surface defect distributions. Fig. 6 shows the carrier concentration of the epitaxial layers grown without the rotation of the rotary susceptor. Two wafers each with 75-mm diameter were placed on the gas inlet and outlet sides toward the edge of the wafer holder. The off-angle direction was perpendicular to gas flow. A schematic drawing of wafer positions is shown in the inset of Fig. 6. The carrier concentration distribution on the gas inlet side drastically increases near the edge of the wafer holder, and this exponential increase was similar to the carrier concentration distribution of the 150-mm-diameter epitaxial layer as shown in Fig. 5(b). This indicates that the carrier concentration distribution of the epitaxial layers grown with rotation is due to high doping concentration on the gas inlet side. A possible cause of such a distribution is the difference in the effective C/Si ratio. It has been reported that the effective C/Si ratio on the gas inlet side is relatively low because SiH4 decomposes faster than C3H8 [14–16]. Moreover, it is well known that the carrier concentration increases with a lowering of the C/Si ratio,
3.3. Cause of the large carrier concentration distribution As we have shown, the carrier concentration of the 150-mmdiameter epitaxial layer had a large distribution. We discuss here the cause of this large distribution and how the uniformity can be improved. We carried out epitaxial growth without the rotation of the rotary susceptor to investigate cause of the carrier concentration
Fig. 6. Distribution of the carrier concentration in the direction of the gas flow. (Inset: Schematic drawing of the wafer positions in the case of growth without the rotation of the rotary susceptor.)
Fig. 5. Contour maps of the (a) thickness and (b) carrier concentration of the 150-mm-diameter epitaxial layer. The contour intervals of the thickness and carrier concentration are 0.1 μm and 1 1016 cm 3, respectively.
K. Masumoto et al. / Journal of Crystal Growth 381 (2013) 139–143
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Fig. 7. Distribution of the (a) reflection loss, (b) shallow pits, and (c) triangular defects generated on the epitaxial layers with an equivalent 150-mm-diameter size grown at a C/Si ratio of 1.8.
i.e., the site competition principle [17,18]. Therefore, the carrier concentration distribution of the epitaxial layer grown on the 150-mm-diameter wafer was presumably due to the distribution of the effective C/Si ratio in the direction of the gas flow on the gas inlet side. Moreover, it is thought that C3H8 decomposes enough on the gas outlet side because the carrier concentration distribution on the gas outlet side was largely unchanged. Fig. 7(a), (b), and (c) shows the reflection loss, shallow pit, and triangular defect distributions, respectively, of the epitaxial layers with an equivalent 150-mm-diameter size grown at a C/Si ratio of 1.8 with the rotation of the rotary susceptor. The sides closest to the center and edge of the wafer holder are indicated in the figure. Fig. 7(a) shows that the surface of the epitaxial layer grown near the center of the wafer holder is significantly rougher than that grown near the edge of the wafer holder, where linearly aligned step bunching was generated. It is thought that the generation of linearly aligned step bunching had nothing to do with growth conditions and was attributed to substrate surface defects. Fig. 7(b) and (c) suggests that the epitaxial layer grown near the center of the wafer holder has higher shallow pit and triangular defect distributions than that grown near the edge of the wafer holder. These distributions were due to the difference in the effective C/Si ratio because the other growth parameters have an insignificant effect on the surface morphology and surface defect density [9]. The surface morphology was improved and the surface defect density decreased by lowering the C/Si ratio, as shown in Figs. 2 and 3. Therefore, epitaxial layers are thought to be grown at relatively low C/Si ratio near the edge of the wafer holder because the epitaxial layer grown in this position had a relatively smooth surface and a low defects density. These results confirm that the hypothesized cause of the large carrier concentration distribution is reasonable. The distributions of the surface morphology and surface defect density were affected by the distribution of the effective C/Si ratio in the direction of the gas flow on the gas inlet side. We can conclude that the cause of the large carrier concentration distribution was the distribution of the effective C/Si ratio in the direction of the gas flow on the gas inlet side. It is expected that the carrier concentration uniformity is improved by decreasing the H2 flow rate, changing the precursors and so on which lead to the distribution reduction of the effective C/Si ratio. 4. Summary We have grown epitaxial layers on a 150-mm-diameter wafer using a horizontal hot-wall chemical vapor deposition system. The surface morphology, surface defect density, and thickness and
carrier concentration uniformities were investigated. We succeeded in growing a 150-mm-diameter epitaxial layer with a smooth surface and a low surface defect density. The shallow pit and triangular defect densities were 4.6 cm 2 and 1.6 cm 2, respectively, and the thickness and carrier concentration uniformities were 3.9% and 47%, respectively. We investigated the large carrier concentration distribution and concluded that the large distribution was due to the distribution of the effective C/Si ratio in the direction of the gas flow.
Acknowledgment This work is supported by Novel Semiconductor Power Electronics Project Realizing Low Carbon Emission Society under New Energy and Industrial Technology Development Organization (NEDO). References [1] A.A. Burk, D. Tsvetkov, D. Barnhardt, M.J. O'Loughlin, L. Garrett, P. Towner, J. Seaman, E. Deyneka, Y. Khlebnikov, J. Palmour, Materials Science Forum 717–720 (2012) 75. [2] A. Miyasaka, J. Norimatsu, K. Fukada, Y. Tajima, D. Muto, Y. Kimura, M. Odawara, T. Okano, K. Momose, Y. Osawa, H. Osawa, T. Sato, Materials Science Forum 740–742 (2013) 197. [3] J. Sameshima, O. Ishiyama, A. Shimozato, K. Tamura, H. Oshima, T. Yamashita, T. Tanaka, N. Sugiyama, H. Sako, J. Senzaki, H. Matsuhata, M. Kitabatake, Materials Science Forum 740–742 (2013) 745. [4] X. Ma, H. Chang, Q. Zhang, T. Sudarshan, Journal of Crystal Growth 279 (2005) 425. [5] A. Shrivastava, P. Muzykov, J.D. Caldwell, T.S. Sudarshan, Journal of Crystal Growth 310 (2008) 4443. [6] T. Hatakeyama, K. Ichinoseki, H. Yamaguchi, N. Sugiyama, H. Matsuhata, Materials Science Forum 717–720 (2012) 359. [7] T. Suzuki, H. Yamaguchi, T. Hatakeyama, H. Matsuhata, J. Senzaki, K. Fukuda, T. Shinohe, H. Okumura, Materials Science Forum 717–720 (2012) 789. [8] T. Hatakeyama, T. Suzuki, K. Ichinoseki, H. Matsuhata, K. Fukuda, T. Shinohe, K. Arai, Materials Science Forum 645–648 (2010) 799. [9] C. Kudou, K. Tamura, T. Aigo, W. Ito, J. Nishio, K. Kojima, T. Ohno, Materials Research Society Symposium Proceedings 1433, 2012, 6 pp, http://dx.doi.org/ 10.1557/opl.2012.1140 (mrss12-1433-h01-02). [10] Y. Ishida, T. Takahashi, H. Okumura, S. Yoshida, Materials Science Forum 600–603 (2009) 473. [11] Y.N. Picard, K.X. Liu, R.E. Stahlbush, M.E. Twigg, Journal of Electronic Materials 37 (2008) 655. [12] S. Nakamura, T. Kimoto, H. Matsunami, Japanese Journal of Applied Physics 42 (2003) L846. [13] S. Nakamura, T. Kimoto, H. Matsunami, Materials Science Forum 457–460 (2004) 163. [14] D.J. Larkin, P.G. Neudeck, J.A. Powell, L.G. Matus, Applied Physics Letters 65 (1994) 1659. [15] W. Chen, M.A. Capano, Journal of Applied Physics 98 (2005) 114907. [16] S. Nishizawa, M. Pons, Microelectronic Engineering 83 (2006) 100. [17] O. Danielsson, P. Sukkaew, M. Yazdanfar, O. Kordina, E. Janzen, Materials Science Forum 740–742 (2013) 213. [18] C.D. Stinespring, J.C. Wormhoudt, Journal of Crystal Growth 87 (1988) 481.
Contents lists available at ScienceDirect
Journal of Crystal Growth journal homepage: www.elsevier.com/locate/jcrysgro
Growth of silicon carbide epitaxial layers on 150-mm-diameter wafers using a horizontal hot-wall chemical vapor deposition Keiko Masumoto a,b,n, Chiaki Kudou a,c, Kentaro Tamura a,d, Johji Nishio a,e, Sachiko Ito a,b, Kazutoshi Kojima a,b, Toshiyuki Ohno a,f, Hajime Okumura a,b a
R & D Partnership for Future Power Electronics Technology, 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan National Institute of Advanced Industrial Science and Technology, Central 2 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan c Panasonic Corporation, 700 Tomonobu, Bizen-City, Okayama 705-8585, Japan d ROHM Co., Ltd., 21 Saiin Mizosaki-Cho, Ukyo, Kyoto 615-8585, Japan e Toshiba Corporation, 1 Komukai-Toshiba-cho, Saiwai, Kawasaki, Kanagawa 212-8582, Japan f Hitachi, Ltd., 1-280 Higashi-Koigakubo, Kokubunji-Shi, Tokyo 185-8601, Japan b
art ic l e i nf o
a b s t r a c t
Article history: Received 19 June 2013 Received in revised form 10 July 2013 Accepted 19 July 2013 Communicated by K.W. Benz Available online 27 July 2013
Epitaxial layers on a 150-mm-diameter silicon carbide wafer have been grown using a horizontal hotwall chemical vapor deposition system for three 150-mm-diameter wafers. We investigated the surface morphology and surface defects such as shallow pits and triangular defects of the grown epitaxial layers, as well as the thickness and carrier concentration uniformities. The shallow pit and triangular defect densities were 4.6 cm 2 and 1.6 cm 2, respectively, and the thickness and the carrier concentration uniformities were 3.9% and 47%, respectively. We focused on improving the carrier concentration distribution for practical use and concluded that the cause of the distribution was the distribution in the effective C/Si ratio in the direction of the gas flow. & 2013 Elsevier B.V. All rights reserved.
Keywords: A1. Crystal morphology A3. Chemical vapor deposition processes B1. Inorganic compounds B2. Semiconducting silicon compounds
1. Introduction Power devices are used to control various high-voltage components such as power supplies and motors so that electricity can be used efficiently. Silicon carbide (SiC) possesses certain physical properties such as a wide bandgap and high thermal conductivity that allows high-temperature operation and miniaturization of power devices, which in turn expands the range of use such power devices and creates space for other functional systems. Therefore, it is expected that SiC power devices are often used for applications such as automotive and railway electronics. SiC power devices such as Schottky barrier diodes and metal-oxide-semiconductor field-effect transistors (MOSFETs) are commercially available. However, because these devices are more expensive than common Si-based devices, it is necessary to reduce the cost of chips to further expand their use. The mainstream SiC wafer sizes are 75 and 100 mm diameter, but larger wafers will result in a reduction of the chip cost because a larger number of chips per wafer area can be fabricated. Indeed, Si wafer sizes have been enlarged to improve the productivity, and n Corresponding author at: National Institute of Advanced Industrial Science and Technology, Central 2 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan. Tel.: +81 29 861 4165; fax: +81 29 861 5434. E-mail address: [email protected] (K. Masumoto).
0022-0248/$ - see front matter & 2013 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.jcrysgro.2013.07.025
wafers with diameters of up to 200 mm are already used for power devices. SiC wafers with a 150-mm diameter should be used from now on because such wafers are becoming standard materials in the industry. Some vendors have already released 150-mm-diameter SiC bulk wafers [1], and growth of SiC epitaxial layers on such wafers has been reported [1,2]. Burk et al. first reported SiC epitaxial layer growth on 150-mm-diameter wafers using a planetary chemical vapor deposition (CVD) system in 2012 [1]. They achieved a total defect density of 4.4 cm 2 and thickness and carrier concentration uniformities of 1.6% and 12.8%, respectively. Miyasaka et al. also reported SiC epitaxial layer growth on 150-mm-diameter wafers using a planetary CVD system, but the carrier concentration uniformity was of an undesirable level [2]. To obtain SiC epitaxial layers on 150-mm-diameter with a suitably high quality, conditions relating to the defect density and carrier concentration uniformity have not yet been satisfied. The surface morphology, shallow pits, and triangular defects of SiC layers should be investigated because they have an adverse influence on the performance of SiC-based devices [3–8]. It has been reported that a rough surface and shallow pits, which originate from threading screw dislocations, degrade the reliability of gate oxides [3,6,7]. Moreover, triangular defects have been reported to be one of the main causes of short MOS capacitor
140
K. Masumoto et al. / Journal of Crystal Growth 381 (2013) 139–143
lifetimes [8]. In addition, there are no reports on shallow pits that consider the whole wafer because it is difficult for conventional optical surface analyzers to detect shallow pits. The thickness and carrier concentration uniformities of the epitaxial layers are also important because they have a significant effect on device yields. In general, the type of growth system affects the uniformities, and therefore, the uniformities obtained with each growth system need to be investigated. We have previously grown SiC epitaxial layers with a size equivalent to 150 mm by arranging two wafers with 75-mm diameters and using a horizontal hot-wall CVD system for three 150-mm-diameter wafers, Tokyo Electron Probus-SiC [9]. We focused on the surface morphology and surface defects such as shallow pits and triangular defects of these layers and found that the C/Si ratio is an important growth parameter for improving the surface morphology and reducing the surface defect density. In this study, we grew an epitaxial layer on a 150-mm-diameter wafer using the horizontal hot-wall CVD system and investigated the surface morphology, surface defect density, and thickness and carrier concentration uniformities. To do this, we first grew epitaxial layers with an equivalent 150-mm-diameter size to optimize the growth conditions for a smooth surface and few surface defects over the whole wafer. We discuss here the origins of the carrier concentration distribution and way to improve the uniformity.
2. Experimental procedure Epitaxial growth was performed using a horizontal hot-wall CVD system, Tokyo Electron Probus-SiC. Fig. 1(a) and (b) show schematic drawings of the CVD reactor from parallel and perpendicular to gas flow directions, respectively. The fixed susceptor, which is heated by a high-frequency induction heating system, and rotary susceptor are made of graphite. A wafer holder for three 150-mm-diameter wafers is placed on the rotary susceptor during growth. A schematic drawing of the wafer holder is shown in Fig. 1(c). Open circles and dashed circles show the wafer pockets with 150 mm diameter and 75 mm diameter, respectively. The offangle direction is the same as the rotation tangential direction when wafers are put on the wafer holder as shown in this figure. Two wafers with diameters of 75 mm are arranged in the radial direction of the wafer holder to grow layers with an equivalent 150-mm-diameter size. Conventional n-type 4H-SiC Si-face wafers with a 41 off-angle toward the [11–18] direction were used as substrates after chemical-mechanical polishing treatment. In-situ H2 etching was carried out at 1605 1C and 12 kPa. The H2 flow rate was 150 slm, and the etched depth was about 55 nm. Epitaxial layers were grown for 1 h. The growth temperature was varied between 1580 and 1680 1C, and the growth pressure was varied between 6.3 and 12 kPa. N2 as a doping gas was injected at a rate of 5 sccm. The H2 and C3H8 (10% in H2) flow rates were 100 slm and 170 230 sccm,
respectively. The C/Si ratio was changed from 1.0 to 1.8 by varying the flow rate of SiH4 (10% in H2). The growth rate was about 5.5 μm/h. The thickness and carrier concentration were investigated by using conventional Fourier transform-infrared spectroscopy and mercury probe capacitance–voltage measurements, respectively. The surface morphology and surface defects were inspected by using a confocal microscope with a differential interference contrast (CDIC) system, Lasertec SICA 61. The confocal microscope system efficiently obtains signals from the surface because out-offocus signals are rejected, and using the SICA therefore enables shallow pits to be detected. Reflection loss was detected to investigate the surface morphology throughout the whole wafer and was estimated from the difference between the irradiated and reflected light intensities. Large reflection loss values mean that the reflected light intensity decreased due to a rough surface.
3. Results and discussion 3.1. Growth of SiC epitaxial layers with an equivalent 150-mm-diameter size We began by growing epitaxial layers with an equivalent 150-mm-diameter size to optimize the growth conditions for a 150-mm-diameter epitaxial layer. The surface morphology and densities of surface defects such as shallow pits and triangular defects were investigated across the whole wafer. Fig. 2 shows the dependence of the reflection loss on the C/Si ratio; the reflection loss was obtained from SICA measurements of the two 75-mm-diameter wafers. The reflection loss of a conventional epitaxial layer with an 81 off-angle, which has smooth
Fig. 2. Dependence of the reflection loss on the C/Si ratio. (Inset: CDIC image of the epitaxial layer grown at a C/Si ratio of 1.8.)
Fig. 1. Schematic drawing of the (a) CVD reactor and (b) wafer holder. The wafer pockets have diameters of 150 mm (solid lines) and 75 mm (dashed lines).
K. Masumoto et al. / Journal of Crystal Growth 381 (2013) 139–143
surface without step bunching, is also shown for comparison. Low values of the reflection loss mean that the surface is smooth, and this figure suggests that the surface morphology is improved by lowering the C/Si ratio. The reflection loss of the epitaxial layer grown at a C/Si ratio of 1.0 is almost the same as that of the conventional epitaxial layer, which indicates that the epitaxial layer has smooth surface with little step bunching. A CDIC image of the epitaxial layer grown at a C/Si ratio of 1.8 is shown in the inset of Fig. 2. We found that the whole surface was rough owing to the generation of step bunching. It has been reported that step bunching is generated due to impurity effects originating from Si or C clusters that are formed on the terraces due to an excessive supply of SiH4 or C3H8 [10]. These clusters can act as obstacles to steps movement, and thus step bunching is generated. We believe that here step bunching was generated due to C clusters formed by supplying excess C3H8 in the case of growth at a C/Si ratio of 1.8 and lowering the C/Si ratio led to the suppression of step bunching due to a decrease in the number of C clusters. Fig. 3(a) and (b) shows dependence of the shallow pit and triangular defect densities, respectively, on the C/Si ratio. Both densities decrease with a lowering of the C/Si ratio, and at C/Si ratio of 1.0, the shallow pit and triangular defect densities decreased by a factor of one hundred and five, respectively, compared to those at C/Si ratio of 1.8. It has been reported that shallow pits are generated at dislocations in the substrate [5,11], and therefore, shallow pits were likely generated through growth inhibition attributed to dislocations. In addition, we believe that
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the triangular defects were generated due to the shallow pits owing to the fact that the shallow pits are present at the starting point of almost all triangular defects [9]. Therefore, when the C/Si ratio was lowered, which has been reported to enhance step-flow growth [12,13], growth inhibition was suppressed and the shallow pit and triangular defect densities decreased. From these results, we concluded that growth at a low C/Si ratio of 1.0 was effective for improving the surface morphology and reducing the surface defect density of the epitaxial layers with an equivalent 150-mm-diameter. 3.2. Growth of a SiC epitaxial layer on a 150 mm-diameter wafer As indicated in Section 3.1, growth at a low C/Si ratio of 1.0 was effective for improving the surface morphology and reducing the surface defect density of the epitaxial layers with equivalent 150mm-diameter. We investigated the surface morphology, surface defect density, and the thickness and carrier concentration uniformities of an epitaxial layer grown on a 150-mm-diameter wafer at a C/Si ratio of 1.0. We confirmed that the reflection loss across the whole wafer was the same as that of these epitaxial layers grown with an equivalent 150-mm-diameter size at a C/Si ratio of 1.0. It means that the surface morphology of 150-mm-diameter epitaxial layer was sufficiently smooth. Fig. 4(a) and (b) shows the shallow pit and triangular defect distribution, respectively, of the 150-mm-diameter epitaxial layer.
Fig. 3. Dependence of the (a) shallow pit and (b) triangular defect densities on the C/Si ratio.
Fig. 4. Distribution of the (a) shallow pits and (b) triangular defects of the 150-mm-diameter epitaxial layer.
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We found that there were only a few surface defects, and the shallow pit and triangular defect densities were estimated to be 4.6 cm 2 and 1.6 cm 2, respectively. These results are similar to those of the epitaxial layers with an equivalent 150-mm-diameter size grown at a C/Si ratio of 1.0. This confirms that the generation of surface defects is suppressed by growing at C/Si ratio of 1.0. Fig. 5(a) and (b) shows contour maps of the thickness and carrier concentration, respectively, of the 150-mm-diameter epitaxial layer. The sides closest to the center and edge of the wafer holder are indicated in the figure. We used 137 points to measure the thickness and 56 points to measure the carrier concentration. The contours are shown for intervals of 0.1 μm in the case of the thickness and 1 1016 cm 3 in the case of the carrier concentration. The uniformity (s/mean) of the thickness was 3.9%, which is suitable for practical use. The uniformity of the carrier concentration, however, was 47%, and there is a sharp increase on the side close to the edge of the wafer holder. The carrier concentration uniformity was worse than the 150-mm-diameter epitaxial layers grown using a planetary CVD system [1] and should be improved for practical use. It will be necessary to investigate the cause of this large carrier concentration distribution in order to improve the uniformity. From these results, we were able to confirm that the epitaxial layer grown on the 150-mm-diameter wafer at a C/Si ratio of 1.0 using the horizontal hot-wall CVD system had smooth surface and low surface defect densities across the whole wafer. The uniformity of the thickness was suitable for practical use, but we found that the carrier concentration uniformity should be improved.
distribution and confirmed the reasonability of the hypothesized cause by investigating the reflection loss and surface defect distributions. Fig. 6 shows the carrier concentration of the epitaxial layers grown without the rotation of the rotary susceptor. Two wafers each with 75-mm diameter were placed on the gas inlet and outlet sides toward the edge of the wafer holder. The off-angle direction was perpendicular to gas flow. A schematic drawing of wafer positions is shown in the inset of Fig. 6. The carrier concentration distribution on the gas inlet side drastically increases near the edge of the wafer holder, and this exponential increase was similar to the carrier concentration distribution of the 150-mm-diameter epitaxial layer as shown in Fig. 5(b). This indicates that the carrier concentration distribution of the epitaxial layers grown with rotation is due to high doping concentration on the gas inlet side. A possible cause of such a distribution is the difference in the effective C/Si ratio. It has been reported that the effective C/Si ratio on the gas inlet side is relatively low because SiH4 decomposes faster than C3H8 [14–16]. Moreover, it is well known that the carrier concentration increases with a lowering of the C/Si ratio,
3.3. Cause of the large carrier concentration distribution As we have shown, the carrier concentration of the 150-mmdiameter epitaxial layer had a large distribution. We discuss here the cause of this large distribution and how the uniformity can be improved. We carried out epitaxial growth without the rotation of the rotary susceptor to investigate cause of the carrier concentration
Fig. 6. Distribution of the carrier concentration in the direction of the gas flow. (Inset: Schematic drawing of the wafer positions in the case of growth without the rotation of the rotary susceptor.)
Fig. 5. Contour maps of the (a) thickness and (b) carrier concentration of the 150-mm-diameter epitaxial layer. The contour intervals of the thickness and carrier concentration are 0.1 μm and 1 1016 cm 3, respectively.
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Fig. 7. Distribution of the (a) reflection loss, (b) shallow pits, and (c) triangular defects generated on the epitaxial layers with an equivalent 150-mm-diameter size grown at a C/Si ratio of 1.8.
i.e., the site competition principle [17,18]. Therefore, the carrier concentration distribution of the epitaxial layer grown on the 150-mm-diameter wafer was presumably due to the distribution of the effective C/Si ratio in the direction of the gas flow on the gas inlet side. Moreover, it is thought that C3H8 decomposes enough on the gas outlet side because the carrier concentration distribution on the gas outlet side was largely unchanged. Fig. 7(a), (b), and (c) shows the reflection loss, shallow pit, and triangular defect distributions, respectively, of the epitaxial layers with an equivalent 150-mm-diameter size grown at a C/Si ratio of 1.8 with the rotation of the rotary susceptor. The sides closest to the center and edge of the wafer holder are indicated in the figure. Fig. 7(a) shows that the surface of the epitaxial layer grown near the center of the wafer holder is significantly rougher than that grown near the edge of the wafer holder, where linearly aligned step bunching was generated. It is thought that the generation of linearly aligned step bunching had nothing to do with growth conditions and was attributed to substrate surface defects. Fig. 7(b) and (c) suggests that the epitaxial layer grown near the center of the wafer holder has higher shallow pit and triangular defect distributions than that grown near the edge of the wafer holder. These distributions were due to the difference in the effective C/Si ratio because the other growth parameters have an insignificant effect on the surface morphology and surface defect density [9]. The surface morphology was improved and the surface defect density decreased by lowering the C/Si ratio, as shown in Figs. 2 and 3. Therefore, epitaxial layers are thought to be grown at relatively low C/Si ratio near the edge of the wafer holder because the epitaxial layer grown in this position had a relatively smooth surface and a low defects density. These results confirm that the hypothesized cause of the large carrier concentration distribution is reasonable. The distributions of the surface morphology and surface defect density were affected by the distribution of the effective C/Si ratio in the direction of the gas flow on the gas inlet side. We can conclude that the cause of the large carrier concentration distribution was the distribution of the effective C/Si ratio in the direction of the gas flow on the gas inlet side. It is expected that the carrier concentration uniformity is improved by decreasing the H2 flow rate, changing the precursors and so on which lead to the distribution reduction of the effective C/Si ratio. 4. Summary We have grown epitaxial layers on a 150-mm-diameter wafer using a horizontal hot-wall chemical vapor deposition system. The surface morphology, surface defect density, and thickness and
carrier concentration uniformities were investigated. We succeeded in growing a 150-mm-diameter epitaxial layer with a smooth surface and a low surface defect density. The shallow pit and triangular defect densities were 4.6 cm 2 and 1.6 cm 2, respectively, and the thickness and carrier concentration uniformities were 3.9% and 47%, respectively. We investigated the large carrier concentration distribution and concluded that the large distribution was due to the distribution of the effective C/Si ratio in the direction of the gas flow.
Acknowledgment This work is supported by Novel Semiconductor Power Electronics Project Realizing Low Carbon Emission Society under New Energy and Industrial Technology Development Organization (NEDO). References [1] A.A. Burk, D. Tsvetkov, D. Barnhardt, M.J. O'Loughlin, L. Garrett, P. Towner, J. Seaman, E. Deyneka, Y. Khlebnikov, J. Palmour, Materials Science Forum 717–720 (2012) 75. [2] A. Miyasaka, J. Norimatsu, K. Fukada, Y. Tajima, D. Muto, Y. Kimura, M. Odawara, T. Okano, K. Momose, Y. Osawa, H. Osawa, T. Sato, Materials Science Forum 740–742 (2013) 197. [3] J. Sameshima, O. Ishiyama, A. Shimozato, K. Tamura, H. Oshima, T. Yamashita, T. Tanaka, N. Sugiyama, H. Sako, J. Senzaki, H. Matsuhata, M. Kitabatake, Materials Science Forum 740–742 (2013) 745. [4] X. Ma, H. Chang, Q. Zhang, T. Sudarshan, Journal of Crystal Growth 279 (2005) 425. [5] A. Shrivastava, P. Muzykov, J.D. Caldwell, T.S. Sudarshan, Journal of Crystal Growth 310 (2008) 4443. [6] T. Hatakeyama, K. Ichinoseki, H. Yamaguchi, N. Sugiyama, H. Matsuhata, Materials Science Forum 717–720 (2012) 359. [7] T. Suzuki, H. Yamaguchi, T. Hatakeyama, H. Matsuhata, J. Senzaki, K. Fukuda, T. Shinohe, H. Okumura, Materials Science Forum 717–720 (2012) 789. [8] T. Hatakeyama, T. Suzuki, K. Ichinoseki, H. Matsuhata, K. Fukuda, T. Shinohe, K. Arai, Materials Science Forum 645–648 (2010) 799. [9] C. Kudou, K. Tamura, T. Aigo, W. Ito, J. Nishio, K. Kojima, T. Ohno, Materials Research Society Symposium Proceedings 1433, 2012, 6 pp, http://dx.doi.org/ 10.1557/opl.2012.1140 (mrss12-1433-h01-02). [10] Y. Ishida, T. Takahashi, H. Okumura, S. Yoshida, Materials Science Forum 600–603 (2009) 473. [11] Y.N. Picard, K.X. Liu, R.E. Stahlbush, M.E. Twigg, Journal of Electronic Materials 37 (2008) 655. [12] S. Nakamura, T. Kimoto, H. Matsunami, Japanese Journal of Applied Physics 42 (2003) L846. [13] S. Nakamura, T. Kimoto, H. Matsunami, Materials Science Forum 457–460 (2004) 163. [14] D.J. Larkin, P.G. Neudeck, J.A. Powell, L.G. Matus, Applied Physics Letters 65 (1994) 1659. [15] W. Chen, M.A. Capano, Journal of Applied Physics 98 (2005) 114907. [16] S. Nishizawa, M. Pons, Microelectronic Engineering 83 (2006) 100. [17] O. Danielsson, P. Sukkaew, M. Yazdanfar, O. Kordina, E. Janzen, Materials Science Forum 740–742 (2013) 213. [18] C.D. Stinespring, J.C. Wormhoudt, Journal of Crystal Growth 87 (1988) 481.