- Email: [email protected]
Guest Editorial: Special issue on low voltage low power integrated circuits and systems
Microelectronics Journal xxx (xxxx) xxx
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Editorial
Guest Editorial: Special issue on low voltage low power integrated circuits and systems A B S T R A C T
The development of low-voltage and low-power design techniques is observed since several decades, as system power constraints and advanced deeply-scaled CMOS technologies require lower and lower supply voltages. It is predicted that the supply voltage for high performance microprocessors will be decreased to 0.6 V in a near future. Even lower supply voltage may be requested for low-power systems, especially the ones applied in biomedical implantable or wearable electronic devices, autonomous sensor nodes supplied with non-conventional energy sources and other similar applications. The requested parameters of low-voltage and low-power systems are often difficult to achieve with the use of traditional design techniques. Therefore, the circuit and system designers are seeking to develop novel architectural solutions capable to operate with low supply voltage, while maintaining acceptable performances. The main goal of this special issue is on the research challenges relating to the theory, design and applications of low voltage integrated circuits and systems. From 53 submitted manuscripts, a total of 15 papers have been accepted for publication. The papers have been arranged to cover three main topics: analog and mixed-signal circuits, digital circuits, and supply/energy harvesting circuits. Below is a summary of the accepted contributions under each of the themes.
1. Analog and mixed-signal circuits In the paper “A Low-Voltage Gain Boosting-Based Current Mirror with High Input/Output Dynamic Range”, by Doreyatim et al., a bulkdriven current mirror circuit based on the gain-boosting technique to achieve high input/output dynamic range and high output resistance is presented. The bulk-driven based diode-connected transistor at the input removes the threshold voltage limitation to provide low headroom voltage on the basic transistors. Simulation results in a 0.18 μm CMOS technology show a maximum output voltage swing of 0.9 V under a 1 V supply, while the input and output resistances are 68.3 Ω and 10.5 GΩ, respectively. The current transfer error also changes between 0.085% and þ0.075% for an input current range of 1000 μA. In the paper “0.4 V fully differential current conveyor using multipleinput bulk-driven MOST technique”, by Kumngern, a new ultra-low voltage ultra-low power fully differential current conveyor (FDCCII) which is suitable for extremely low-voltage low-power analog signal circuit applications is presented. Thanks to multiple-input bulk-driven MOS transistor technique, the proposed structure employs two differential pairs which offer low complexity and low power consumption. The circuit has been used to realize summing/subtracting amplifier as design examples. The performances of the proposed FDCCII and design examples are demonstrated through PSPICE simulations using a 0.18 μm TSMC CMOS process with 0.4 V supply voltage. In the paper “Low-Voltage and Low-Power Fractional-Order Parallel Tunable Resonator”, by Bertsias et al., a novel implementation of a fractional-order parallel resonator, capable of operating in a 0.5 V power supply voltage environment, is presented. Compared to the corresponding already published structures, it offers the benefit of reduced circuit complexity, due to the utilization of very simple voltage-mode 1st-
order filter sections, leading also to reduction in the dc power consumption. Electronic tuning capability is another attractive feature of the proposed structure achieved using programmable MOS transistor transconductance parameters. In the paper “Electronically controlled voltage mode first order multifunction filter using low-voltage low-power bulk-driven OTAs”, by Jaikla et al., a new versatile voltage mode first order filter using lowvoltage low-power bulk-driven OTAs is presented. The performances of the proposed filter were evaluated via PSPICE simulations using CMOS 0.18 μm TSMC technology parameters with 0.4 V supply voltages. The proposed filter consumes 47.2 μW. The proposed filter was also experimentally validated using commercially available IC, LM13700. In the paper “A 0.6-V Pseudo-Differential OTA with Switched-Opamp technique for Low Power Applications”, by Wang et al., a low-voltage pseudo-differential OTA is presented for power-effective applications. The cross-coupled common-mode feedforward (CMFF) technique is proposed to improve the CMRR performance and double transconductance of pseudo-differential OTA with the same power consumption as the conventional one. Implemented in a 0.18-μm standard CMOS process, the OTA occupies an active chip area of 0.05 mm2 and provides the settling time of 310 ns with 0.1% accuracy for 0.6 Vpp output step. The measured input noise spectrum density is 147 dBv/√Hz (45 nv/√Hz) @ 25 MHz. The output-referred integrated noise voltage is 485 μV from 20 Hz to 25 MHz. In the paper “SOI FinFET Based Instrumentation Amplifier for Biomedical Applications”, by Sonkusare et al., a design of SOI FinFET device based Instrumentation Amplifier (IN-Amp) for biomedical applications is presented. The performance metrics of the proposed IN-Amp such as DC gain, Common mode rejection ratio (CMRR) were enhanced by using nanometre FinFET device technology. To achieve these
https://doi.org/10.1016/j.mejo.2019.104674 Available online xxxx 0026-2692/© 2019 Elsevier Ltd. All rights reserved.
Please cite this article as: F. Khateb et al., Guest Editorial: Special issue on low voltage low power integrated circuits and systems, Microelectronics Journal, https://doi.org/10.1016/j.mejo.2019.104674
Editorial
Microelectronics Journal xxx (xxxx) xxx
concept, the ternary arithmetic circuits based on GNR are designed with 0.5 V supply voltage. The computational results confirm the threshold voltages values as well as the suitable figure of merits of using GNRFETs in multiple-valued logic circuit design. In the paper “An improved read-assist-energy efficient single-ended P–P–N based 10T SRAM cell for wireless sensor network”, by Sanvale et al. a novel single ended PPN based 10T static random-access memory (SRAM) with high read stability is presented. The proposed cell is energy efficient with double ended write, and single-ended read decoupled circuit for wireless sensor networks. To evaluate the performance of the cells static noise margin, delay, power dissipation, leakage current, and area are calculated using the cadence environment at a standard CMOS 45nm process technology. The simulation results show that it has enhancement of 83.4%, 50.14%, 43.3%, 50.14% and 3.09% on read SNM when compared with the conventional 6T, ST11T, ST1, ST2, and PPN10T respectively at 1V supply voltage. The proposed cell also achieves write SNM of 1.29 , 1.12 , and 1.18 higher compared to 6T, PPN10T, and ST11T, respectively.
desirable performance metrics, size of transistors is optimized and passive resistances are replaced by active 30 nm SOI FinFET transistor. The proposed SOI FinFET based Instrumentation amplifier achieves an overall gain and CMRR of 99.6 dB and 103 dB respectively. In the paper “Reconfigurable Low voltage Low power Dual-band SelfCascode Current-Reuse Quasi-differential LNA for 5G”, by Hari Kishore et al., a low noise amplifier (LNA) which can be reconfigured to operate in two frequency bands at low power is presented. The proposed LNA is designed to operate in (3.1–4.7 GHz: Band1) and (5.0–7.2 GHz: Band2) in the 5G frequency spectrum. The proposed LNA requires an area of 0.03276 mm2. The power dissipation, maximum gain, minimum noise figure, average IIP3, IIP2 of the LNA operating in Band1 and Band2 are found to be (0.97 mW, 17.6 dB, 2.20 dB, þ0.72dBm, þ46.49dBm) and (0.485 mW, 12.1 dB, 3.31 dB, þ0.12dBm, þ42.60dBm) respectively. In the paper “A Low-Power, Low-Noise, High-Accurate Epileptic Seizure Detection System for Wearable Applications”, by Tohidi et al. a low-power epileptic-seizure-detection-system (ESDS), including an instrumentation-amplifier (IA), a level-detection-ADC (LD-ADC) and frequency-detection-units (FDUs) is presented. In the proposed ESDS, by using a PGA with variable-gain, a LD-ADC with variable samplingfrequency and FDUs with variable reset-time, the sensitivity is increased up to 100% with the latency of 8.8 s. Besides, a compatible ESDS with different low-voltage fast-activity epileptic-seizures is achieved. In the paper “Study of Circuit Performance and Non Quasi Static effect in Germanium Tunnel FET for different Temperatures”, by Ghosh et al., the impact of temperature variation is systematically analyzed in germanium (Ge) pTFET in terms of Non-Quasi-static small-signal-model parameters along with Analog Figure-of-Merits is presented. Also, linearity performance is investigated by means of IIP3 and 1-dB compression point for the variation of temperature, ranges from 200 K to 400 K. Finally, the impact of temperature variation is analyzed in mixed mode circuit simulations for the applications of cascode amplifier circuit and common source amplifier circuit.
3. Supply and energy harvesting circuits In the paper “Analysis and Design of the Dickson Charge Pump for sub-50 mV Energy Harvesting”, by Bender Machado et al., the analysis and design of a DC/DC boost converter operating from supply voltages around the thermal voltage (26 mV at room temperature), for energy harvesting applications is presented. The extremely low voltage operation, made feasible through an enhanced-swing ring oscillator and zeroVT transistors, is demonstrated via a prototype fabricated in 130 nm CMOS technology. For an input voltage of 17 mV, the converter delivers an output current of 10 nA at 1 V output and provides a current of 1 μA at a DC output of 1 V from an input voltage of 23 mV. In the paper “Load and Frequency dependent CMOS Dual-Mode DCDC Converter”, by Lee et al., a CMOS integrated dual-mode DC-DC buck converter is proposed for portable application. The proposed dual-mode converter is designed to be controlled by PFM (pulse frequency modulation) or PWM (pulse width modulation) modes which depend on the range of the output current. The PWM/PFM dual-mode converter, which is used for the application of wide current range and high power efficiency, is to generate the output voltage of 0.5–3.0 V with the battery source of 3.3–5.0 V and the load current in the range of 5–250 mA. The proposed dual-mode DC-DC buck converter is integrated with 0.35 μm CMOS process. Simulation result shows that the converter provides the well-regulated line and load regulations with power efficiency of 78–82% in the load range of 10–250 mA.
2. Digital circuits In the paper “An Ultra-low Power, Reconfigurable, Aging Resilient RO-PUF for IoT Applications”, by Khan et al., an ultra-low power, lightweight, configurable Ring Oscillator Physically Unclonable Functions (RO PUF) based on the 4T XOR architecture is presented. It has a large number of challenge-response-pair (CRP) compared to the other architectures, which makes it suitable for chip identification as well as cryptographic key generation. The proposed PUF is implemented in 40 nm CMOS technology. The simulation results show that it has a uniqueness of 0.489 and worst-case reliability of 96.43% and 93.15% at 125 C and 1.2 V, respectively. Compared to the conventional RO PUF it consumes 98.06% and 95.47% less dynamic and leakage power, respectively. In the paper “Design of FinFET based Energy Efficient Pass-Transistor Adiabatic Logic for Ultra-Low Power Applications”, by Bhuvana et al., a FinFET-based Energy Efficient Pass Transistor Adiabatic Logic (EEPAL) powered by four-phase power clock capable of operating up to 1 GHz with low energy dissipation is presented. Differential cascode adiabatic logic and pass transistor structure are employed. Furthermore, EEPAL employs discharge transistors assisting in eliminating floating output nodal issues of existing adiabatic circuits. Energetics of EEPAL and effect of parameter variations on energy dissipation have been derived and analyzed. At 500 MHz, 16-bit CSM designed using EEPAL is 25%, 34%, 21% and 12% energy efficient than CSM designed using 2N2P, 2N2N2P, PFAL and DCPAL. In the paper “Approach for MVL Design based on Armchair Graphene Nanoribbon Field Effect Transistor and Arithmetic Circuits Design”, by Nayeri et al., the approach for multiple-valued logic (MVL) design and implementing the arithmetic circuit based on armchair graphene nanoribbon field effect transistors (GNRFETs) is presented. As a proof of the
4. Conclusion All of the papers selected for this Special Issue present different kinds of analog, digital and mixed signal circuits, in most cases operating from deep sub 1V supply. The proposed circuits provide improved performance in an ultra-low voltage environment as compared with state of the art. Theoretical analyses, extensive simulations and final hardware realizations validate the proposed solutions. Acknowledgement We hope that all the papers presented in this special issue will be of interest to the readers. We would like to thank all the reviewers for their insightful comments, which helped us in evaluating the submitted papers. We also thank all the authors who have submitted their manuscripts for this special issue. Special thanks should be addressed to the Editor-inChief of the Microelectronics Journal Prof. E.G. Friedman and editorial office members for their valuable support and assistance during this project.
2
Editorial
Microelectronics Journal xxx (xxxx) xxx Fabian Khateb received the M.Sc. and Ph.D. degrees in electrical engineering and communication and also in business and management from the Brno University of Technology, Czech Republic, in 2002, 2005, 2003, and 2007, respectively. He is currently an Associate Professor with the Department of Microelectronics, Faculty of Electrical Engineering and Communication, Brno University of Technology, and also with the Department of Information and Communication Technology in Medicine, Faculty of Biomedical Engineering, Czech Technical University in Prague. He holds five patents. He has authored or co-authored over 100 publications in journals and proceedings of international conferences. He has expertise in new principles of designing low-voltage low-power analog circuits, particularly biomedical applications. He is a member of the Editorial Board of Microelectronics Journal. He is an Associate Editor of the Circuits, Systems and Signal Processing, IET Circuits, Devices & Systems, and International Journal of Electronics. He is a Lead Guest Editor for a special issue on Low Voltage Integrated Circuits and Systems for Circuits, Systems and Signal Processing (2017) and the IET Circuits Devices and Systems (2018). He is also a Guest Editor for a special issue on Current-Mode Circuits and Systems; Recent Advances, Design and Applications for the International Journal of Electronics and Communications (2017).
Luís H. C. Ferreira received the B.E. degree in control engineering and the M.Sc. and D.Sc. degrees in electrical engineering from the Federal University of Itajuba, Itajuba, Brazil, in 2002, 2004, and 2008, respectively. He was an IC Design Engineer with Freescale Semiconductors, Campinas, Brazil, from 2004 to 2006. Since 2007, he has been with the Systems Engineering and Information Technology Institute, Federal University of Itajuba, where he is an Associate Professor and a Researcher. From 2011 to 2012, he was a Visiting Faculty with the Department of Electrical and Computer Engineering, Tufts University, Medford, MA, USA, conducting research on ultralow power circuit techniques in nanometre CMOS process for biomedical applications. His current research interests include multivariable feedback control for industrial application and low-power analog and mixed-signal circuit design for biomedical and life sciences application.
Antonio J. Lopez-Martin received the M.S. and Ph.D. (Hons.) degrees from the Public University of Navarra, Pamplona, Spain, in 1995 and 1999, respectively. He was a Visiting Professor with New Mexico State University, Las Cruces, NM, USA, and an Invited Researcher with the Swiss Federal Institute of Technology, Zürich, Switzerland. He is currently Research Director and Professor at the Public University of Navarra and an Adjunct Professor at New Mexico State University. He is also a Consultant for local companies. He has authored more than 400 technical contributions in books, journals, and conferences. He holds six international patents. His current research interests include wireless transceivers and sensor interfaces with emphasis on low-voltage low-power implementations. Dr. Lopez-Martin is with the Technical Committee of various conferences. He was a recipient of the Talgo Technological Innovation Award in 2012, the ANIT’s Engineer of the Year Award in 2008, the Caja Navarra Research Award in 2007, the Young Investigator Award from the Complutense University of Madrid in 2006, the 2005 IEEE Transactions on Education Best Paper Award, and the European Center of Industry and Innovation Award in 2004 for excellence in transfer of research results to industry. He was an Associate Editor of the IEEE Transactions on Circuits and Systems–Part II: Express Briefs from 2006 to 2007 and the IEEE Transactions on Circuits and Systems–Part I: Regular Papers from 2008 to 2009.
Tomasz Kulej received the M.Sc. and Ph.D. degrees (Hons.) from Gda nsk University of Technology, Gda nsk, Poland, in 1990 and 1996, respectively. He was a Senior Design Analysis Engineer at polish branch of Chipworks Inc., Ottawa, Canada. He is currently an Associate Professor with the Department of Electrical Engineering, Częstochowa University of Technology, Poland, where he conducts lectures on electronics fundamentals, analog circuits, and computer aided design. He has authored or co-authored over 70 publications in peer-reviewed journals and conferences. He holds three patents. His recent research interests include analog integrated circuits in CMOS technology, with emphasis to low voltage and low power solutions. He serves as an Associate Editor of the Circuits Systems and Signal Processing and IET Circuits Devices and Systems. He was also a Guest Editor for the special issues on Low Voltage Integrated Circuits on Circuits Systems and Signal Processing (2017), and IET Circuits Devices and Systems (2018).
F. Khateba,*, T. Kulejb, L.H.C. Ferreirac, A.J. Lopez-Martind Brno University of Technology, Faculty of Electrical Engineering and Communication, Department of Microelectronics, Czechia b Częstochowa University of Technology, Department of Electrical Engineering, Poland c Federal University of Itajub a, Systems Engineering and Information Technology Institute, Brazil d Public University of Navarra, Department of Electrical, Electronic and Communications Engineering, Spain a
* Corresponding author. E-mail address: [email protected] (F. Khateb).
3
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Editorial
Guest Editorial: Special issue on low voltage low power integrated circuits and systems A B S T R A C T
The development of low-voltage and low-power design techniques is observed since several decades, as system power constraints and advanced deeply-scaled CMOS technologies require lower and lower supply voltages. It is predicted that the supply voltage for high performance microprocessors will be decreased to 0.6 V in a near future. Even lower supply voltage may be requested for low-power systems, especially the ones applied in biomedical implantable or wearable electronic devices, autonomous sensor nodes supplied with non-conventional energy sources and other similar applications. The requested parameters of low-voltage and low-power systems are often difficult to achieve with the use of traditional design techniques. Therefore, the circuit and system designers are seeking to develop novel architectural solutions capable to operate with low supply voltage, while maintaining acceptable performances. The main goal of this special issue is on the research challenges relating to the theory, design and applications of low voltage integrated circuits and systems. From 53 submitted manuscripts, a total of 15 papers have been accepted for publication. The papers have been arranged to cover three main topics: analog and mixed-signal circuits, digital circuits, and supply/energy harvesting circuits. Below is a summary of the accepted contributions under each of the themes.
1. Analog and mixed-signal circuits In the paper “A Low-Voltage Gain Boosting-Based Current Mirror with High Input/Output Dynamic Range”, by Doreyatim et al., a bulkdriven current mirror circuit based on the gain-boosting technique to achieve high input/output dynamic range and high output resistance is presented. The bulk-driven based diode-connected transistor at the input removes the threshold voltage limitation to provide low headroom voltage on the basic transistors. Simulation results in a 0.18 μm CMOS technology show a maximum output voltage swing of 0.9 V under a 1 V supply, while the input and output resistances are 68.3 Ω and 10.5 GΩ, respectively. The current transfer error also changes between 0.085% and þ0.075% for an input current range of 1000 μA. In the paper “0.4 V fully differential current conveyor using multipleinput bulk-driven MOST technique”, by Kumngern, a new ultra-low voltage ultra-low power fully differential current conveyor (FDCCII) which is suitable for extremely low-voltage low-power analog signal circuit applications is presented. Thanks to multiple-input bulk-driven MOS transistor technique, the proposed structure employs two differential pairs which offer low complexity and low power consumption. The circuit has been used to realize summing/subtracting amplifier as design examples. The performances of the proposed FDCCII and design examples are demonstrated through PSPICE simulations using a 0.18 μm TSMC CMOS process with 0.4 V supply voltage. In the paper “Low-Voltage and Low-Power Fractional-Order Parallel Tunable Resonator”, by Bertsias et al., a novel implementation of a fractional-order parallel resonator, capable of operating in a 0.5 V power supply voltage environment, is presented. Compared to the corresponding already published structures, it offers the benefit of reduced circuit complexity, due to the utilization of very simple voltage-mode 1st-
order filter sections, leading also to reduction in the dc power consumption. Electronic tuning capability is another attractive feature of the proposed structure achieved using programmable MOS transistor transconductance parameters. In the paper “Electronically controlled voltage mode first order multifunction filter using low-voltage low-power bulk-driven OTAs”, by Jaikla et al., a new versatile voltage mode first order filter using lowvoltage low-power bulk-driven OTAs is presented. The performances of the proposed filter were evaluated via PSPICE simulations using CMOS 0.18 μm TSMC technology parameters with 0.4 V supply voltages. The proposed filter consumes 47.2 μW. The proposed filter was also experimentally validated using commercially available IC, LM13700. In the paper “A 0.6-V Pseudo-Differential OTA with Switched-Opamp technique for Low Power Applications”, by Wang et al., a low-voltage pseudo-differential OTA is presented for power-effective applications. The cross-coupled common-mode feedforward (CMFF) technique is proposed to improve the CMRR performance and double transconductance of pseudo-differential OTA with the same power consumption as the conventional one. Implemented in a 0.18-μm standard CMOS process, the OTA occupies an active chip area of 0.05 mm2 and provides the settling time of 310 ns with 0.1% accuracy for 0.6 Vpp output step. The measured input noise spectrum density is 147 dBv/√Hz (45 nv/√Hz) @ 25 MHz. The output-referred integrated noise voltage is 485 μV from 20 Hz to 25 MHz. In the paper “SOI FinFET Based Instrumentation Amplifier for Biomedical Applications”, by Sonkusare et al., a design of SOI FinFET device based Instrumentation Amplifier (IN-Amp) for biomedical applications is presented. The performance metrics of the proposed IN-Amp such as DC gain, Common mode rejection ratio (CMRR) were enhanced by using nanometre FinFET device technology. To achieve these
https://doi.org/10.1016/j.mejo.2019.104674 Available online xxxx 0026-2692/© 2019 Elsevier Ltd. All rights reserved.
Please cite this article as: F. Khateb et al., Guest Editorial: Special issue on low voltage low power integrated circuits and systems, Microelectronics Journal, https://doi.org/10.1016/j.mejo.2019.104674
Editorial
Microelectronics Journal xxx (xxxx) xxx
concept, the ternary arithmetic circuits based on GNR are designed with 0.5 V supply voltage. The computational results confirm the threshold voltages values as well as the suitable figure of merits of using GNRFETs in multiple-valued logic circuit design. In the paper “An improved read-assist-energy efficient single-ended P–P–N based 10T SRAM cell for wireless sensor network”, by Sanvale et al. a novel single ended PPN based 10T static random-access memory (SRAM) with high read stability is presented. The proposed cell is energy efficient with double ended write, and single-ended read decoupled circuit for wireless sensor networks. To evaluate the performance of the cells static noise margin, delay, power dissipation, leakage current, and area are calculated using the cadence environment at a standard CMOS 45nm process technology. The simulation results show that it has enhancement of 83.4%, 50.14%, 43.3%, 50.14% and 3.09% on read SNM when compared with the conventional 6T, ST11T, ST1, ST2, and PPN10T respectively at 1V supply voltage. The proposed cell also achieves write SNM of 1.29 , 1.12 , and 1.18 higher compared to 6T, PPN10T, and ST11T, respectively.
desirable performance metrics, size of transistors is optimized and passive resistances are replaced by active 30 nm SOI FinFET transistor. The proposed SOI FinFET based Instrumentation amplifier achieves an overall gain and CMRR of 99.6 dB and 103 dB respectively. In the paper “Reconfigurable Low voltage Low power Dual-band SelfCascode Current-Reuse Quasi-differential LNA for 5G”, by Hari Kishore et al., a low noise amplifier (LNA) which can be reconfigured to operate in two frequency bands at low power is presented. The proposed LNA is designed to operate in (3.1–4.7 GHz: Band1) and (5.0–7.2 GHz: Band2) in the 5G frequency spectrum. The proposed LNA requires an area of 0.03276 mm2. The power dissipation, maximum gain, minimum noise figure, average IIP3, IIP2 of the LNA operating in Band1 and Band2 are found to be (0.97 mW, 17.6 dB, 2.20 dB, þ0.72dBm, þ46.49dBm) and (0.485 mW, 12.1 dB, 3.31 dB, þ0.12dBm, þ42.60dBm) respectively. In the paper “A Low-Power, Low-Noise, High-Accurate Epileptic Seizure Detection System for Wearable Applications”, by Tohidi et al. a low-power epileptic-seizure-detection-system (ESDS), including an instrumentation-amplifier (IA), a level-detection-ADC (LD-ADC) and frequency-detection-units (FDUs) is presented. In the proposed ESDS, by using a PGA with variable-gain, a LD-ADC with variable samplingfrequency and FDUs with variable reset-time, the sensitivity is increased up to 100% with the latency of 8.8 s. Besides, a compatible ESDS with different low-voltage fast-activity epileptic-seizures is achieved. In the paper “Study of Circuit Performance and Non Quasi Static effect in Germanium Tunnel FET for different Temperatures”, by Ghosh et al., the impact of temperature variation is systematically analyzed in germanium (Ge) pTFET in terms of Non-Quasi-static small-signal-model parameters along with Analog Figure-of-Merits is presented. Also, linearity performance is investigated by means of IIP3 and 1-dB compression point for the variation of temperature, ranges from 200 K to 400 K. Finally, the impact of temperature variation is analyzed in mixed mode circuit simulations for the applications of cascode amplifier circuit and common source amplifier circuit.
3. Supply and energy harvesting circuits In the paper “Analysis and Design of the Dickson Charge Pump for sub-50 mV Energy Harvesting”, by Bender Machado et al., the analysis and design of a DC/DC boost converter operating from supply voltages around the thermal voltage (26 mV at room temperature), for energy harvesting applications is presented. The extremely low voltage operation, made feasible through an enhanced-swing ring oscillator and zeroVT transistors, is demonstrated via a prototype fabricated in 130 nm CMOS technology. For an input voltage of 17 mV, the converter delivers an output current of 10 nA at 1 V output and provides a current of 1 μA at a DC output of 1 V from an input voltage of 23 mV. In the paper “Load and Frequency dependent CMOS Dual-Mode DCDC Converter”, by Lee et al., a CMOS integrated dual-mode DC-DC buck converter is proposed for portable application. The proposed dual-mode converter is designed to be controlled by PFM (pulse frequency modulation) or PWM (pulse width modulation) modes which depend on the range of the output current. The PWM/PFM dual-mode converter, which is used for the application of wide current range and high power efficiency, is to generate the output voltage of 0.5–3.0 V with the battery source of 3.3–5.0 V and the load current in the range of 5–250 mA. The proposed dual-mode DC-DC buck converter is integrated with 0.35 μm CMOS process. Simulation result shows that the converter provides the well-regulated line and load regulations with power efficiency of 78–82% in the load range of 10–250 mA.
2. Digital circuits In the paper “An Ultra-low Power, Reconfigurable, Aging Resilient RO-PUF for IoT Applications”, by Khan et al., an ultra-low power, lightweight, configurable Ring Oscillator Physically Unclonable Functions (RO PUF) based on the 4T XOR architecture is presented. It has a large number of challenge-response-pair (CRP) compared to the other architectures, which makes it suitable for chip identification as well as cryptographic key generation. The proposed PUF is implemented in 40 nm CMOS technology. The simulation results show that it has a uniqueness of 0.489 and worst-case reliability of 96.43% and 93.15% at 125 C and 1.2 V, respectively. Compared to the conventional RO PUF it consumes 98.06% and 95.47% less dynamic and leakage power, respectively. In the paper “Design of FinFET based Energy Efficient Pass-Transistor Adiabatic Logic for Ultra-Low Power Applications”, by Bhuvana et al., a FinFET-based Energy Efficient Pass Transistor Adiabatic Logic (EEPAL) powered by four-phase power clock capable of operating up to 1 GHz with low energy dissipation is presented. Differential cascode adiabatic logic and pass transistor structure are employed. Furthermore, EEPAL employs discharge transistors assisting in eliminating floating output nodal issues of existing adiabatic circuits. Energetics of EEPAL and effect of parameter variations on energy dissipation have been derived and analyzed. At 500 MHz, 16-bit CSM designed using EEPAL is 25%, 34%, 21% and 12% energy efficient than CSM designed using 2N2P, 2N2N2P, PFAL and DCPAL. In the paper “Approach for MVL Design based on Armchair Graphene Nanoribbon Field Effect Transistor and Arithmetic Circuits Design”, by Nayeri et al., the approach for multiple-valued logic (MVL) design and implementing the arithmetic circuit based on armchair graphene nanoribbon field effect transistors (GNRFETs) is presented. As a proof of the
4. Conclusion All of the papers selected for this Special Issue present different kinds of analog, digital and mixed signal circuits, in most cases operating from deep sub 1V supply. The proposed circuits provide improved performance in an ultra-low voltage environment as compared with state of the art. Theoretical analyses, extensive simulations and final hardware realizations validate the proposed solutions. Acknowledgement We hope that all the papers presented in this special issue will be of interest to the readers. We would like to thank all the reviewers for their insightful comments, which helped us in evaluating the submitted papers. We also thank all the authors who have submitted their manuscripts for this special issue. Special thanks should be addressed to the Editor-inChief of the Microelectronics Journal Prof. E.G. Friedman and editorial office members for their valuable support and assistance during this project.
2
Editorial
Microelectronics Journal xxx (xxxx) xxx Fabian Khateb received the M.Sc. and Ph.D. degrees in electrical engineering and communication and also in business and management from the Brno University of Technology, Czech Republic, in 2002, 2005, 2003, and 2007, respectively. He is currently an Associate Professor with the Department of Microelectronics, Faculty of Electrical Engineering and Communication, Brno University of Technology, and also with the Department of Information and Communication Technology in Medicine, Faculty of Biomedical Engineering, Czech Technical University in Prague. He holds five patents. He has authored or co-authored over 100 publications in journals and proceedings of international conferences. He has expertise in new principles of designing low-voltage low-power analog circuits, particularly biomedical applications. He is a member of the Editorial Board of Microelectronics Journal. He is an Associate Editor of the Circuits, Systems and Signal Processing, IET Circuits, Devices & Systems, and International Journal of Electronics. He is a Lead Guest Editor for a special issue on Low Voltage Integrated Circuits and Systems for Circuits, Systems and Signal Processing (2017) and the IET Circuits Devices and Systems (2018). He is also a Guest Editor for a special issue on Current-Mode Circuits and Systems; Recent Advances, Design and Applications for the International Journal of Electronics and Communications (2017).
Luís H. C. Ferreira received the B.E. degree in control engineering and the M.Sc. and D.Sc. degrees in electrical engineering from the Federal University of Itajuba, Itajuba, Brazil, in 2002, 2004, and 2008, respectively. He was an IC Design Engineer with Freescale Semiconductors, Campinas, Brazil, from 2004 to 2006. Since 2007, he has been with the Systems Engineering and Information Technology Institute, Federal University of Itajuba, where he is an Associate Professor and a Researcher. From 2011 to 2012, he was a Visiting Faculty with the Department of Electrical and Computer Engineering, Tufts University, Medford, MA, USA, conducting research on ultralow power circuit techniques in nanometre CMOS process for biomedical applications. His current research interests include multivariable feedback control for industrial application and low-power analog and mixed-signal circuit design for biomedical and life sciences application.
Antonio J. Lopez-Martin received the M.S. and Ph.D. (Hons.) degrees from the Public University of Navarra, Pamplona, Spain, in 1995 and 1999, respectively. He was a Visiting Professor with New Mexico State University, Las Cruces, NM, USA, and an Invited Researcher with the Swiss Federal Institute of Technology, Zürich, Switzerland. He is currently Research Director and Professor at the Public University of Navarra and an Adjunct Professor at New Mexico State University. He is also a Consultant for local companies. He has authored more than 400 technical contributions in books, journals, and conferences. He holds six international patents. His current research interests include wireless transceivers and sensor interfaces with emphasis on low-voltage low-power implementations. Dr. Lopez-Martin is with the Technical Committee of various conferences. He was a recipient of the Talgo Technological Innovation Award in 2012, the ANIT’s Engineer of the Year Award in 2008, the Caja Navarra Research Award in 2007, the Young Investigator Award from the Complutense University of Madrid in 2006, the 2005 IEEE Transactions on Education Best Paper Award, and the European Center of Industry and Innovation Award in 2004 for excellence in transfer of research results to industry. He was an Associate Editor of the IEEE Transactions on Circuits and Systems–Part II: Express Briefs from 2006 to 2007 and the IEEE Transactions on Circuits and Systems–Part I: Regular Papers from 2008 to 2009.
Tomasz Kulej received the M.Sc. and Ph.D. degrees (Hons.) from Gda nsk University of Technology, Gda nsk, Poland, in 1990 and 1996, respectively. He was a Senior Design Analysis Engineer at polish branch of Chipworks Inc., Ottawa, Canada. He is currently an Associate Professor with the Department of Electrical Engineering, Częstochowa University of Technology, Poland, where he conducts lectures on electronics fundamentals, analog circuits, and computer aided design. He has authored or co-authored over 70 publications in peer-reviewed journals and conferences. He holds three patents. His recent research interests include analog integrated circuits in CMOS technology, with emphasis to low voltage and low power solutions. He serves as an Associate Editor of the Circuits Systems and Signal Processing and IET Circuits Devices and Systems. He was also a Guest Editor for the special issues on Low Voltage Integrated Circuits on Circuits Systems and Signal Processing (2017), and IET Circuits Devices and Systems (2018).
F. Khateba,*, T. Kulejb, L.H.C. Ferreirac, A.J. Lopez-Martind Brno University of Technology, Faculty of Electrical Engineering and Communication, Department of Microelectronics, Czechia b Częstochowa University of Technology, Department of Electrical Engineering, Poland c Federal University of Itajub a, Systems Engineering and Information Technology Institute, Brazil d Public University of Navarra, Department of Electrical, Electronic and Communications Engineering, Spain a
* Corresponding author. E-mail address: [email protected] (F. Khateb).
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