Hierarchical interconnection technology

Update Hierarchical interconnection technology J R Ashman outlines plans to develop a new equipment practice to overcome the interconnection and testing problems of high-density, surface mount PCBs

Surface mount technology is enabling the density of components placed on a PC8 to be increased, but consequently presents problems for testing and interconnection of boards. In the UK a working party has been formed by the Institution of Electrical Engineers (lED to overcome these, and associated, problems. The paper considers the important factors in a new board interconnection strategy, presents some initial design specifications, and outlines the working party's future development plans. electrical hardware

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surface mount technology interconnection

Predictions of a trebling in demand for surface mount devices (SMDs) in Europe between now and 1991 are commonplace. A recent survey by the US market research company Frost & Sullivan, for example, anticipates a potential value of the European SMD market of nearly $2000M compared with estimates of $657M for the present market. While current Japanese demand for SMDs is thought to be some six times higher than that of Europe, significant European growth is nonetheless predicted, mainly in areas such as consumer appliances and television, data processing and telecommunications. The effect that these developments are having on increased board values and test times is already noticeable. Increases in packaging densities are now a matter of serious concern to production engineers confronted by the difficulties and high costs associated with testing a The McMurdo Instrument Company, Rodney Road, Portsmouth, Hampshire P04 8SG, UK

finished product, particularly when it comes to producing expensive diagnostic test programs. Equally, reworking presents additional problems due to difficulties of removing and replacing soldered-in multipin elements without impairing overall quality of the final product. In the UK, advanced engineering teams within commercial, military and telecommunications sectors have been preoccupied by these problems for some time. A broad consensus has been reached by all parties recognizing that the difficulties and costs of testing a unit of given physical size, whether for initial production or for field servicing, are aggravated by increased complexity as well as reduced numbers of access points. Both effects are implicit in the use of surface mount technology which by definition increases the overall density of packages that can be accommodated by a PCB while, arguably, precluding the use of incircuit testers and also making available only a relatively small number of edge connector contacts. These problems can be alleviated if a circuit can be partitioned into smaller units. By subdividing a double Eurocard assembly into smaller boards, reductions in board values and test times are a practical possibility. By necessitating new developments in child and daughter board substrates, subcircuit designs, connector systems and automatic test equipment (ATE) methods, while also precluding any requirement for specially developed surface mount connectors, an approach of this nature marks a significant advance in electronic equipment practice. Its ramifications are such that any successful implementation requires that development be carried out on a concerted national and international

basis to agreed standards and practices. As a result, McMurdo was instrumental last year in initially bringing together British Aerospace, British Telecom and Plessey to form a UK industry user group. Membership of the group has since been expanded to include other leading domestic professional equipment manufacturers and potential users, while part funding of development work is being provided by the British Government. This coordinated effort is being carried out under the auspices of an Institution of Electrical Engineers (lEE) working party chaired by Brian Wilkins, an ATE specialist at the University of Southampton, UK. The declared aim of the working party is to recommend to other comparable national bodies a new equipment practice standard as well as a basic connector specification, and to oversee the design and development of an entirely new interconnection system capable of meeting both domestic and international requirements.

PACKAGING Equipment practice is defined as a process by which packaging of electronic circuits in a standardized format will facilitate the building and use of systems. Anticipated codes of practice are twofold: • To provide mechanical mounting and protection suitable for electronic circuits. • To be suitable electrically in terms of connectivity, signal access, power, functional modularity, cooling and screening. Designs are being developed by an agreed connector manufacturers' consortium led by McMurdo and

0141-9331/87/05273-04 $03.00 © 1987 Butterworth & Co. (Publishers) Ltd Vol 77 No 5 June "1987

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Update consisting of Ferranti and ITT Cannon, supported by Bicc-Vero on PCB prototyping and Plessey on electronic design. Designated 'hierarchical interconnection technology' (HIT), these designs are directed towards the development of up to eight child boards parallel mounted on one side of a double Eurocard, or daughter board (Figures 1 and 2). In effect, the child board forms the basis of the entire system and is being designed in such a way as to meet a complete range of basic metric dimensional standards. The smallest of these will be 35.56 × 50.8 mm (1.4 × 2.0 in). Since other systems will require circuits with higher levels of complexity and more 'real estate', however, two standard sizes are being developed. These are single and double, the latter made possible by combining two singles occupying th~ same overall envelope.

Figure 1. unit 274

CONNECTORS Connections are routed via all four edges of one face in a north-south data and east-west control direction. A standard ATE system common to all boards is also being developed. For advanced telecommunications systems using, say, line cards, a strip connector for modular assembly in a variety of linear and rectangular configurations is being designed. For use where I/Os are relatively small in number, this will typically provide connection at each of the rectangular line cards, with child boards keyed to sockets to prevent incorrect assembly. Since current test beds are being constructed to imperial unit spacings, the contact pitch is 0.05 in. This will not, however, prohibit computeraided design using a metric grid. The connector system itself will consist of low-profile rectangular or strip

Prototype of an "hierarchical interconnection technology' assembly

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prototype connectors accepting child boards with zero insertion force to a basic specification which includes a maximum pin count of 132 at 0.050 pitch, contact resistance up to 20 mD, and a minimum life expectancy of 100 insertions. Principal component characteristics are summarized in Table 1. Daughter boards (single, double or triple Eurocards, standard telecommunications boards and line cards, or custom-designed versions embodied in computer systems or special-purpose military equipment) will accommodate both HIT and DIN backplane connectors. In reality, the backplane interface will be transferred directly to child boards so that daughter boards would therefore become standard components. Principal connector design objectives are, understandably, maximum cost effectiveness and reliability. A zero insertion force contact system based on contacts already proven in similar applications, and using a high-pressure wiping contact format, is being adopted. Connectors can be part loaded with contacts for maximum economy, while development trials are already being carried out by way of assessing the relative performance and reliability characteristics of gold, palladium nickel and tin lead.

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Update THERMAL MANAGEMENT

Table 1.

Increases in heat generation occasioned by higher-speed components and greater packaging densities will clearly demand good thermal management techniques. For HIT, standardization of the distance between a child and daughter board will allow implementation of both conductive and convective methods. In this way, for example, it will be possible to have a thermal pillar for transfer of heat from a child board to the daughter board heat plane (Figure 3). Depending on the precise application, thermal dissipation planned for the double Eurocard extends from 7 to 40W, with an average loading of 30 W. With an anticipated operating temperature range of -40°C to +125°C, a number of thermal approaches can be developed. Apart from natural convection and forced draught cooling using space under child boards and finned clamps above, altemate methods of conductive paths through thermal pillars from the underside of the child board to the heat plane on the double board can also be adopted. The enclosure formed by the child board and socket can protect components mounted on the underside of the child board from direct exposure to forced air, particularly where it may be contaminated, such as in airborne applications.

Size 60 mm max. x 55.88 mm max. x 9.2 mm max.* (*with 1.6 mm nominal thickness child board)

DEVELOPMENT PROGRAMME

Working frequencies up to 100 Mbit s-1 are planned for highspeed VLSI, although development work is initially being confined to a spectrum up to 25 Mbit s-1. Close attention has been given to contact design and layout in order to minimize the effect of mutual inductance and inductance loops. The induction of the single contact is approximately 4 nH between daughter and child board. Interconnection system development is to be complemented by the design of standard plug-in child module packages compatible with

Vol 11 No 5 June 1987

Connector characteristics

Footprints Through board: 2.54 mm (contacts may be fitted on all four sides) Materials and finishes Moulding: thermoplastic suitable for reflow soldering at 230°C Contacts: BeCu or PhBr Contact finish: tin alloy, gold etc. Termination styles Through board Surface mount Electrical Current signal contacts: 200 mA max. power contacts: 1 A max. Contact resistance: 20 m n (after test) Environmental Maximum working temperature: + 90°C Minimum working temperature: - 40°C Vibration severity: 10 Hz to 2 kHz, 0.75 mm/10gn (duration 6 h) Bump severity: 390 m s-2 (40gn), 4000 + 10 bumps Shock severity: 490 m s-2 (50 gQ) for 11 ms Acceleration severity: 490 m s-~ (50 gn) Mechanical Mechanical endurance: 100 operations Engaging and separating force: ZlF or LIF Contact retention: 10 N Fluid resistance Resistant to isopropanol, trichlorotrifluoroethane, trichloroethane and trichloroethylene

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HIT connector: thermal management options

connectors. The current programme embraces standard electronic circuit module (ECM) outlines, layers and allocations, minimum track widths

and card gaps, through-hole plate parameters, buried vias, safety earthing, voltages in excess of 25 V, screening, thermal management

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Update techniques, sinks, auto-handling and multiwire systems. Child boards may differ both in substrate materials and numbers of layers. The current development programme includes circuit board definition and analysis of modularity, i.e. design implications (including those for thermal analysis), and interconnection protocols at both mezzanine and circuit board levels. Similarly, proposals are under consideration for the development and adoption of mainstream surface mount technologies to suit HIT Connectors, including hermetically sealed components for professional and military ultrahigh-density applications as well as prepackaged and pretested surface mount components on plated through-hole FR4 PCBs. Embracing a wide variety of substrate materials, including alumina- and berylia-based compounds, this particular aspect of development work will include development of heat plates or sinks to provide thermally conductive paths. Additionally, the latest advances in thermoplastic moulding materials with high strength and low coefficient of expansion are being exploited by the development of moulded child boards with added multilayer circuits, and also by the possibility of integrally moulded connector parts. It should be noted that dielectric constant and loss factors are becoming increasingly important for modern communications electronics. Since the dielectric characteristics of currently available moulding materials can be significantly better than those of laminated substrates and ceramics, the use of additive circuit processing allied to liquid crystal polymers and a process for moulded-in electronic circuits is being investigated with a view to developing a volume production, optimum performance substrate derived from high performance materials at relatively low cost. A possible development subsequently could be a hybrid package with a secondary encapsulation stage for hermetic sealing of naked chips. Other prospective developments include an increase in interconnection density based on current

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design work on high-density backplane connectors. Alternatively, the adoption of optoelectronic interfaces with outputs from a number of cards serialized to a laser chip and routed via a flying fibre at around 10 Mbit s-1 is already being considered by a number of advanced engineering concerns. A further option under development is for line-of-sight transmit-receive coupling between adjacent HIT modules for data speeds of around 100 Mbit s-l, which create transmission problems for electromechanical systems. According to cost-benefit analyses recently carried out by a UK military equipment manufacturer, the true cost of testing any given product is largely determined by the way in which it was originally designed and built. In recognizing these considerations, HIT child boards are therefore being designed in accordance with boundary scan techniques. Testing of daughter boards will be routine for corresponding diagnosis of child boards, which can otherwise be regarded as the smallest field replacement unit. Improved diagnostic resolution will be possible by the introduction of built-in test procedures at child board level, and will therefore preclude any necessity for expensive 'bed-of-nails' testing. Overall standards of system reliability will be stringent, with a proposed mean time between failure (MTBF) rating of around 50 000 h. Assessment testingwill be carried out through environmental stressing and will include temperature cycling, industrial atmosphere and life testing to destruction in order to determine precise margins of performance in excess of basic specification requirements, on the principle of reliability 'designed-in' rather than 'tested-in'. For production, board yields will be significantly higher with smaller prebuilt units. A faster response to customer orders will therefore be possible. Similarly, repair and maintenance will be simplified. Most repair work can be carried out using pluggable elements with selfdiagnostic subassemblies, while field maintenance will be quicker with less disruption and downtime.

CONCLUSION The global potential for H IT could be considerable. This is implicitly recognized by the lEE working party which is also responsible for the submission of proposals for a new equipment practice to the British Standards Institution. The BSI has accepted the project and will be preparing a UK standard proposal (which will also include the connector specification) for consideration by other comparable national bodies.

BIBLIOGRAPHY Meyerstein, M V "HIT': a proposal for combining surface mount circuits with existing equipment practices' Internepcon Conf. (1986) Wilkins, B R "HIT': a solution to the testing problem' lEE Colloq. No 127: Computer Aided Engineering for Surface Mounted Systems (December 1986) Iloh, K 'Heat management faces demand of high thermal density' Electronic Packaging & Production 0anuary 1987) pp 136-139 ........... Iohn Ashman is technical director of The McMurdo Instrument Co. A chartered engineer, he is a fellow of the Institution of Electronic and Radio Engineers. He has been associated with the electronic components industry for a number of years, and was the recipient of the UK Design Council's first award for component design for development of the Plessey Printswffch. Responsible for the conception and initial design of hierarchical interconnection technology, he was instrumental in establishing an industry working group which led to the formation of the lEE working party now concerned with progressive development of the system to agreed standards and equipment working practices.

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