High-performance solid-state on-chip supercapacitors based on Si nanowires coated with ruthenium oxide via atomic layer deposition

Journal of Power Sources 341 (2017) 1e10

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High-performance solid-state on-chip supercapacitors based on Si nanowires coated with ruthenium oxide via atomic layer deposition Wen Zheng a, Qingmei Cheng b, Dunwei Wang b, Carl V. Thompson a, * a b

Department of Materials Science and Engineering, MIT, Cambridge, MA, 02139, USA Department of Chemistry, Merkert Chemistry Center, Boston College, MA, 02467, USA

h i g h l i g h t s

g r a p h i c a l a b s t r a c t


Solid-state supercapacitors made using ruthenium oxide coated silicon nanowires.
Fabrication process is compatible with silicon integrated circuit processing.
Ruthenium oxide provides a three order of magnitude increase in capacitance.
Specific capacitance scales with the total nanowire surface area.
High specific energies and cyclability without sacrificing power performance.

a r t i c l e i n f o

a b s t r a c t

Article history: Received 11 September 2016 Received in revised form 20 November 2016 Accepted 25 November 2016

Solid-state on-chip supercapacitors based on ruthenium oxide coated silicon nanowires were fabricated using a process that is compatible with silicon integrated circuit processing. Ordered arrays of silicon nanowires were fabricated using metal-assisted anodic etching (MAAE). Atomic layer deposition (ALD) was used to form a uniform coating of ruthenium oxide on high-aspect-ratio silicon nanowires at a moderate temperature of 290  C. Coated nanowire electrodes were studied using cyclic voltammetry and charge-discharge tests in a neutral Na2SO4 electrolyte, and a specific capacitance of 19 mFcm2 was achieved at 5 mVs1. Solid state nanowire capacitors were then fabricated with symmetric face to face nanowire arrays separated by a polymer-based electrolyte. This device exhibited a specific capacitance as high as 6.5 mFcm2 at 2 mVs1. The full device was tested over 10000 cycles under galvanostatic chargedischarge at 0.4 mAcm2, and showed a retention of 92% of the specific capacitance. The specific capacitance was found to scale with the total nanowire surface area, as controlled by controlling the aspect ratios of the wires. The solid state nanowire-based device also achieved high specific energies without sacrificing power performance. © 2016 Published by Elsevier B.V.

Keywords: Supercapacitors Silicon nanowires Ruthenium oxide Solid-state Specific capacitance Power performance

1. Introduction

* Corresponding author. E-mail addresses: [email protected] (W. Zheng), [email protected] (Q. Cheng), [email protected] (D. Wang), [email protected] (C.V. Thompson). http://dx.doi.org/10.1016/j.jpowsour.2016.11.093 0378-7753/© 2016 Published by Elsevier B.V.

In recent years, the rapid growth of the number and kinds of portable electronic devices has generated a demand for highly efficient micro power systems [1,2]. Supercapacitors, also called electrochemical capacitors, have drawn much attention due to their

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high power density and long cycle life. They store energy through electric double layer formation (electrical double layer supercapacitors) or by additional near-surface redox reactions (pseudocapacitors). In micro supercapacitors, a solid electrolyte is preferred over a liquid electrolyte, since additional encapsulation is required to prevent leakage of a liquid electrolyte. The main efforts in developing solid state micro supercapacitors have been focused on carbon-based electrode materials. Various forms of carbon or carbon composites have been investigated for solid state supercapacitor applications [3e9]. However, to further miniaturize the size of portable electronics and enable local energy delivery, it is desirable to make solid state micro supercapacitors in such a way that they can be integrated with electronics on the same chip, using CMOS compatible processes. Therefore, silicon is an obvious candidate electrode material. There has been much research to achieve high performance electric double layer type supercapacitors using silicon based materials. Various silicon structures fabricated using the vapor-liquidsolid (VLS) method have been used to increase the electrode surface area for high electrochemical performance [10e15]. However, in these studies, electrode performance was tested using a threeelectrode setup in an ionic liquid electrolyte in order to achieve stable electrochemical performance. Moreover, specific capacitances on the order of tens of mF/cm2 have been achieved in this work, which is only one order of magnitude higher than planar silicon electrodes. Silicon nanostructures including porous silicon generated using anodization [16] and porous silicon nanowires etched using metal-assisted chemical etching (MACE) [17,18] showed capacitance densities as high as 325 mF/cm2, due to their high surface area. However, the electrodes were only tested in aqueous or ionic liquid electrolytes, where a passivation layer such as SiC [17] or an ultrathin carbon sheath [16,18] was necessary to avoid reactions between the electrolyte and the silicon, in order to achieve stable performance. However, the coating processes require temperatures of 800e900  C, which significantly exceeds the maximum CMOS processing temperatures that can be used once device structures have been fabricated (~400  C). Moreover, no studies have been carried out on use of high-aspect-ratio porous silicon nanostructures in solid electrolytes. An alternative to relying on increased silicon surface areas alone to achieve high capacitances in electric double layer supercapacitors is to use silicon nanostructures as scaffolds for making pseudocapacitive type electrodes. In this case, the challenge of obtaining high capacitance densities is solved in two steps. The first step is to create three dimensional structures, such as nanowire arrays, to increase the effective silicon surface area per footprint. The second step is to modify the silicon surfaces with pseudocapacitive layers such as transition metal oxides that involve redox reactions during charging and discharging. Among various transition metal oxides for pseudocapacitor applications, ruthenium oxide stands out due to its high gravimetric capacity of nearly 1000 Fg-1 [19], good conductivity of 37 mU cm [20], and good cyclability. Hydrous ruthenium oxide was widely investigated for supercapacitor applications some time ago [21e23]. However, the high cost of the material has limited its applications for bulk supercapacitors. In recent years, ruthenium oxide has received renewed attention for its potential application in microsupercapacitors, as only a small amount is needed. Ruthenium oxide synthesized using wet chemical approaches have been combined with materials that have high surface area, including graphene [24,25], carbon nanotubes [26,27], carbon nanofibers [28], carbon nanowalls [29], porous gold [30], virus templated surfaces [31] or 3D silicon microstructures [32], in order to achieve a specific capacitance as high as a few Fcm2. However, thin film morphology is difficult to control in solution-based wet chemical synthesis. Ruthenium oxide deposited using dry thin film deposition

techniques has also been investigated for supercapacitor applications. Yoon et al. demonstrated a solid state on-chip supercapacitor with the structure of RuO2/LiPON/RuO2 and achieved a capacitance of around 6.4 mFcm2 [33] using sputter deposition of planar 200 nm RuO2 films as each electrode. Recent studies have developed recipes for deposition of ruthenium oxide using atomic layer deposition (ALD) [34,35]. ALD is superior to other techniques in that it enables precise control of the film thickness in the ultrathin regime. Moreover, it can achieve conformal coatings on high aspect ratio structures, which is not possible with sputter or e-beam deposition. A full solid state on-chip micro-supercapacitor was also developed using viruses coated using ALD RuO2, yielding a cell specific capacitance of around 0.6 mFcm2 [36]. However, in these solid state on-chip supercapacitors, planar silicon is only used as the substrate and does not contribute to the device performance. The only ALD RuO2 modified porous silicon electrode previously developed made use of an aqueous electrolyte [35], and a factor of 4800 increase in the specific capacitance was achieved through ALD RuO2 modification of electrodes for single electrode tests. However, the silicon structures in this study were fabricated through anodization of silicon. The high-aspect-ratio pores will be difficult for a solid electrolyte to access, leading to a less electrochemically active surface area compared to an aqueous electrolyte. Here we demonstrate solid state on-chip supercapacitors with excellent electrochemical properties, including high specific capacitance, high power, and high stability, based on ruthenium oxide coated silicon nanowire arrays. Arrays of silicon nanowires with high surface areas were generated in a commercial wafer through metal-assisted anodic etching (MAAE), and were used directly as a scaffold to create supercapacitor electrodes. In a second step, the silicon nanowires were coated with ruthenium oxide using ALD. Finally, a symmetric solid state full supercapacitor device was made using nanowire electrodes separated by a polymer-based solid electrolyte. The entire supercapacitor fabrication process is carried at temperatures that are compatible with integration with the manufacture of silicon based integrated circuits. The processes are also carried out using standard chemicals and tools used by the semiconductor industry. Thus our fabrication can be very costeffective considering that it can be readily integrated into standard IC processing.

2. Materials and experiment 2.1. Electrode fabrication The silicon nanowire arrays were fabricated in (100) heavily doped n-type silicon wafers using the metal-assisted anodic etching (MAAE) approach. A Au film was deposited on a silicon wafer and patterned using interference lithography to generate an ordered array of holes in the metal. Then, anodic contact was made to the Au mesh and a Pt wire was used as a counter electrode to complete the circuit. When a bias is applied between the two electrodes in an aqueous 4 M HF solution, metal assisted etching at the Au-Si interface leads to formation of silicon nanowire arrays. Lai et al. provide a more detailed discussion of the mechanisms of this process [37]. In this work, two etching conditions were used to produce wires with different aspect ratios; 20.8 mAcm2 for 5 min and 13.2 mAcm2 for 30 min. Ruthenium oxide was deposited on the nanowire arrays using ALD with Ru(EtCp)2 heated to 110  C and oxygen at room temperature serving as precursors in a commercial ALD chamber. Various numbers of ALD cycles were used to create RuO2 layers of different thickness and continuity. The growth temperature was kept at 290  C.

W. Zheng et al. / Journal of Power Sources 341 (2017) 1e10

2.2. Solid state supercapacitor fabrication Polyvinyl alcohol powder (PVA, molecular weight~125000) was purchased from Sigma-Aldrich. The solid PVA/H2SO4 electrolyte was prepared by dissolving PVA (1 g) into 10 mL of deionized water. One gram of H2SO4 was then added into the solution. This aqueous solution was vigorously stirred in a water bath at 85  C for 1 h and then cooled to room temperature. The nanowire electrodes were cut into 1 cm by 1 cm pieces, and 10 nm Ti and 100 nm Al films were deposited using e-beam evaporation to create a back contact. The polymer-based electrolyte was spin-coated onto the substrate at a speed of 1 K rpm and baked for 10 min at 45  C. Each chip was cut into halves using a diamond pen, resulting in two samples with an area of 0.5 cm by 1 cm. Another layer of electrolyte was then spin-coated on one of the electrodes at 3 K rpm, and the other electrode was placed face down on it. Finally, this symmetric device was baked in an oven at 45  C for 30 min to fully solidify the electrolyte. Pt wires were bonded to the backside Al layers using silver paste. 2.3. Characterization The morphologies of the samples were observed using a Zeiss/ Leo Gemini 982 scanning electron microscope (SEM). Transmission electron microscopy (TEM) and Energy-dispersive X-ray spectroscopy (EDX) were carried out using a JEOL 2010 FEG analytical electron microscope. X-Ray diffraction characterization was performed using a Panalytical Multipurpose Diffractometer and X-ray photoelectron spectroscopy (XPS) measurements were made using a PHI Versaprobe II X-ray Photoelectron Spectrometer. A focused ion beam was used to make cross-sections of polymer filled electrodes in a Helios Dual Beam Workstation. For electrochemical tests, the reference electrode was a commercial saturated Ag/AgCl electrode and the counter electrode was a platinum mesh. Cyclic voltammetry (CV) and galvanostatic charge/discharge measurements were conducted from 0.2 V to 0.8 V vs. Ag/AgCl in 1 M Na2SO4 aqueous solution with a potentiostat. Electrochemical impedance spectroscopy (EIS) was performed across the frequency range 7 MHz and 5 mHz with a potential amplitude of 10 mV. The solid state supercapacitors were tested with a two electrode set-up using cyclic voltammetry between 0.5 V and 0.5 V. The charge-discharge tests were carried out in the voltage window of 0 Ve1 V. Finally, the cell stability was tested using charge-discharge cycles at a constant current density. 3. Results and discussions

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studied, including planar Si substrates and silicon nanowire arrays with fixed diameters (180 nm) and center-to-center spacings (400 nm), but with different lengths of 1.8 mm, or 6.4 mm, as shown in Fig. 1a and b. These samples will be referred to as planar Si, SiNW1, SiNW2, respectively, in the following discussions. ALD was then used to deposit ruthenium oxide layers. To analyze the effect of ALD cycle numbers on the electrochemical performance, two different batches of samples were subjected to 150 ALD cycles or 400 ALD cycles. The cycle numbers are added to the electrode description to distinguish between two batches. For example, SiNW1-150cyc represents the electrodes composed of 1.8 mm tall Si NW arrays coated with ruthenium oxide using 150 ALD cycles. TEM analysis shows that a sparse coating of nanoparticles was achieved on the 150cyc electrodes, as can be seen in Fig. 2a. When the cycle number was increased to 400, impinging nanoparticles that formed a relatively continuous coating were observed on the surfaces of the nanowires, as seen in Fig. 2 bed. TEM images of different locations along the nanowires (Fig. 2b, c, and d) indicate that the coating was relatively uniform from the top to the bottom of the nanowires. However, high-resolution TEM (HRTEM) images show that most crystalline nanoparticles have lattice spacings corresponding to Ru, as shown in Fig. 2e. EDX was also performed to further characterize the elemental composition of the coatings (supplemental material, Fig. S1) and a higher ratio of ruthenium to oxygen than expected for the RuO2 phase was observed. Moreover, XRD measurements (supplemental material, Fig. S2) reveal that the new peaks observed after ALD correspond to metallic Ru, instead of crystalline RuO2. Though XRD shows that little or no crystalline RuO2 formed during the ALD process, it is still possible that amorphous RuO2 co-exists with metallic Ru. Semiquantitative XPS analysis on the SiNW2-150cyc electrodes showed asymmetric peaks indicating the presence of Ru with multiple oxidation states (Fig. 2f). A peak deconvolution analysis revealed that the dominant peaks at ~280.1 and 284.2 eV correspond to metallic Ru 3d5/2 and 3d3/2 doublet peaks, with additional peaks at positions ~1 eV higher with respect to metallic Ru, which arise from RuO2 [38]. Quantification using the metallic and oxide component spectral fits gives ~40% oxide phase and ~60% metallic Ru in this sample. Similar phenomena have been previously reported for deposition of both metallic Ru and RuO2 using ALD [35], but excellent electrochemical activity was still observed. Therefore, the as-generated electrodes were used to study the effect of the ruthenium oxide coating. However, to be more accurate in the following discussions, the deposited mixture will be referred to as RuOx. All the electrodes were evaluated using both CV and chargedischarge measurements. CV tests showed that the ALD step led to a substantial increase in the capacitance for both the 150cyc and

Three different types of heavily doped n-type substrates were

Fig. 1. SEM images of silicon nanowire arrays before ALD of RuO2: (a) 1.8 mm (SiNW1) and (b) 6.4 mm (SiNW2) tall nanowires.

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Fig. 2. TEM images of (a) a SiNW1-150cyc sample and (b) top, (c) middle, and (d) bottom views of a SiNW2-400cyc sample. (e) HRTEM of a nanoparticle on a SiNW2-400cyc sample. (f) XPS of a SiNW2-150cyc sample.

Fig. 3. CV plots for (a) 150cyc electrodes at 100 mVs1, (b) 400cyc electrodes at 100 mVs1, and (c) a Si nanowire sample (1 mm long) without RuOx at various scan rates. Full range EIS results for (d) 150cyc electrodes, (e) 400cyc electrodes, and (f) a planar Si electrode without RuOx.

W. Zheng et al. / Journal of Power Sources 341 (2017) 1e10

400cyc processes (Fig. 3a and b). However, the 150cyc electrodes exhibit deviations from ideal capacitive behaviors expected from ruthenium oxide, and these deviations are more severe for the longer Si NWs (Fig. 3a). A comparison between Fig. 3a and c reveals that CV plots for the 150cyc electrodes with long Si NWs evolve toward that of bare silicon nanowire electrodes. For Si NWs without surface modification (Fig. 3c), the large increase of the current densities near þ0.8 V vs. Ag/AgCl correspond to the oxidation of the silicon surface [17]. EIS measurements were also carried out on all seven electrodes (Fig. 3d, e and f). As can be seen in Fig. 3f, planar Si without RuOx shows a line along the diagonal direction in the lowfrequency range, instead of a line close to the vertical axis expected for ideal capacitive behavior. This is related to the unstable nature of silicon in this aqueous electrolyte during electrochemical tests, which is oxidized near þ0.8 V vs. Ag/AgCl and dissolves into the solution. This irreversible oxidation process generates a porous silicon surface. The slow ionic diffusion into the porous silicon structure results in the decreased slope from that of ideal capacitive behavior [39]. For the 150cyc electrodes, it is clear from Fig. 3d that the impedance curves in the low-frequency range move toward the diagonal direction with increasing nanowire lengths, indicating a greater contribution from Si. This is due to the sparse RuOx coating on the electrodes, which results in more silicon surface exposure to the electrolyte in longer Si NWs. However, for the 400cyc electrodes, CV plots are more rectangular and the impedance curves retain similar angles away from the vertical axis (Fig. 3e). This is due to the relatively continuous coating of RuOx that prevents the Si surface from contacting the electrolyte. Therefore, the contribution of Si to the overall electrode performance is negligible for the 400cyc electrodes. In addition to more exposure of the silicon surface, the resistance is also found to play a role in the non-ideal capacitive behavior of the 150cyc electrodes. The resistance is characterized in the high frequency regime of the impedance spectra, shown in Fig. 4a, b and c. In all of the electrodes, a tail at the highest frequencies is observed. This is likely related to the silicon substrate, as it is also seen for planar Si without RuOx (Fig. 4a). The first

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intersections of the tails with the real axis at the low-frequency end indicate the equivalent series resistance (ESR), including the resistance of the electrode, the contact resistance between the electrode and current collector, and the ionic resistance of the electrolyte. New semicircles with increasing diameters are observed with increasing wire length in the 150cyc case, following the initial tail region (Fig. 4b), while they are not observed in planar Si without RuOx. The semicircles with larger radii indicate higher resistance. The increasing resistance in the 150cyc electrodes is also due to the sparse RuOx coating, which results in an increasing intrinsic resistance for charge transfer in the longer Si NWs. As the electrical contact is made through the back of the silicon wafer, the electrons must travel through the silicon nanowires to be collected, as shown in Fig. 4d. Nanowires with small diameters and mesoporous structures, such as these, are reported to be highly resistive [40]. Moreover, the longer the nanowires are, the higher the resistance will be. However, for 400cyc electrodes, no new semicircles are seen due to a relatively continuous coating of RuOx (Fig. 4c). This continuous layer formed by RuOx nanoparticles provides a much lower resistance pathway for electron transport. As shown in the schematic (Fig. 4e), the electrons, in this case, do not need to go through the narrow silicon nanowires to be collected. The ALD coating acts both as the active electrode material and the current collector. The larger ESR of 28 U observed in the SiNW2-400cyc sample compared to 16 U for other electrodes might be related to the porous layer underneath the Si NWs generated during MAAE, as reported previously in heavily doped substrates [37]. Though the 400cyc electrodes exhibit more rectangular CV shapes, a relatively sharp peak around 0.2 V vs. Ag/AgCl is observed (Fig. 3b). This peak is probably associated with redox reactions of Ru species (e.g. Ru/Ru(II), standard potential, þ0.255 V vs. Ag/AgCl), or contaminants in the aqueous electrolyte introduced during the ALD process. CV testing was also carried out on various electrodes at different scan rates. Fig. 5a shows an example CV plot for a SiNW2-400cyc electrode from 5 mVs1 to 200 mVs1. The specific capacitance is determined from the CV plot using the following equation:

Fig. 4. Zoom in view of the high-frequency regions of the EIS spectra for (a) a planar Si sample without RuOx, (b) 150cyc electrodes, (c) 400cyc electrodes. Schematic diagrams of charge transfer in (d) 150cyc electrodes, and (e) 400cyc electrodes.

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Fig. 5. (a) CV plots for SiNW2-400cyc electrodes at different scan rates. (b) Specific capacitance of all seven electrodes obtained from CV plots at different scan rates. (c) Galvanostatic charge-discharge curves for a planar Si sample at 0.007 mAcm2, and planar Si-400cyc, SiNW1-400cyc, and SiNW2-400cyc electrodes at 0.07 mAcm2. (d) Specific capacitance of the planar Si, planar Si-400cyc, SiNW1-400cyc, and SiNW2-400cyc electrodes obtained from charge-discharge curves at different current densities.

Z jdV C¼

2V s

:

(1)

In this equation, j represents the current density, V is the potential window, s is the scan rate, and C is the specific capacitance. The extracted specific capacitances versus the scan rates for all seven electrodes are plotted in Fig. 5b. The decreasing specific capacitance with the increasing scan rate was observed for all samples because at high scan rates there is insufficient time for energy to be stored or released through the redox processes. At slow scan rates, the ALD RuOx coating resulted in a more than two order of magnitude higher specific capacitance compared to uncoated planar Si, which proves the electrochemical activity of the deposited material. The scalability of utilizing silicon nanowire arrays was then examined. For simplicity, we assume a conformal film coats the nanowires with a thickness of tR . The specific capacitance for planar electrodes and nanowire based electrodes can be calculated using Eqs. (2) and (3).

Cplanar ¼ rtR ACR ; CNW ¼ r  tR  pdl 

(2) A CR þ rtR ACR ; p2

(3)

where r is the density of the deposited material, A is the footprint of

the electrode, and CR is the gravimetric specific capacitance of the coated material. In terms of the geometry of our silicon nanowire arrays, d represents the diameter of the nanowires (180 nm), l represents the wire length, and p is the period of the nanowire arrays (400 nm). The ratio of the capacitance of a nanowire electrode to that of a planar electrode, the increase ratio, is then given by

Ratio ¼

Cnw pdl ¼ 2 þ 1: Cplanar p

(4)

The theoretical increase ratio of the specific capacitance is the same as the geometrical surface area increase ratio, and is calculated to be 7.4 for SiNW1 and 23.6 for SiNW2. At 5 mVs1, the specific capacitance densities are 0.50, 3.95, and 11.1 mFcm2 for planar-150cyc, SiNW1-150cyc and SiNW2-150cyc electrodes, which results in experimental specific capacitance increase ratios of 7.9 and 22.2 for SiNW1 and SiNW2 structures respectively. In the 400cyc batch, the experimental capacitance densities are 0.71, 5.73, and 18.8 mFcm2 for planar electrodes and short and long NW based electrodes, respectively. The increase ratios are calculated to be 8.1 and 26.4. At this slow scan rate, the experimental increase ratio matches roughly with the theoretical increase from the surface area, thus demonstrating the scalability of the specific capacitance with the surface area of nanowire arrays. From Fig. 5b, it is also clear that the specific capacitance is higher with higher ALD cycle numbers for the same Si nanowire arrays. As

W. Zheng et al. / Journal of Power Sources 341 (2017) 1e10

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Fig. 6. (a) A schematic of the symmetric solid state on-chip supercapacitors based on SiNW-RuOx electrodes. (b) CVs of full solid state devices based on bare planar Si, planar Si400cyc, SiNW1-400cyc and SiNW2-400cyc electrodes at 100 mVs1. (c) CV curves for the device made with SiNW2-400cyc electrodes at various scan rates. (d) Specific capacitance values obtained from the CV curves versus the scan rates for all solid state devices.

discussed previously, the silicon nanowires with 150cyc ALD coatings also exhibit a significant capacitance contribution from the exposed Si, as well as a significant effect from the increasing resistance. Therefore, the ALD cycle number effect will be assessed only for the planar electrodes. The CV plots show a 40% increase in the specific capacitance when going from 150 ALD cycles to 400 ALD cycles at 5 mVs1, revealing that the specific capacitance does not scale 1:1 with the cycle numbers. For supercapacitors, the electrochemical performance mainly comes from the electrode surface or near-surface layers, and the effective surface does not scale 1:1 with the cycle numbers. In fact, similar behavior and a similar explanation have been reported on electrodeposited ruthenium oxide thin film electrodes [41]. In order to reduce the use of expensive Ru while maintaining a continuous coating, the ALD process will be optimized in future experiments so that fewer deposition cycles will be needed. As discussed earlier, the 400cyc electrodes were more continuously coated, leading to a more ideal capacitive behavior. Therefore, galvanostatic charge-discharge characterization was carried out on this batch of electrodes at various current densities. A bare planar Si electrode without ALD RuOx was also tested for comparison. The specific capacitance is determined from the chargedischarge curves according to Eq. (5):

Z 2j Vdt C¼

V2

:

(5)

Here, j represents the constant discharge current density, V is the discharge potential window and C is the specific capacitance. The 400 ALD cycles yield a more than two order of magnitude increase in the specific capacitance of planar Si electrodes in our test window. SiNW1-400cyc electrodes show another factor of 8 increase over planar Si-400cyc electrodes at 0.07 mAcm2. Finally, a specific capacitance as high as 20 mFcm2 is achieved with the longest Si nanowire based electrodes at 0.07 mAcm2, which is approximately 40 times higher than the planar Si-400cyc electrode. Symmetric solid state on-chip full devices using bare planar Si and the three 400cyc batch electrodes were assembled according to the procedure described in the experimental section. Fig. 6a shows a schematic of the as-fabricated device, in which the yellow part represents the polymer-based solid electrolyte. CV measurements were carried out between 0.5 V and 0.5 V, a regime in which the devices showed nearly rectangular CV curves, as shown in Fig. 6b. The rectangular shape of the CV curves indicates a nearly ideal capacitive behavior of the device. Moreover, the peak around 0.2 V vs. Ag/AgCl observed for the 400cyc electrodes in the aqueous electrolyte is no longer present in these solid state devices, suggesting the appearance of that peak is electrolyte dependent. The four types of devices were tested at various CV scan rates, from 2 mVs1 to 200 mVs1. Fig. 6c shows an example of results for a solid state device made with SiNW2-400cyc electrodes tested at multiple scan rates. The specific capacitance was extracted from the CV curves following the same method used for the aqueous electrolyte. From Fig. 6d, it can be seen that the highest specific capacitance of

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Fig. 7. (a) Galvanostatic charge and discharge curves for symmetric cells composed of a planar bare Si electrode at 0.01 mAcm2, and planar Si-400cyc, SiNW1-400cyc and SiNW2400cyc electrodes at 0.08 mAcm2. (b) The charge-discharge curves for a solid state device based on SiNW2-400cyc electrodes at various current densities. The unit in the legend is mAcm2. (c) The specific capacitance of four types of solid state devices obtained from the galvanostatic charge and discharge curves versus the current density. (d) The specific capacitance versus cycle number for the solid state supercapacitor device based on SiNW2-400cyc electrodes at a discharge current density of 0.4 mAcm2.

Fig. 8. (a) A comparison chart for specific capacitance normalized by chip area and thickness of RuOx based pseudocapacitors made using CMOS compatible thin film deposition techniques for a variety of solid-state on-chip supercapacitors including those described in this work, ALD RuOx [36] and sputter deposited RuOx [31]. (b) Areal Ragone plot for the four types of solid state devices made in this work.

the solid state device was obtained from SiNW2-400cyc electrodes, with a value of 6.5 mFcm2 at 2 mVs1. In the solid state device, ALD coating of planar Si electrodes also yields a capacitance enhancement of more than two orders of magnitude compared to bare planar Si electrodes. In terms of scalability, at the slowest scan rate

of 2 mVs1, the SiNW1-400cyc based device shows approximately a factor of 5.5 increase over the planar Si-400cyc device. The SiNW2400cyc based device shows a factor of 15.4 increase over the planar Si-400cyc device. The weaker scalability of the solid state devices compared to measurements in the aqueous electrolyte might be

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due to either the imperfect filling of the polymer based electrolyte in the spaces between the nanowires, or damage to the nanowires such as detachment from the substrate that occurs while coating or baking the electrolyte (supplemental material, Fig S3). The solid state symmetric supercapacitors were also tested in galvanostatic charge-discharge experiments over various current densities between 0 V and 1 V, as shown in Fig. 7a and b. All devices show nearly symmetric charge/discharge curves at all current densities. The specific capacitance was calculated using the same integration method mentioned earlier with the discussion of testing in the aqueous electrolyte (Fig. 7c). Specific capacitances as high as 2.9 mFcm2 were achieved with the device based on SiNW2-400cyc electrodes at 0.08 mAcm2, which dropped to 2.3 mFcm2 at 0.4 mAcm2. Similar to the trend observed from the CV curves, the 400 ALD cycles led to a specific capacitance increase of over two orders of magnitude compared to bare Si electrodes. An additional factor of 4 and 15 times increase in the specific capacitance was achieved with SiNW1-400cyc and SiNW2-400cyc based devices at 0.08 mAcm2, respectively. Electrochemical stability of the SiNW2-400cyc electrode based solid state device was characterized using galvanostatic charge-discharge tests at 0.4 mAcm2 for 10000 cycles. Fig. 7d shows that the device achieves approximately 92% capacitance retention after 10000 charge-discharge cycles, indicating a good stability of the device. As described earlier, the solid state on-chip supercapacitors fabricated in this work achieve a specific capacitance as high as 6.5 mFcm2 at a scan rate of 2 mVs1. This is much higher than state-of-the-art silicon trench-based electrostatic capacitors, which have specific capacitances in the range of tens of mFcm2 [42e44]. It is also comparable to other types of solid state supercapacitors. For example, various carbon based solid state full cells have been reported with capacitance densities as high as 2.3 mFcm2 [45], 4.3 mFcm2 [7], and 35 mFcm2 [8]. The performance of our devices is also comparable to other on-chip solid state supercapacitors based on RuOx generated using CMOS compatible dry thin-film deposition techniques. However, when the specific capacitance of ours and others' devices are normalized by the thickness of the RuOx, it can be seen that our high specificcapacitance devices are achieved with significantly less RuOx. In this work, 400 ALD cycles yielded approximately 30 nm-thick RuOx layers, which results in a normalized specific capacitance as high as 217 mFcm2 per mm thick RuOx for the best device made in this work. This is much higher than what was achieved with solid state on-chip devices based on ALD RuO2 on a virus template (19.3 mFcm2 per mm thick RuOx) [34], and the on-chip device made with sputtered RuO2 (32 mFcm2 per mm thick RuOx) [31]. This is significant because the materials cost scales with the film thickness and because use of thicker films can contribute to higher processing costs. Given that charge is predominantly stored through redox processes in the near-surface region, tuning of the ALD process to obtain continuous coatings of reduced thickness would still further reduce the cost of ruthenium oxide. For energy storage purposes, both high energy and high power densities are desired. The specific energy and specific power can be calculated using Eqs. (6) and (7).

E¼

1 2 CV ; 2

(6)

and

P¼

9

galvanostatic charge-discharge curves, V is the voltage window, and Dt is the discharge time. The data needed to compare the power performance for the other ruthenium oxide devices shown in Fig. 8a is not provided in the references. However, a Ragone plot of the specific energy versus the specific power is shown in Fig. 8b for the devices made in this study. The units are converted to the most commonly used ones in the literature, i.e. Whcm2 and Wcm2 for energy and power. Within the test range of this work, the specific energy drops only slightly with increasing specific power for each type of device. The incorporation of high aspect ratio silicon nanowire electrodes leads to more than one order of magnitude higher specific energy than planar Si-400cyc devices, without significantly decreasing the specific power. 4. Summary and conclusions ALD deposition of RuOx on silicon nanowire arrays generated using the MAAE process has been used to fabricate solid-state supercapacitors that achieve high specific energies while maintaining high specific powers and good cyclability. We show that a high ALD cycle number of 400 is necessary to obtain relatively continuous RuOx coatings on silicon nanowires, which is crucial to achieve nearly ideal capacitive behaviors. We also demonstrate that for a given number of ALD cycles, the specific capacitance scales with the length of the silicon nanowires. The ALD deposited RuOx leads to an increase of over two magnitudes in the specific capacitance in the aqueous electrolyte. Moreover, the specific capacitance scales roughly with the geometric increase of the surface area of silicon nanowire arrays. A specific capacitance of 19 mF/cm2 is achieved using SiNW2-400cyc RuOx electrode at 5 mVs1 in the aqueous electrolyte. For solid state symmetric on-chip supercapacitors assembled with a PVA-based solid electrolyte, the specific capacitance is also significantly improved through use of silicon nanowires. The best fabricated device shows a specific capacitance as high as 6.5 mFcm2 at 2 mVs1, which is comparable with other types of solid state supercapacitors reported in literature. In addition, it shows a high specific energy of 0.4mWhcm2 at 0.03 mWcm2, and 0.32mWhcm2 at 0.17 mWcm2. The higher specific energy is achieved over planar devices without a drop in the specific power. This all-solid-state nanowire device also exhibits a good stability over 10000 cycles of charge and discharge. In addition to the excellent electrochemical performance, the devices demonstrated in this work were fabricated using a CMOS compatible process and the highest temperature used was 290  C for the ALD process. To further improve the power and energy performance, an on-chip interdigitated supercapacitor device will be explored in future work. Acknowledgments The authors acknowledge the Nanostructure Laboratory at MIT and MIT Center for Materials Science and Engineering for use of their facilities. The authors thank Jinghui Miao for assistance in XPS measurements. This work was financially supported by SingaporeMIT Alliance for Research and Technology through the program for Low Energy Electronic Systems. Appendix A. Supplementary data Supplementary data related to this article can be found at http:// dx.doi.org/10.1016/j.jpowsour.2016.11.093.

E

Dt

;

(7)

where C is the areal specific capacitance extracted from

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