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High-temperature single-hole silicon transistors
Superlattices and Microstructures, Vol. 23, No. 6, 1998 Article No. sm960360
High-temperature single-hole silicon transistors N. T. B AGRAEV, L. E. K LYACHKIN , A. M. M ALYARENKO A. F. Ioffe Physico-Technical Institute, St. Petersburg, 194021, Russia
W. G EHLHOFF Technische Universit¨at Berlin, Arbeitsgruppe EPR am Institut f¨ur Festk¨orperphysik, Rudower Chaussee 5, D-12489 Berlin, Germany
(Received 15 July 1996) We present high-temperature (77 K, 300 K) single-hole n+ –p+ –n transistors based on silicon diffusion nanostructures. This is made possible by utilizing a quantum wire with isolated quantum dots, which is naturally formed inside an ultrashallow p+ -diffusion profile using nonequilibrium diffusion processes. c 1998 Academic Press Limited
Key words: quantum dot, single-hole tunneling, transistor.
Short-time diffusion of boron and phosphorus has been performed from gas phase into n-type monocrystalline silicon using controlled surface injection of self-interstitials and vacancies. By varying the parameters of the surface oxide overlayer, the C1 levels in the gas phase and the diffusion temperature (800–1100 ◦ C), it was possible to define the criteria leading to the parity between the kick-out and dissociative vacancy diffusion mechanisms. The deceleration of the diffusion process thus achieved has permitted the fabrication of ultrashallow n+ –p+ –n transistor structures (Fig. 1) with quantum well (QW) p+ -base diffusion profile, the depth of which could be controlled using the SIMS technique over 5–30 nm (Fig. 2). The cyclotron resonance investigations and current–voltage measurements at different angles between the diffusion profile plane and the bias voltage, which was applied by the point gate contacts prepared along crystallographic axes [1], show that the p+ diffusion profiles obtained under parity between two diffusion mechanisms (900 ◦ C) consist predominantly of natural longitudinal quantum wells (LQW), whereas natural lateral quantum wells (LaQW) oriented along the h111i and h100i crystallographic axes dominate in the p+ diffusion profile realized respectively by the kick-out (1100 ◦ C) and dissociative vacancy (800 ◦ C) diffusion mechanisms. The high-temperature (77 K) quantized conductance (Fig. 3) and temperature dependencies of thermal friction coefficient (Fig. 4) [2] have revealed quantum wire systems that are formed inside LQW and LaQW because of the electrostatic confining potential induced by strong charge correlations which are responsible for a correlation gap in the DOS of the degenerate hole gas (Fig. 5A, B). The local fluctuations in the dopant distribution along a quantum wire determine the dispersion of the correlation gap value, which seems to be due to negative −U reaction: 2B 0 → B + + B − , and represent the places for the creation of dynamic quantum dots under the gate voltage (Fig. 5C, D). 0749–6036/98/061333 + 07
$25.00/0
c 1998 Academic Press Limited
1334
Superlattices and Microstructures, Vol. 23, No. 6, 1998 Voltage source (Uds)
Current measuring system (Ids)
n+ p+
n–Si
Voltage source (Ubc)
Current measuring system (Ibc)
Fig. 1. Quantum well silicon n+ –p+ –n transistor structure prepared in the Hall-effect geometry. The depth of both the n+ - and p+ diffusion profiles corresponds to the SIMS data presented in Fig. 2.
1021
2
N (B, P) (cm–3)
1 1020
1019
1018 6
12 18 X (nm)
24
Fig. 2. Quantum well diffusion profiles obtained after subsequent diffusion of boron (1) and phosphorus (2) dopants at diffusion temperatures of 900 ◦ C (1) and 1100 ◦ C (2) in n-type silicon (100)-wafers (N (P) = 2 × 1014 cm−3 ) with a thin oxide overlayer.
Superlattices and Microstructures, Vol. 23, No. 6, 1998
Longitudinal wire
6
Lateral wire 6 B
A
5 σ (4e2/h)
1335
5 T = 77 K
4
T = 77 K
4
3
Ug = 0
3
2
E || h100i
2
1
Ug = 0 E || h100i
1 0
0.1
0.2
0.3
0.4
0
0.02
0.06
Uds (V)
0.10
0.14
Urev(V)
Fig. 3. The quantized conductance (QC) at 77 K versus crystallographically oriented A drain-source and B reverse voltage applied to QW p+ -diffusion obtained at A 900 ◦ C and B 1000 ◦ C in n-type silicon (100)-wafers with a A thin and B thick oxide overlayer. The QC staircase demonstrates the weak localization regime of dynamic quantum wires created by external electric field applied along the HDQW plane.
200 S (µV K–1)
S (µV K–1)
60 40 20
0 –200 –400
A 0
100
T (K)
200
B –600
300
0
100
T (K)
200
300
S (µV K–1)
200
150
C
100 100
200
300
T (K) Fig. 4. Temperature dependencies of the thermo-efm (Seebeck coefficient) of p+ -diffusion profiles obtained at A 1100 ◦ C, B 800 ◦ C and C 900 ◦ C in n-type silicon (100)-wafers with C thin and A, B thick oxide overlayer, which reveal A a strongly correlated metal, B strong and (see also Fig. 5A) C weak localization regimes of a quantum wire.
1336
Superlattices and Microstructures, Vol. 23, No. 6, 1998
EF
Ev
EF
Ev
A EF
B
Ev
EF
Ev
C
D
Fig. 5. One-electron band scheme for the quantum wire with A multiple and B single fluctuations in a correlation energy gap near the silicon valence band; creation of dynamic quantum dots by C negative (Ug < 0) and D positive (Ug > 0) gate voltage.
Ids (µA)
0.02
T = 77 K
B
0.01 –100
–50 50
A EF Ev
–0.01
100
Uds (mV)
Ug = 0 Ug = –7.6 V
–0.02
Ug = –10.4 V
–0.03 Fig. 6. One-electron band scheme for a quantum wire with a single energy-barrier created by negative gate voltage (Ug < 0) (a) and drain–source Ids –Uds characteristics (T = 77 K) of the longitudinal quantum wire inside the QW p+ -diffusion profile, which reveal a Coulomb blockade regime for a hole transport under Ug < 0 applied to the QW n+ –p+ –n silicon field effect transistor structure.
Superlattices and Microstructures, Vol. 23, No. 6, 1998
1337
8 Longitudinal wire
7
A
Ids (pA)
6 5 4 3 2 1 0
T = 77 K 0
25
Ug = –3.1V
75 100 Uds (mV)
125
Longitudinal wire
B
50
1.30
150
1.25
Ids (pA)
1.20 1.15 1.10 1.05 T = 77 K Uds = 30 mV 1.00 –5.50
6
–5.55
–5.60 Ug (V)
Longitudinal wire
–5.65 C
Ids (pA)
5 4 3 2 1 Uds = 10 mV T = 77 K 0 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Ug (V) Fig. 7. A Coulomb staircase in A the drain–source Ids –Uds characteristics and B, C gate–voltage Ids –Ug characteristics of the longitudinal quantum wire inside the QW p+ -diffusion profile, which reveal the creation of a multiple-tunnel dot at 77 K by both A, B negative (Ug < 0) and C positive (Ug > 0) gate voltage applied to the QW n+ –p+ –n silicon transistor structure in the field-effect regime.
1338
Superlattices and Microstructures, Vol. 23, No. 6, 1998
5 Lateral wire 4
T = 77 K
2
1: Udc = 1 V 2: Udc = 2 V 3: Udc = 3 V
1
E || h100i
Iec (nA)
3
0
0.1
0.3
0.5 0.7 Uec (V)
0.9
1.1
Fig. 8. Iec –Uec characteristics of the lateral quantum wire inside the QW p+ -diffusion profile, which reveal the creation of a dynamic quantum dot at 77 K by the emitter–collector (Uec ) voltage applied to the QW n+ –p+ –n silicon transistor structure in the bipolar regime.
Ids (nA)
T = 300 K Uds = 0.1 V
Ug = 0
10
1: T = 300 K 2: T = 77 K
8
T = 77 K
2.0
5.0
1.0
2.5
Uds = 0.1 V
6 2
4
1
2
A 0
0.05
0.1 Uds (V)
0.15 0
B 0.5 Ug (V)
C 5
6 Ug (V)
7
Fig. 9. A single plateau in A the drain–source Ids –Uds characteristics and B, C the gate–voltage Ids –Ug characteristics of the longitudinal quantum wire inside the QW p+ -diffusion profile, which reveal the single hole (curve 1 in A, B and Cooper pair (curve 2 in A, C tunnelling through single fluctuation of a correlation gap by positive (Ug > 0) gate voltage applied to the QW n+ –p+ –n silicon transistor structure in the field-effect regime.
The nanotechnology suggested enables us to obtain ultrashallow n+ –p+ –n transistor structures with capacitances up to 10−19 F, which are enough to observe the charging effects of discrete holes at high temperature (Figs 6B, 7–9). The simplest version of a single-hole transistor represents a readout type based on a single energy barrier created under negative gate voltage in the quantum wires with local fluctuations in the dopant distribution (Fig. 6A, B). The high-temperature (77 K, 300 K) field-effect and bipolar transistors, which are based on isolated longitudinal and lateral quantum wires with the dynamic quantum dots created respectively by the gate and drain–source voltage, reveal Coulomb staircase, evidence supporting operation of a singlehole transistor (Figs 7A and 8). Periodic current oscillations as a function of the gate voltage, which are due to single-hole charging effect, have also been observed (Fig. 7B, C). The double step in the current plateau
Superlattices and Microstructures, Vol. 23, No. 6, 1998
1339
(Fig. 9A) and corresponding changes in the period of current oscillations versus the gate voltage demonstrate that the single fluctuations in a correlation gap value (Fig. 5B) can be present as the Josephson contacts which seem to be responsible for the hole pair tunnelling at 77 K and single hole tunnelling process at 300 K (e = C • 1Ug ; 2e = C • 21Ug , see Fig. 9B, C).
References [1] }W. Gehlhoff, N. T. Bagraev, and L. E. Klyachkin, Sol. St. Phenom. 47–48, 589 (1995). [2] }N. T. Bagraev, L. E. Klyachkin, et al. Semiconductors 29, 1112 (1995).
High-temperature single-hole silicon transistors N. T. B AGRAEV, L. E. K LYACHKIN , A. M. M ALYARENKO A. F. Ioffe Physico-Technical Institute, St. Petersburg, 194021, Russia
W. G EHLHOFF Technische Universit¨at Berlin, Arbeitsgruppe EPR am Institut f¨ur Festk¨orperphysik, Rudower Chaussee 5, D-12489 Berlin, Germany
(Received 15 July 1996) We present high-temperature (77 K, 300 K) single-hole n+ –p+ –n transistors based on silicon diffusion nanostructures. This is made possible by utilizing a quantum wire with isolated quantum dots, which is naturally formed inside an ultrashallow p+ -diffusion profile using nonequilibrium diffusion processes. c 1998 Academic Press Limited
Key words: quantum dot, single-hole tunneling, transistor.
Short-time diffusion of boron and phosphorus has been performed from gas phase into n-type monocrystalline silicon using controlled surface injection of self-interstitials and vacancies. By varying the parameters of the surface oxide overlayer, the C1 levels in the gas phase and the diffusion temperature (800–1100 ◦ C), it was possible to define the criteria leading to the parity between the kick-out and dissociative vacancy diffusion mechanisms. The deceleration of the diffusion process thus achieved has permitted the fabrication of ultrashallow n+ –p+ –n transistor structures (Fig. 1) with quantum well (QW) p+ -base diffusion profile, the depth of which could be controlled using the SIMS technique over 5–30 nm (Fig. 2). The cyclotron resonance investigations and current–voltage measurements at different angles between the diffusion profile plane and the bias voltage, which was applied by the point gate contacts prepared along crystallographic axes [1], show that the p+ diffusion profiles obtained under parity between two diffusion mechanisms (900 ◦ C) consist predominantly of natural longitudinal quantum wells (LQW), whereas natural lateral quantum wells (LaQW) oriented along the h111i and h100i crystallographic axes dominate in the p+ diffusion profile realized respectively by the kick-out (1100 ◦ C) and dissociative vacancy (800 ◦ C) diffusion mechanisms. The high-temperature (77 K) quantized conductance (Fig. 3) and temperature dependencies of thermal friction coefficient (Fig. 4) [2] have revealed quantum wire systems that are formed inside LQW and LaQW because of the electrostatic confining potential induced by strong charge correlations which are responsible for a correlation gap in the DOS of the degenerate hole gas (Fig. 5A, B). The local fluctuations in the dopant distribution along a quantum wire determine the dispersion of the correlation gap value, which seems to be due to negative −U reaction: 2B 0 → B + + B − , and represent the places for the creation of dynamic quantum dots under the gate voltage (Fig. 5C, D). 0749–6036/98/061333 + 07
$25.00/0
c 1998 Academic Press Limited
1334
Superlattices and Microstructures, Vol. 23, No. 6, 1998 Voltage source (Uds)
Current measuring system (Ids)
n+ p+
n–Si
Voltage source (Ubc)
Current measuring system (Ibc)
Fig. 1. Quantum well silicon n+ –p+ –n transistor structure prepared in the Hall-effect geometry. The depth of both the n+ - and p+ diffusion profiles corresponds to the SIMS data presented in Fig. 2.
1021
2
N (B, P) (cm–3)
1 1020
1019
1018 6
12 18 X (nm)
24
Fig. 2. Quantum well diffusion profiles obtained after subsequent diffusion of boron (1) and phosphorus (2) dopants at diffusion temperatures of 900 ◦ C (1) and 1100 ◦ C (2) in n-type silicon (100)-wafers (N (P) = 2 × 1014 cm−3 ) with a thin oxide overlayer.
Superlattices and Microstructures, Vol. 23, No. 6, 1998
Longitudinal wire
6
Lateral wire 6 B
A
5 σ (4e2/h)
1335
5 T = 77 K
4
T = 77 K
4
3
Ug = 0
3
2
E || h100i
2
1
Ug = 0 E || h100i
1 0
0.1
0.2
0.3
0.4
0
0.02
0.06
Uds (V)
0.10
0.14
Urev(V)
Fig. 3. The quantized conductance (QC) at 77 K versus crystallographically oriented A drain-source and B reverse voltage applied to QW p+ -diffusion obtained at A 900 ◦ C and B 1000 ◦ C in n-type silicon (100)-wafers with a A thin and B thick oxide overlayer. The QC staircase demonstrates the weak localization regime of dynamic quantum wires created by external electric field applied along the HDQW plane.
200 S (µV K–1)
S (µV K–1)
60 40 20
0 –200 –400
A 0
100
T (K)
200
B –600
300
0
100
T (K)
200
300
S (µV K–1)
200
150
C
100 100
200
300
T (K) Fig. 4. Temperature dependencies of the thermo-efm (Seebeck coefficient) of p+ -diffusion profiles obtained at A 1100 ◦ C, B 800 ◦ C and C 900 ◦ C in n-type silicon (100)-wafers with C thin and A, B thick oxide overlayer, which reveal A a strongly correlated metal, B strong and (see also Fig. 5A) C weak localization regimes of a quantum wire.
1336
Superlattices and Microstructures, Vol. 23, No. 6, 1998
EF
Ev
EF
Ev
A EF
B
Ev
EF
Ev
C
D
Fig. 5. One-electron band scheme for the quantum wire with A multiple and B single fluctuations in a correlation energy gap near the silicon valence band; creation of dynamic quantum dots by C negative (Ug < 0) and D positive (Ug > 0) gate voltage.
Ids (µA)
0.02
T = 77 K
B
0.01 –100
–50 50
A EF Ev
–0.01
100
Uds (mV)
Ug = 0 Ug = –7.6 V
–0.02
Ug = –10.4 V
–0.03 Fig. 6. One-electron band scheme for a quantum wire with a single energy-barrier created by negative gate voltage (Ug < 0) (a) and drain–source Ids –Uds characteristics (T = 77 K) of the longitudinal quantum wire inside the QW p+ -diffusion profile, which reveal a Coulomb blockade regime for a hole transport under Ug < 0 applied to the QW n+ –p+ –n silicon field effect transistor structure.
Superlattices and Microstructures, Vol. 23, No. 6, 1998
1337
8 Longitudinal wire
7
A
Ids (pA)
6 5 4 3 2 1 0
T = 77 K 0
25
Ug = –3.1V
75 100 Uds (mV)
125
Longitudinal wire
B
50
1.30
150
1.25
Ids (pA)
1.20 1.15 1.10 1.05 T = 77 K Uds = 30 mV 1.00 –5.50
6
–5.55
–5.60 Ug (V)
Longitudinal wire
–5.65 C
Ids (pA)
5 4 3 2 1 Uds = 10 mV T = 77 K 0 6.0 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Ug (V) Fig. 7. A Coulomb staircase in A the drain–source Ids –Uds characteristics and B, C gate–voltage Ids –Ug characteristics of the longitudinal quantum wire inside the QW p+ -diffusion profile, which reveal the creation of a multiple-tunnel dot at 77 K by both A, B negative (Ug < 0) and C positive (Ug > 0) gate voltage applied to the QW n+ –p+ –n silicon transistor structure in the field-effect regime.
1338
Superlattices and Microstructures, Vol. 23, No. 6, 1998
5 Lateral wire 4
T = 77 K
2
1: Udc = 1 V 2: Udc = 2 V 3: Udc = 3 V
1
E || h100i
Iec (nA)
3
0
0.1
0.3
0.5 0.7 Uec (V)
0.9
1.1
Fig. 8. Iec –Uec characteristics of the lateral quantum wire inside the QW p+ -diffusion profile, which reveal the creation of a dynamic quantum dot at 77 K by the emitter–collector (Uec ) voltage applied to the QW n+ –p+ –n silicon transistor structure in the bipolar regime.
Ids (nA)
T = 300 K Uds = 0.1 V
Ug = 0
10
1: T = 300 K 2: T = 77 K
8
T = 77 K
2.0
5.0
1.0
2.5
Uds = 0.1 V
6 2
4
1
2
A 0
0.05
0.1 Uds (V)
0.15 0
B 0.5 Ug (V)
C 5
6 Ug (V)
7
Fig. 9. A single plateau in A the drain–source Ids –Uds characteristics and B, C the gate–voltage Ids –Ug characteristics of the longitudinal quantum wire inside the QW p+ -diffusion profile, which reveal the single hole (curve 1 in A, B and Cooper pair (curve 2 in A, C tunnelling through single fluctuation of a correlation gap by positive (Ug > 0) gate voltage applied to the QW n+ –p+ –n silicon transistor structure in the field-effect regime.
The nanotechnology suggested enables us to obtain ultrashallow n+ –p+ –n transistor structures with capacitances up to 10−19 F, which are enough to observe the charging effects of discrete holes at high temperature (Figs 6B, 7–9). The simplest version of a single-hole transistor represents a readout type based on a single energy barrier created under negative gate voltage in the quantum wires with local fluctuations in the dopant distribution (Fig. 6A, B). The high-temperature (77 K, 300 K) field-effect and bipolar transistors, which are based on isolated longitudinal and lateral quantum wires with the dynamic quantum dots created respectively by the gate and drain–source voltage, reveal Coulomb staircase, evidence supporting operation of a singlehole transistor (Figs 7A and 8). Periodic current oscillations as a function of the gate voltage, which are due to single-hole charging effect, have also been observed (Fig. 7B, C). The double step in the current plateau
Superlattices and Microstructures, Vol. 23, No. 6, 1998
1339
(Fig. 9A) and corresponding changes in the period of current oscillations versus the gate voltage demonstrate that the single fluctuations in a correlation gap value (Fig. 5B) can be present as the Josephson contacts which seem to be responsible for the hole pair tunnelling at 77 K and single hole tunnelling process at 300 K (e = C • 1Ug ; 2e = C • 21Ug , see Fig. 9B, C).
References [1] }W. Gehlhoff, N. T. Bagraev, and L. E. Klyachkin, Sol. St. Phenom. 47–48, 589 (1995). [2] }N. T. Bagraev, L. E. Klyachkin, et al. Semiconductors 29, 1112 (1995).