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High-voltage IC driver for AC plasma panel
Technicol note High-voltage IC driver for AC plasma panel FRAN(~OISE VIALETTES
To reaJi~ a functional plasma display terminal, specific integrated circuits are required. A particular circuit for this p u r p o s e is d e s c r i b e d - - UEB 4732.
Keywords: data displays (computers), plasma display panel, high-voltage IC driver
For the last few years, AC plasma panel display systems have experienced a large development effort, mainly due to the advantages offered to the user by these flat panels: high contrast ratio, large viewing angle, no flicker, orange colour well suited to the human eye, perfect geometry, small overall dimensions, etc. Moreover, the simple structure of these displays, associated with a rugged technology, gives the plasma panel high resistance to severe environmental conditions. Plasma panels of large dimensions (512 rows x 512 columns, 1024 x 1024, etc.) are now available from several suppliers in USA, Japan and Europe.
with the current flow created by these signals. Two types of signals are needed by the plasma panel (Figure 1)2"3: sustaining voltage, swinging between 0 and + 100 V, and between 0 and - 100 V, simultaneously on all the electrodes; the switching time of the sustain waveform is short (< 0.5 las); the sustain waveform creates a luminous discharge current that can reach 100 mA for an electrode and that lasts 0.2 ~ts; the Erase
In order to realize a functional display terminal, these panels need specific integrated circuits. In response to this problem, Thomson Semiconductors has designed the UEB 4732 using its BIMOS technology, alongside Thomson CSF Electron Tube Division and with support from the French DGA (Direction Grnrrale de l'Armement). The circuit was designed after a careful study of requirements of large plasma panels. A prototype IC ~ was first manufactured. Measurements and models made using this prototype ensured that the final structure integrated in the UEB 4732 was well defined. DRIVE SIGNALS
Write
_/ v~-Vx
Sustain
-F-, ---
x_.jt
0 v
,._
~
-IOOV
-200 V
"-~
._] vv
,. . . . . a L. . . . . ~ •
_.•
~ r ..... m l . . . . . ,; ,%,,.__JJ
/
+loov ov F -lO0 v
IL
The AC plasma display panel (PDP) is an X - Y matrix gas discharge display with inherent memory. The pixel defined by the intersection of the line electrode Y and the column electrode X is driven by the voltage (Vy - Vx), created by the difference between the voltages Vy and Vx applied respectively to the line Y and the column X. The write, erase and sustain signals (Vy Vx) of a pixel are sketched in Figure 1 along with the voltages Vy and Vx of the corresponding electrodes, and
v,
Thomson Semiconductors Marketing Service, BP54, 38120 St Egreve, France
Figure 1. Command signals for an A C plasma display panel
DISPLAYS,JULY 1 9 8 6
sss''~ ," ....
I
•
sJ'-'~
s .....
0141--9382/86/030131--04 $03.00© 1986Butterworth& Co (Publishers)Ltd
+lOOV t
L
0 V
131
Technicol note C MOS logic signals
p%
0 -%
High-voltage amplifier
Ioe, l
>
I
>
4732
Logic
signals
Power supply
DI Clock Strobe Inv
I
AC plasma display panel UEB 4732
To 32 electrodes lines or columns I
Vccl vA2 Vref
vAa
I
1
>
Figure 2. Display terminal with UEB 4732 IC
drive circuit must have a low voltage drop to maintain the luminous signal of the plasma, selective writing and erasure address signals 4, bringing the selected electrodes to 100 V above the others; these signals are slow (leading edge >1 las); their role is to charge the capacitor between a selected electrode and its neighbouring electrodes, and to supply the write and erase currents of the pixels; these currents appear during the rising slope of the signal and are always below 10 mA; they can be supplied from a high impedance (1 k~2).
Clock
DI
Strobe
Inv
VA2
VA3
I
To PDP electrode
For one output
STRUCTURE OF AC PLASMA DISPLAY TERMINAL WITH UEB 4732 IC The UEB 4732 is connected directly to 32 electrodes of the PDP. It creates the sustain and selective signals from 12 V logic signals and a high voltage supply. It drives either rows or columns of the PDP. Realizing a complete AC plasma panel control system (Figure 2) requires only UEB 4732 circuits and two high-voltage common amplifiers for rows and columns of the panel. The whole network is driven by a few CMOS logic signals. 132
23
Figure 3. Block diagram DISPLAYS, JULY 1986
Technical note 32 pulses
UEB 4732 IC The UEB 4732 is an interface circuit designed using BIMOS technologyS: bipolar, CMOS and complementary DMOS on the same chip. It includes (Figure 3) a 32 bit shift register with latches, a decoding logic circuit, and a low-high voltage interface. The logic part is made of polysilicon gate CMOS, offering good integration density and low power consumption. For good immunity to input interference, differential input stages have been designed on the four logic inputs. These sta~es incorporate both bipolar and MOS devices (Figure 4)6. Moreover, the logic (V=r) and high-voltage (VA3) references are separated to avoid disturbances from high-voltage swing. The shift register can run at 8 MHz at 25°C, and 4 MHz over the whole military temperature range ( - 55°C to + 125°C). Data is entered into the shift register on the leading edge of Clock, and is stored in the 32 latches on the falling edge of Strobe. Thus, outputs are stable during the low state of Strobe, regardless of Clock and DI; and new data may be entered immediately. This offers a high rate of change of data displayed on the plasma panel.
Input
[]
I
Ii
--U]J1R . . . . . J ~ L f l J ~ 32 bits ~
DI
32 bits
I
Strobe
.....
I
I
I-
0V
Vref =VA3 vA2
axis
Output
/"1
+!00 V
¢/- "~
+100 V 0V
0V
,"~
+100V
Vref =VA3
.
.
.
.
.
.
100V
VA2 .
Output
~
.
.
.
.
.... Sustain
Write
Erase
Figure 6. Timing diagram
Vcc1/2
~ J
V ref
Figure 4. Schematic of one input I
Clock
32 pulses
V A2
Due to the Inv input, the UEB 4732 IC may drive both rows and columns of a plasma panel7: Inv causes the output state given by the 32 latches to be inverted (Inv = l) or noninverted (Inv -- 0). Inv input may also be used as a 'sustain' input: when Strobe is high, if Inv is switched low, all outputs switch low (II63); if Inv is switched high, all outputs switch high (VA2). The output stages of UEB 4732 are complementary high voltage LDMOSN and P (BVDS __> 120 V) (Figure 5). Their output impedance, for a 20 mA current, is less than 0.5 k~ at 25°C, less than 1 kfl over the whole military temperature range ( - 5 5 °C to + 125°C). Each clamp diode has voltage drop less than 2 V for a 100 mA current 8. TIMING D I A G R A M
Output to
~ PDP
electrode
VA3
Figure 5. Schematic of one output stage DISPLAYS,JULY 1986
A typical timing diagram is sketched in Figure 6. The sustain waveform is supplied by a high-voltage amplifier. The voltage reference of UEB 4732 circuits on Y axis follows this waveform, while the UEB 4732 circuits on X axis remain grounded. VA2 stays equal to Vref as long as there is no selective signal. On the two axes, rows and columns, the clamp diodes of UEB 4732 supply the sustain pulsed currents. The voltage degradation of the signal is small: AVmaX = 3 V for a 100 mA pulse simultaneously on each of the 32 outputs of a UEB 4732. The luminance is therefore kept maximal, even for a large panel with all its pixels lit. 133
1LDl:h ol nofe During the selective signals, write and erase, the highvoltage amplifier, common to all the UEB 4732 circuits, supplies a Vm voltage higher (100 V) than the IC reference voltage (Vre0. When Strobe is low, the output stages of UEB 4732 selectively address the electrodes according to the states of the latches and of lnv input. (Inv = 0 on Xaxis, Inv = 1 on Yaxis).
POWER CONSUMPTION Based on the analysis of currents and voltages in an AC plasma panel, the UEB 4732 was conceived in order to minimize the power consumption of the circuit during sustain, as well as during write and erase cycles. Since sustain represented the state used most frequently, the lowest power consumption for this case was sought. The low voltage part (logic + differential input stages) consumption is roughly 60 mW.
BIMOS TECHNOLOGY The BIMOS IC technology has been developed to address the problem of interface circuits requiring output elements with high voltages (up to 120 V) or high currents (1 A per output). This technology fits the requirements of display systems driving electronics very well. The BIMOS technology is the result of the merging of a standard junction isolated bipolar process and a silicon gate CMOS process. Although the process complexity is fairly acceptable (13 photolithographic masks), it yields a large variety of components, including NMOS and PMOS, 5-12 V; NPN and PNP, 5--12 V; N and P high-voltage lateral MOS, 120 V; NPN and PNP, BV CEO = 80 V; capacitor on gate oxide on deep N plug. The following characteristics of the BIMOS technology are worth noting. It offers low power consumption logic (CMOS) with inputs compatible with TTL or CMOS requirements. It allows easy design of analogic functions (amplification, voltage reference, etc.) The output stages can either deliver current under intermediate voltage due to bipolar components (for instance 1 A, 80 V), or hold voltages up to 120 V due to offset gate MOS devices. The push-pull type output configuration is easy to implement because both MOS and bipolar components havc complementary types.
During the sustain cycle, the power consumption is due to the current flow through the clamp diodes of the IC. For a large panel (1024 × 1024 points), the total power dissipation in a UEB 4732 does not exceed 180 mW, thanks to the low voltage drop of the clamp diodes. This maximum is reached when the 32 electrodes are all lit; if the electrodes are off, this power dissipation is less than 80 roW. For a 1024 × 1024 plasma panel addressed at a video rate, the total power consumption of a UEB 4732 circuit is roughly 300 mW (logic + sustain + write and erase cycles).
REFERENCES REALIZATION UEB 4732 is a 20 mm z chip, with 14 mm z for output stages. It is packaged in a 40 pins DIL. A micropackage is being studied. Samples of the version for commercial applications are available, while samples for military applications (UEC 4732) will be soon released.
1 Deigrange, L, Vialettes, F, Deschamps, J and Thomas, G 'A high voltage IC driver for large-area AC plasma display panels' SID Digest (1984) p 103 2
Desehamps, J 'L'affichage de donn6es graphiques ct alphanum6riques par panneau fi plasma' Revue technique Thomson-CSFVol 10, No 2 (June 1978)
3 Texas Instruments Display driver handbook (1984)
CONCLUSION The UEB 4732 circuit is particularly suited to the drive of large AC plasma panels. It delivers a 100 mA pulse current during sustain and drives selectively 32 electrodes under 0.5 kO, 20 mA for write and erase.
4
Criseimagna, T N, Beidi, J R and Trusheli, J B 'Write and erase waveform for high resolution AC plasma display panels' IEEE (1980) ch. 1520. 6/80
5
Vialettes, F and Thomas, G 'BIMOS technology and its application to plasma panel IC driver' Opto 1985 digest (1985) p 245
Its logic circuit working at 8 mHz (shift register + latches) allows a rapid change of data displayed on the panel (for example video terminal application). Its simplicity, on X and Y axes of the PDP, allows easy assembly of the plasma display terminal with only a few components.
6 le Roux, G and Vialettes, F 'Circuit de conversion d'une entr6e diff+rentielle en niveaux Iogiques CMOS' I N P I N o 85 - - 13758 7
Delgraoge, L, S~ety, M and Vialettes, F 'Circuit de commande d'un panneau ~ plasma de type alternatif' INPI No 85 --- 03227
The UEB 4732 does not need careful handling, due to its logic being shielded against disturbances induced by high-voltage swings.
8
Deigrange, L, I)eschamps, J and Vialettes, F 'AC plasma display panel control ciruit' US patent application No 431 152
134
DISPLAYS,JULY 1986
To reaJi~ a functional plasma display terminal, specific integrated circuits are required. A particular circuit for this p u r p o s e is d e s c r i b e d - - UEB 4732.
Keywords: data displays (computers), plasma display panel, high-voltage IC driver
For the last few years, AC plasma panel display systems have experienced a large development effort, mainly due to the advantages offered to the user by these flat panels: high contrast ratio, large viewing angle, no flicker, orange colour well suited to the human eye, perfect geometry, small overall dimensions, etc. Moreover, the simple structure of these displays, associated with a rugged technology, gives the plasma panel high resistance to severe environmental conditions. Plasma panels of large dimensions (512 rows x 512 columns, 1024 x 1024, etc.) are now available from several suppliers in USA, Japan and Europe.
with the current flow created by these signals. Two types of signals are needed by the plasma panel (Figure 1)2"3: sustaining voltage, swinging between 0 and + 100 V, and between 0 and - 100 V, simultaneously on all the electrodes; the switching time of the sustain waveform is short (< 0.5 las); the sustain waveform creates a luminous discharge current that can reach 100 mA for an electrode and that lasts 0.2 ~ts; the Erase
In order to realize a functional display terminal, these panels need specific integrated circuits. In response to this problem, Thomson Semiconductors has designed the UEB 4732 using its BIMOS technology, alongside Thomson CSF Electron Tube Division and with support from the French DGA (Direction Grnrrale de l'Armement). The circuit was designed after a careful study of requirements of large plasma panels. A prototype IC ~ was first manufactured. Measurements and models made using this prototype ensured that the final structure integrated in the UEB 4732 was well defined. DRIVE SIGNALS
Write
_/ v~-Vx
Sustain
-F-, ---
x_.jt
0 v
,._
~
-IOOV
-200 V
"-~
._] vv
,. . . . . a L. . . . . ~ •
_.•
~ r ..... m l . . . . . ,; ,%,,.__JJ
/
+loov ov F -lO0 v
IL
The AC plasma display panel (PDP) is an X - Y matrix gas discharge display with inherent memory. The pixel defined by the intersection of the line electrode Y and the column electrode X is driven by the voltage (Vy - Vx), created by the difference between the voltages Vy and Vx applied respectively to the line Y and the column X. The write, erase and sustain signals (Vy Vx) of a pixel are sketched in Figure 1 along with the voltages Vy and Vx of the corresponding electrodes, and
v,
Thomson Semiconductors Marketing Service, BP54, 38120 St Egreve, France
Figure 1. Command signals for an A C plasma display panel
DISPLAYS,JULY 1 9 8 6
sss''~ ," ....
I
•
sJ'-'~
s .....
0141--9382/86/030131--04 $03.00© 1986Butterworth& Co (Publishers)Ltd
+lOOV t
L
0 V
131
Technicol note C MOS logic signals
p%
0 -%
High-voltage amplifier
Ioe, l
>
I
>
4732
Logic
signals
Power supply
DI Clock Strobe Inv
I
AC plasma display panel UEB 4732
To 32 electrodes lines or columns I
Vccl vA2 Vref
vAa
I
1
>
Figure 2. Display terminal with UEB 4732 IC
drive circuit must have a low voltage drop to maintain the luminous signal of the plasma, selective writing and erasure address signals 4, bringing the selected electrodes to 100 V above the others; these signals are slow (leading edge >1 las); their role is to charge the capacitor between a selected electrode and its neighbouring electrodes, and to supply the write and erase currents of the pixels; these currents appear during the rising slope of the signal and are always below 10 mA; they can be supplied from a high impedance (1 k~2).
Clock
DI
Strobe
Inv
VA2
VA3
I
To PDP electrode
For one output
STRUCTURE OF AC PLASMA DISPLAY TERMINAL WITH UEB 4732 IC The UEB 4732 is connected directly to 32 electrodes of the PDP. It creates the sustain and selective signals from 12 V logic signals and a high voltage supply. It drives either rows or columns of the PDP. Realizing a complete AC plasma panel control system (Figure 2) requires only UEB 4732 circuits and two high-voltage common amplifiers for rows and columns of the panel. The whole network is driven by a few CMOS logic signals. 132
23
Figure 3. Block diagram DISPLAYS, JULY 1986
Technical note 32 pulses
UEB 4732 IC The UEB 4732 is an interface circuit designed using BIMOS technologyS: bipolar, CMOS and complementary DMOS on the same chip. It includes (Figure 3) a 32 bit shift register with latches, a decoding logic circuit, and a low-high voltage interface. The logic part is made of polysilicon gate CMOS, offering good integration density and low power consumption. For good immunity to input interference, differential input stages have been designed on the four logic inputs. These sta~es incorporate both bipolar and MOS devices (Figure 4)6. Moreover, the logic (V=r) and high-voltage (VA3) references are separated to avoid disturbances from high-voltage swing. The shift register can run at 8 MHz at 25°C, and 4 MHz over the whole military temperature range ( - 55°C to + 125°C). Data is entered into the shift register on the leading edge of Clock, and is stored in the 32 latches on the falling edge of Strobe. Thus, outputs are stable during the low state of Strobe, regardless of Clock and DI; and new data may be entered immediately. This offers a high rate of change of data displayed on the plasma panel.
Input
[]
I
Ii
--U]J1R . . . . . J ~ L f l J ~ 32 bits ~
DI
32 bits
I
Strobe
.....
I
I
I-
0V
Vref =VA3 vA2
axis
Output
/"1
+!00 V
¢/- "~
+100 V 0V
0V
,"~
+100V
Vref =VA3
.
.
.
.
.
.
100V
VA2 .
Output
~
.
.
.
.
.... Sustain
Write
Erase
Figure 6. Timing diagram
Vcc1/2
~ J
V ref
Figure 4. Schematic of one input I
Clock
32 pulses
V A2
Due to the Inv input, the UEB 4732 IC may drive both rows and columns of a plasma panel7: Inv causes the output state given by the 32 latches to be inverted (Inv = l) or noninverted (Inv -- 0). Inv input may also be used as a 'sustain' input: when Strobe is high, if Inv is switched low, all outputs switch low (II63); if Inv is switched high, all outputs switch high (VA2). The output stages of UEB 4732 are complementary high voltage LDMOSN and P (BVDS __> 120 V) (Figure 5). Their output impedance, for a 20 mA current, is less than 0.5 k~ at 25°C, less than 1 kfl over the whole military temperature range ( - 5 5 °C to + 125°C). Each clamp diode has voltage drop less than 2 V for a 100 mA current 8. TIMING D I A G R A M
Output to
~ PDP
electrode
VA3
Figure 5. Schematic of one output stage DISPLAYS,JULY 1986
A typical timing diagram is sketched in Figure 6. The sustain waveform is supplied by a high-voltage amplifier. The voltage reference of UEB 4732 circuits on Y axis follows this waveform, while the UEB 4732 circuits on X axis remain grounded. VA2 stays equal to Vref as long as there is no selective signal. On the two axes, rows and columns, the clamp diodes of UEB 4732 supply the sustain pulsed currents. The voltage degradation of the signal is small: AVmaX = 3 V for a 100 mA pulse simultaneously on each of the 32 outputs of a UEB 4732. The luminance is therefore kept maximal, even for a large panel with all its pixels lit. 133
1LDl:h ol nofe During the selective signals, write and erase, the highvoltage amplifier, common to all the UEB 4732 circuits, supplies a Vm voltage higher (100 V) than the IC reference voltage (Vre0. When Strobe is low, the output stages of UEB 4732 selectively address the electrodes according to the states of the latches and of lnv input. (Inv = 0 on Xaxis, Inv = 1 on Yaxis).
POWER CONSUMPTION Based on the analysis of currents and voltages in an AC plasma panel, the UEB 4732 was conceived in order to minimize the power consumption of the circuit during sustain, as well as during write and erase cycles. Since sustain represented the state used most frequently, the lowest power consumption for this case was sought. The low voltage part (logic + differential input stages) consumption is roughly 60 mW.
BIMOS TECHNOLOGY The BIMOS IC technology has been developed to address the problem of interface circuits requiring output elements with high voltages (up to 120 V) or high currents (1 A per output). This technology fits the requirements of display systems driving electronics very well. The BIMOS technology is the result of the merging of a standard junction isolated bipolar process and a silicon gate CMOS process. Although the process complexity is fairly acceptable (13 photolithographic masks), it yields a large variety of components, including NMOS and PMOS, 5-12 V; NPN and PNP, 5--12 V; N and P high-voltage lateral MOS, 120 V; NPN and PNP, BV CEO = 80 V; capacitor on gate oxide on deep N plug. The following characteristics of the BIMOS technology are worth noting. It offers low power consumption logic (CMOS) with inputs compatible with TTL or CMOS requirements. It allows easy design of analogic functions (amplification, voltage reference, etc.) The output stages can either deliver current under intermediate voltage due to bipolar components (for instance 1 A, 80 V), or hold voltages up to 120 V due to offset gate MOS devices. The push-pull type output configuration is easy to implement because both MOS and bipolar components havc complementary types.
During the sustain cycle, the power consumption is due to the current flow through the clamp diodes of the IC. For a large panel (1024 × 1024 points), the total power dissipation in a UEB 4732 does not exceed 180 mW, thanks to the low voltage drop of the clamp diodes. This maximum is reached when the 32 electrodes are all lit; if the electrodes are off, this power dissipation is less than 80 roW. For a 1024 × 1024 plasma panel addressed at a video rate, the total power consumption of a UEB 4732 circuit is roughly 300 mW (logic + sustain + write and erase cycles).
REFERENCES REALIZATION UEB 4732 is a 20 mm z chip, with 14 mm z for output stages. It is packaged in a 40 pins DIL. A micropackage is being studied. Samples of the version for commercial applications are available, while samples for military applications (UEC 4732) will be soon released.
1 Deigrange, L, Vialettes, F, Deschamps, J and Thomas, G 'A high voltage IC driver for large-area AC plasma display panels' SID Digest (1984) p 103 2
Desehamps, J 'L'affichage de donn6es graphiques ct alphanum6riques par panneau fi plasma' Revue technique Thomson-CSFVol 10, No 2 (June 1978)
3 Texas Instruments Display driver handbook (1984)
CONCLUSION The UEB 4732 circuit is particularly suited to the drive of large AC plasma panels. It delivers a 100 mA pulse current during sustain and drives selectively 32 electrodes under 0.5 kO, 20 mA for write and erase.
4
Criseimagna, T N, Beidi, J R and Trusheli, J B 'Write and erase waveform for high resolution AC plasma display panels' IEEE (1980) ch. 1520. 6/80
5
Vialettes, F and Thomas, G 'BIMOS technology and its application to plasma panel IC driver' Opto 1985 digest (1985) p 245
Its logic circuit working at 8 mHz (shift register + latches) allows a rapid change of data displayed on the panel (for example video terminal application). Its simplicity, on X and Y axes of the PDP, allows easy assembly of the plasma display terminal with only a few components.
6 le Roux, G and Vialettes, F 'Circuit de conversion d'une entr6e diff+rentielle en niveaux Iogiques CMOS' I N P I N o 85 - - 13758 7
Delgraoge, L, S~ety, M and Vialettes, F 'Circuit de commande d'un panneau ~ plasma de type alternatif' INPI No 85 --- 03227
The UEB 4732 does not need careful handling, due to its logic being shielded against disturbances induced by high-voltage swings.
8
Deigrange, L, I)eschamps, J and Vialettes, F 'AC plasma display panel control ciruit' US patent application No 431 152
134
DISPLAYS,JULY 1986