Hole trapping in flash EEPROM gate oxide and damages induced by gate to source erasing

J O U R N A L OF

ELSEVIER

Journal of Non-Cry stalline Solids 216 (1997) 162 - 167

Section 6. Electrical characterisation: charge injection

Hole trapping in flash EEPROM gate oxide and damages induced by gate to source erasing P. Candelier a,*, F. Mondon b, B. Guillaumot c, G. Reimbold a, F. Martin

a

a G R E S S I / L E T I / ( C E A ) 17 Rue des martyrs 38054 Grenoble cedex 9, France b j. Fourier University Grenoble, Grenoble, France c SGS/Thomson BP 217 F38019, Grenoble cedex, France

Abstract

Gate to source erasing damages are investigated with regards to evolution of electron and hot hole current components during erasure stressing. Measurements on transistors (dummy cells) show that hole current dominates at the beginning of the stress but progressively decreases due to hole trapping. Electron erasing current increases for long stress times and smaller electric fields. Over erasing of flash cells is then related to this current increase, taking into account the floating gate potential variation during erasing step. © 1997 Elsevier Science B.V.

1. Introduction

Source side erasing of flash EEPROM (electrically erasable programmable read only memory) is faster than channel erasing but induces more severe device degradation. The main problem is positive trapping in the gate oxide. It was reported to induce accelerated charge loss due to enhanced F o w l e r Nordheim conduction [1,2]. It is also assumed to be responsible for 'over-erasing' failure of the memory cell through apparently erratic enhancement of erasing rate [3]. Analysis of experimental data and simulations [2,4] have shown that erasing current splits into three parts (i) gate to channel Fowler Nordheim (FN) erasing current, (ii) gate to source FN current and (iii) source to gate hot hole erasing current (Fig. 1). Hot holes arise from band-to-band tunneling

* Corresponding author. Tel.: +33-4 76 88 40 45; fax: +33-4 76 88 94 57; e-mail: [email protected].

(BTBT) in the strongly reverse biased source-channel junction. Despite many studies, no clear correlation was made between source side erasing mechanisms and over-erasing. This work presents a detailed analysis of electron and hole contributions to erasing current from which gate current evolution is related to flash cells write/erase cycling and overerasing.

2. Devices

Devices are 0.35 Ixm channel length flash EEPROM cells engineered for the transition from 64 Mbit to 256 Mbit generations. The gate oxide is 11.5 nm thick while interpoly dielectric is a 13.5 nm O - N - O layer obtained by a full LPCVD process [5]. Source and drain are implanted with 30 ° tilt, in four 90 ° rotations with 1014 c m - 2 A s + dose together with boron implantation to avoid punch-through in short channel devices. As the main concern is gate oxide

0022-3093/97/$17.00 © 1997 Elsevier Science B.V. All rights reserved. PII S 0 0 2 2 - 3 0 9 3 ( 9 7 ) 0 0 1 82- 8

P. Candelier et al. / Journal of Non-Crystalline Solids 216 (1997) 162-167

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Fig. 1. Erasing current splits into three parts (i) gate to channel FN erasing current, (ii) gate to source FN current and (iii) source to gate hot hole erasing current.

wearout during erasure, measurements were also cartied on using transistor structures rather than double-poly memory cells. This allowed direct control of voltages applied to the gate oxide. These transistors were processed with exactly the same characteristics as actual memory cells and obtained by providing contact between floating gate and control gate ('dummy cells' with 0.35 × 0.35 ixm 2 or 100 × 100 i~m 2 area). Other test structures are large area - - large perimeter MOS capacitors surrounded by a n + ring (gated diodes).

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1 0

101

102

103

104

105

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Write/erase cycles Fig. 2. W r i t e / E r a s e window measurement on 0.35 pLm flash cell. All ceils are written in 10 ms at Vd = 4 V, Vgc = 7.5 V. M a x i m u m deviation from die to die is 0.3 V on programmed state and 0.7 V on erased state. Vg, ~ and erase time are respectively: - 14 V, 0 V. 0.5 s (zx); - 1 1 V, 4.5 V, 0.3 s (1:3) and - 10 V, 6 V, 0.1 s ( O ) . Lines are drawn as guides for the eye.

3. Experiment: Cycling and erasing stress conditions

at high source voltages, it is thus linked to specific defects probably trapped hole localized at the gate oxide-source edge [3,6,7].

3.1. Write-erase stressing of flash EEPROM

3.2. Write-erase stress of dummy cells

Memory cells are programmed by hot electron injection with Vg = 7.5 V; V0 = 4 V; ~ = 0 V (these voltages are referenced to the p-Si substrate). They are erased either by FN electron transfer from floating gate to the channel (channel erasing: Vg = - 1 4 V; V~ = 0) or source side conduction (gate-source erasing GSE: Vg = - 1 0 V; ~ = 6 V for instance). Erasing conditions can be varied while the gatesource voltage Vgs is kept constant by changing both Vg and V,. The first consequence of cell aging is the gradual closure of the programming window. In addition, a sudden decrease of erased-state and programmed-state Vth values appears unexpectedly when a high erasing source voltage is used. In the experiment displayed Fig. 2 (Vg = - 1 0 V, V~= + 6 V), this over-erasure is followed by Vth_low and Vth_high recovery before definitive V~ drift. In a memory array, the first occurrence of over-erasing dramatically shortens the device life time, as the over-erased cell sinks too much current and disturbs all other cells on the same bit line. Over-erasing occurs mainly

Write-erase stress on dummy cells is compared to write only and erase only repeated stress. The 2 1.5 1

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Cycles Fig. 3. D u m m y cells threshold voltage shift under Write-Erase, Write only and Erase only repeated stress. (Write 10 ms, Vg = 5 V, Vd = 4 V; Erase 0.1 s, Vg = - 10 V. ~ = 6 V). Lines are drawn as guides for the eye.

164

P. Candelier et al. / Journal of Non-Crystalline Solids 216 (1997) 162-167 Equivalent erasing cycles 20 103

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Cycles Fig. 4. Dummy cells transconductance variation under WriteErase, Write only and Erase only repeated stress. (Write 10 ms, Vg = 5 V, Vd = 4 V; Erase 0.1 s , V g = - 10 V, ~ = 6 V). Lines are drawn as guides for the eye.

dummy cells threshold voltage and transconductance variations are reported in Figs. 3 and 4. Erasing stress on 0.35 Ixm devices induces Vth decrease and gm increase, which is consistent with short channel effects induced by hole trapping next to the source [7]. For long stress times the acceptor-like interface traps generation explains the transconductance decrease. Writing stress induces Vth increase and gm decrease. This is related to electron trapping and interface state generation near the drain [8]. When both W / E stress are applied the long term Vth shift is the same as for write-only stress. This shift is consistent with the behavior of oxide trapped charges: electron trapping is non-reversible, while trapped holes and positive-charged traps created under negative gate bias can be discharged under bias reversal [9]. Erase-only stressing thus appears as a worst case for flash cells reliability as it induces a large positive charge build up in the gate oxide.

........ I ........ I 10z

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Stress time (s) Fig, 5. Gate current evolution under static gate to source erasing stress Vg = - 10 V, V~ = + 6 V on 100× 100 ixm z devices. The equivalent erasing cycle number is calculated from injected charge,

ments performed after stress display positive trapping (Fig. 6): at constant Vgs, the trapped charge increases together with the source-substrate voltage Vs. Gate to substrate current measurements at various stress time (Fig. 7) show enhanced conduction at low electric field (stress induced leakage current) while the current is only slightly increased at high electric field.

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Static gate-source erasing stress (Vg = - 10 V, Vs = 6 V) was performed on large area gated diodes (n + ring connected as the source). The gate-source current regularly decreased during the first 3000 s, then it increased slightly until breakdown at = 6000 s (Fig. 5). The injected charge at 3000 s corresponds to 3 × 106 erase cycles. Charge pumping measure-

-8

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V g l (V) Fig. 6. Charge pumping measurement (500 kHz, 50 ns, AVs = 3 V) before and after erasing stress. The device is an array of 0.6 × 0.6 Ixm2 gated diodes with a total area of 30000 g,m 2 and a 45000 I.tm source junction perimeter. Lines are drawn as guides for the eye.

P. Candelier et al./Journal of Non-C~stalline Solids 216 (1997) 162-167 I . . . . . .

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Gate voltage (V) Fig. 7. Negative gate FN current measurement on 100× 100 p,m2 dummy cells for various injected charge at Vg = - 10 V and V,,= 6 V. Lines are drawn as guides for the eye.

Charge pumping results can be explained by band to band tunneling (BTBT) hot hole generation followed by trapping in the gate oxide: more holes are generated at the source junction at high Vs. On the contrary, FN conduction would yield less positive trapping when Vs is increased as the oxide electric field is reduced in the channel region. Gate currentvoltage measurements after stress are consistent with defects generation in the source/gate overlap area: the high field current is not affected, within errors of measurements, by the stress as it is dominated by FN channel conduction in the 100 × 100 p,m 2 devices. The gate-source current variation is not consistent with FN electron conduction, as the current should increase owing to positive trapping, as usually observed with capacitors under FN stress. In addition, the erasing current decrease observed in the first 3000 s cannot leads to over-erasing which generally appears between 105 and 10 6 write-erase cycles. Other evidences of positive charge trapping near the source are found in the literature [2,10] and strengthen the hypothesis that hot hole erasing current linked to BTBT hole generation can dominate in gate to source erasing conditions. A more detailed analysis of flash cell erasing step and erasing currents is required to investigate the respective contributions of gate-source electron current and hot hole injection at various source biases.

Static stressing of dummy cells or capacitors is far from real operating conditions of the memory cell; on the opposite, no current measurement can be carried out on memory cells under actual erasing conditions. When a memory cell is erased, the floating gate potential Vfg varies due to the variation of the stored charge in the floating gate. For instance in GSE conditions (Vgc = - 10 V, ~ = 6 V), we have calculated that Vfg started from - 10 V to reach - 6 V. This change was taken into account by stressing dummy cells using a Vg ramp varying from - 10 V to - 6 V, however the ramp rate was small (0.2 V / s ) to allow gate current measurements. The stress is achieved repeating this ramp while K is constant (V, = 6 V), the injected charge during one ramp is equivalent to 2600 erasure cycles. The Ig(Vg) variations during selected ramps are displayed on Fig. 8. A first aging phase (up to index 125) is characterized by current decreasing in all the Vg range. During the second phase (from index 266), a large current increase takes place in the lower Vg range. We explain such gate current evolution by the variations of the different erasing current components. Analysis of gate current variation with Vs (at constant Vg~) allows separation of electron and hole contributions to erasing current [4]. The FN gate to

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P. Candelier et aL /Journal of Non-Crystalline Solids 216 (1997) 162-167

166

channel erasing current (i) flows only at high gate voltages (low V~). The gate to source erasing current (ii) should remain constant with ~ as VgS is constant (in fact, it can decrease with V~ due to source substrate junction depletion depth increase). Hot hole erasing current (iii) generated by BTBT increases exponentially with V~, an empirical formula for this current is [2]: Jbb = aE~ e x p [ - (b)/(Esi)] (Esi is the electric field in silicon, a and b are empirical fitting parameters). The gate current was plotted versus ~ (at constant Vgs) at some stages of the stress (Fig. 9). Before stress, the gate current increases with V~ (from V~= 4.5 V to 7 V). This increase is due to an increase of hot hole erasing current which dominates at VS > 6 V. However, charge trapping during stress would modify each current contribution. For moderate stress (80 ramps), corresponding to the first aging phase, the gate current is less and still dependent on Vs. For larger stress (400 ramps), the gate current is increased and constant, in the 5 - 7 V range. We explain this change by hole trapping in the gate oxide near the source-channel junction [2]. The positive charge both repels hot holes and enhances electron injection from the gate. For a moderate stress, the hot hole component is reduced but still dominating, while for longer stress the hole current decreases enough to be masked by the increased gate-source FN electron current.

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5. I m p a c t of erasing stress on erased charge

During flash cells erasing, the floating gate potential is large at short times and progressively decreases with a longer time spent at low gate potential. The gate current increase at low gate voltages (second aging phase) should then have a large impact on erased charge. A model was then developed to evaluate the erased charge from lg(Vg) measurement on dummy cells. It takes into account the time spent at each gate bias. The gate current measured on dummy cells presented Fig. 8, can be fitted by the law lg =/gO exp(-SVfg),

where Ig is the gate current, Veg is the floating gate potential, /go and S are curve fitting parameters. The floating gate potential is given by the relation (2) from [11]: Vfg(t)

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Source voltage (V) Fig. 9. G a t e c u r r e n t m e a s u r e m e n t o n 1 0 0 × 100 p , m 2 d u m m y cells b e f o r e a n d d u r i n g e r a s i n g s t r e s s ( V d = 0 V ) at c o n s t a n t g a t e to s o u r c e v o l t a g e . L i n e s are d r a w n as a g u i d e f o r t h e eye.

Cono

(2)

where Qjg is the stored charge in the floating gate, Cono is the interpoly capacitance, V~ and Vgc are the source and the control gate voltages, respectively ag and a S are the gate and source coupling ratios: ag = ( C o n o / / ( f t ) and a s = (Cs)/(C t) with Ct = Cono + Cch + C s where Cch is the capacitance between floating gate and the Si substrate, CS is the capacitance between the floating gate and the source junction. We have calculated ag = 0.7 from flash cell design dimensions, ONO and gate oxide thicknesses measured by C(V). After derivation of Eq. (2) and using Eq. (1), a differential equation is established which solution is the floating gate potential variation during erasing step: Vfg(t) = -~ In

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(1)

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t + exp(SVfg0) ,

(3)

where a r is the erasing area ratio between the 0.35 ~m flash cell and 100 Ixm dummy cell. Vfg0 is the floating gate voltage at the beginning of erasing step. Calculated erasing characteristic is in agreement with measurement on flash cells (Fig. 10). Erased charge is derived from each Ig(Vg) curve presented Fig. 8, its variation is plotted versus equivalent era-

P. Candelier et al. / Journal of Non-Crystalline Solids 216 (1997) 162-167

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(compensated by larger gate voltage) delays the failure, owing to reduced positive charge generation.

Calculated erasing ,~ characteristic

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Erasing time (s) Fig. 10. Comparison between measured and calculated erasing characteristic. (Parameters for simulation: Ig(Vfg) @ V~= 6 V fit: S=2.027 lgo=2.26X10 -18 A: V f g 0 = - 1 0 V; a r = 0 . 4 / 1 0 0 ; Con° = 1.22X 10 -15 F; otg = 0.7), Lines are drawn as a guide for the eye.

Gate to source erasing of flash EEPROM induces source side localized damages which are mainly trapped holes. Erasing current is then altered during cell cycling. The hole component is reduced while, at the end of erasure step, the electron current grows larger as wearout proceeds. Taking into account the erasing current, floating gate potential, erasing time relations, we demonstrated that erasure stress induces a large increase of the erased charge, leading to over erasure. Erasing stress can be reduced by decreasing source voltage and increasing the gate voltage, however the erasing step is then longer. Acknowledgements

sure cycle number on Fig. 11. After a small decrease of the erased charge (gate current lowering during first aging phase), a 20-30% increase is obtained corresponding to 1 V decrease of erased-state Vth (second aging phase). The same work repeated for larger source voltage shows that the onset of over erasure is faster while source voltage reduction 40

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-10 ........ ~ ........ i ........ I 103 104 105 106 Cycles Fig. 11. Calculated erased charge versus equivalent number of cycles. Calculation accuracy should be + 5%, due to residual error on initial curve fit. Each point corresponds to one lg(Vg~ ramp presented Fig. 8. The injected charge during one ramp is equivalent to 2600 erasure cycles. The line is drawn as guide for the eye.

This work was carried out within the GRESSI Consortium between CEA-LETI and FranceT~16com-CNET References [1] S. Haddad, C. Chang, A. Wang, J. Bustillo, J. Lien, T. Montalvo, M. Van Buskirk, IEEE Electron Dev. Lett. 11 (1990) 514. [2] K.T. San, C. Kaya, T.P. Ma, IEEE Trans. Electron Dev. 42 (1995) 150. [3] C. Dunn, C. Kaya, T. Lewis, T. Strauss, J. Schreck, P. Helfey, M. Middendorf, T. San, Proc. IEEE IRPS (1994) 299. [4] C. Huang, T. Wang, T. Chert, N.C. Peng, A. Chang, F.C. Shone, Proc. IEEE IRPS (1995) 61. [5] B. Guillaumot, P. Candelier, F. Martin, Proc. IEEE Nonvolatile Semiconductor Memory Workshop (1995) 4.1. [6] C. Huang, T. Wang, N.C. Peng, Y. Chang, T. Chen, S. Wu, F.C. Shone, Proc. IEEE Nonvolatile Semiconductor Memory Workshop (1995) 3.3. [7] J. Chert, J. Hsu, S. Luan, Y. Tang, D. Liu, S. Haddad, C. Chang, S. Longcor, J. Lien, Proc. IEDM (1995) 331. [8] S. Yamada, Y Hiura, T. Yamane, K. Amemiya, Y. Ohshima, K. Yoshikawa, Proc. IEDM (1993) 23. [9] A. Meinertzhagen, C. Petit, G. Yard, M. Jourdain, G. Salace, J. Appl. Phys. 79 (1996) 2549. [10] K.T. San, T.P. Ma, IEEE Electron Dev. Lett. 13 (1992) 439. [11] R. Bez, E. Camerlenghi, D. Cantarelli, L. Ravazzi, G. Crisenza, Proc. 1EDM (1990) 99.