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Negative-gate to substrate erase transient simulation for flash memory
Microelectronic Engineering 84 (2007) 101–104 www.elsevier.com/locate/mee
Negative-gate to substrate erase transient simulation for flash memory S. Wolfson b
a,*
, Fat D. Ho
b
a Redstone Technical Test Center, Redstone Arsenal, AL 35898, USA University of Alabama in Huntsville, Department of Electrical and Computer Engineering, Huntsville, AL 35899, USA
Received 27 May 2006; accepted 21 August 2006 Available online 11 September 2006
Abstract We present a detailed and accurate physics based transient simulation for modeling flash memory erasing. Typical cells are erased by moving electrons from the floating gate to the drain, source or substrate. This paper addresses substrate erasing using a negative gate bias voltage based on the approximate solution to Poisson’s equation. Substrate erasing using a negative gate bias voltage is one of the more prevalent ways to erase flash memory in currently available consumer products. Many papers have been published on this topic but rarely present detailed derivations and none using this exact set of equations to model this erasing process. 2006 Published by Elsevier B.V. Keywords: Flash memory; Hot-carriers; MOS memory circuits; Semiconductor device models; Simulation
1. Introduction In today’s market there is an increasing need for floating gate (i.e. Flash) memory that provides faster program/erase characteristics, use less power, and require less area. Through accurate simulation the effects of device scaling, supply voltage levels, doping concentration, programming/erase pulse rise time, programming/erase pulse duration and programming/erase pulse magnitudes can be analyzed prior to fabrication. This can greatly reduce the required design time, design cost and time to market for products using this technology. In previous generations of floating gate memory such as the Electrically Erasable Programmable Read-Only Memory (EEPROM), the erase process was accomplished by moving the electrons stored on the floating gate to the drain (or source). This method required an extended overlap area, referred to as the tunnel region, above the drain (or source) which limited the ability to scale the device and/or proved to be inefficient if device size was reduced. A substrate erase method is now used and has proved to be efficient while not having the negative *
characteristics mention when erasing through the drain (source). The following sections detail the derivations of the equations, the simulation sequence, and results achieved. This simulation uses a modified method originally developed for modeling the drain erasing of an EEPROM [1] based upon the approximate solution to Poisson’s Equation. 2. Background The basis for a majority of floating gate models is the capacitive equivalent circuit which is shown in Fig. 1 and the cross-sectional view of a floating gate device which is shown in Fig. 2 [1]. From Figs. 1 and 2, the derivations of the floating gate charge (Qfg), initial floating gate voltage (Vfg), and gate current (Itun) equations are possible. For this model the contact potentials were incorporated to increased accuracy (i.e. V 0g , V 0d , V 0s , and V 0b represent the terminal voltages plus the corresponding contact potentials). Likewise, Vg, Vd, Vs, and Vb represent the terminal voltages only. Qfg ¼ C t V fg C oxg ðV 0g Þ C ox ðUsp þ V 0b Þ C fgd ðV 0d Þ
Corresponding author. Tel.: +1 256 876 8713; fax: +1 256 955 8837. E-mail address: [email protected] (S. Wolfson).
0167-9317/$ - see front matter 2006 Published by Elsevier B.V. doi:10.1016/j.mee.2006.08.008
C fgs ðV 0s Þ
ð1Þ
102
S. Wolfson, F.D. Ho / Microelectronic Engineering 84 (2007) 101–104
Taking the derivative with respect to time of Eq. (1) produces an equation for Itun. dQfg ¼ I tun dt dV fg dV g dUsp dV b C oxg C ox C ox ¼ Ct dt dt dt dt
ð3Þ
Eq. (3) provides the important relationship between the floating gate charge and floating gate voltage to the terminal voltages. The following section uses this equation and derives the equations used to predict the floating gate charge and floating gate voltage as well as the threshold voltage shift with respect to time. 3. Equation derivations Fig. 1. Schematic representation of the floating gate capacitor equivalent circuit.
The primary equation used to model the erase current Itun is the well known Fowler–Nordheim (FN) tunneling equation [2]. As presented in Eq. (4a) and (4b), the current Itun has a strong dependence on the tunnel oxide electric field (Etun) which is shown in Eq. (5). bE 2 ð4aÞ I tun ¼ aE Atun ðEtun Þ exp if Etun > 0 Etun bE 2 ð4bÞ I tun ¼ aE Atun ðEtun Þ exp if Etun < 0 jEtun j where the FN parameters aE = 1.82 · 107 A/V2 and bE = 1.88 · 108 V/cm; Etun ¼
Fig. 2. Cross-sectional representation of a n-channel floating-gate memory cell.
where Coxg(eox/tox1)WL is the control gate to floating gate capacitance, Cox(eox/tox)Atun is the floating gate to substrate capacitance, Cfgd(eox/tox) WLold is the floating gate to drain capacitance, Cfgs(eox/tox)WLols is the floating gate to source capacitance, Atun = W(L Lold Lols) is the tunnel area, Ct = Coxg + Cox + Cfgd + Cfgs is the total capacitance, eox is the permittivity of the gate oxide (3.45 · 1013 F/cm) tox, tox1 is the interpoly oxide and tunnel oxide thicknesses, respectively, Lold, Lols is the drain and source overlap lengths, respectively, Usp is the surface potential of the channel region and W, L–Cell width and length, respectively. The equation for the initial floating gate voltage is easily produced by rearranging the terms in Eq. (1) and solving for Vfg. 1 V fg ¼ ½Qfg þ C oxg ðV 0g Þ þ C ox ðUsp þ V 0b Þ Ct þ C fgd ðV 0d Þ þ C fgs ðV 0s Þ
ð2Þ
V fg Usp tox
ð5Þ
From Eq. (5) it is apparent that accurately determining the channel surface potential is required. This is accomplished by using the approximate solution to Poisson’s equation for a two terminal MOS structure. This equation can be found in [3] and is shown in Eq. (6). In this particular memory cell the two terminal MOS structure is comprised of the floating gate, tunnel oxide, and substrate. This differs from the method presented in [1] which uses the floating gate, tunnel oxide, and drain implant material as the two terminal MOS structure. sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi Usp 2Ufp V fg ¼ V FBp þ Usp þ cp Usp þ Ut exp ð6Þ Ut where 0
V FBp ¼ Ufp :56 Cq0o -Flat-band voltage. ox q0o – Interface charge per unit area (5 · 109 C/cm2). Ut – Thermal at room temperature (0.0259 V). voltage Ufp ¼pUffiffiffiffit ffiln NnAi – Fermi potential. 2qe N A
cp ¼ C0 s – Body effect coefficient. ox C 0ox ¼ etoxox – Oxide capacitance per unit area. es–Permittivity of silicon (1.04 · 1012 F/cm). q–Magnitude of electronic charge (1.6 · 1019 C). NA–Substrate doping concentration. ND–Drain and source doping concentration.
S. Wolfson, F.D. Ho / Microelectronic Engineering 84 (2007) 101–104
The derivative with respect to time of Eq. (6) produces the following equation: h i Usp 2Ufp dUsp Ut dV fg dUsp cp dt 1 þ exp rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ þ ð7Þ dt dt 2 U 2U Usp þ Ut exp sp Ut fp Substituting equation (7) into Eq. (3) and solving for produces Eq. (8). dUsp ¼ dt
I tun þ
dV C oxg dtg
C t C ox þ C t
cp 2
C ox dVdtb
þ Usp 2Ufp
1þexp Ut qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Usp þUt exp
103
8. Calculate Etun(t + 1) and Itun(t + 1). 9. Update Qfg(Qfg(t + 1) = Qfg(t) tstepItun). 10. Update threshold voltage Vt(Vt(t + 1) = Vti Qfg/ Coxg). 11. Update simulation time (t = t + tstep). 12. If t < tstop, go to step 5.
dUsp dt
5. Results ð8Þ
Usp 2Ufp Ut
Since Eq. (8) is of the form df(x)/dt=f(x), the Runge– Kutta method can be used to find Usp at the next time interval (i.e. Usp(t + 1)). Eq. (7) can also be substituted into Eq. (5) to produce Eq. (9). rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi U 2U V FBp þ cp Usp þ Ut exp sp Ut fp Umsp Etun ¼ ð9Þ tox The following two equations are used to determining the initial threshold voltage and initial floating gate charge. The initial threshold voltage (Vti) with respect to the control gate can be determined using Eq. (10). This represents the threshold voltage assuming Qfg = 0. pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! 2qN A es j 2Ufp þ V sb j Ct V ti ¼ V FBp 2Ufp þ C oxg C 0ox
The accuracy of this simulation was validated through comparison to previously published experimental data. Fig. 3 shows the simulation results using parameters given in [5]. Through visual inspection, it is apparent that this simulation provides a very accurate representation on the threshold voltage shift when compared to the data contained in [5]. Table 1 compares some of the Vth data points between this simulation and the data presented in [5] at several time intervals throughout the erase process. The simulation shows a maximum tunnel current (Itun) of 8.398 · 1011 (A) with a tunnel electric field (Etun) of 9.347 · 10+6 (V/cm). Similar accuracy is demonstrated when compared to experimental data presented in [6]. The result of this simulation is presented as Fig. 4. Table 2 compares some of the Vth data points between this simulation and the data presented in [6]. The simulation shows a maximum tunnel
ð10Þ If the programmed cell (i.e. starting) threshold voltage (Vt) is given, the following equation is used to determine the initial value for Qfg. Qfg ¼ C oxg ðV ti V t Þ
ð11Þ
4. Simulation steps This section outlines the simulation steps and equations used to model the erase process. The desired result of the erase process is to determine the threshold voltage shift as charge is removed from the floating gate at each time interval. 1. Enter device parameters (W, L, Lold, Lols, NA, tox, tox1), time intervals (tstart, tstop, tstep), and initial terminal voltages (Vg, Vd, Vs, Vb), final terminal voltages (Vgmin, Vbmax), erase pulse slew rates (dVg/dt and dVb/dt). 2. Calculate device parameters, capacitances and initial Vfg. 3. Calculate initial threshold voltage (Vti). 4. Determine initial floating gate charge (Qfg). 5. Use method presented in [4] to determine initial Usp. 6. Use Runge–Kutta to find Usp(t + 1). 7. Update terminal voltages.
Fig. 3. Results using device parameters from [5] – Simulation results; d results from [5] Vg = 12 V, Vb = 0–6 V.
Table 1 Tabular data extracted from Fig. 3 Time (s)
1 · 107
1 · 106
1 · 105
1 · 104
1 · 103
Vth from simulation (V) Vth from [5] (V)
6.999
6.992
6.352
4.374
2.004
6.96
6.75
5.70
3.85
2.20
104
S. Wolfson, F.D. Ho / Microelectronic Engineering 84 (2007) 101–104
These deviations can be attributed to the small errors produce when using the parallel plate capacitance equations. Follow on work will be conducted to incorporate capacitor models based upon the surface potential which should remove these inaccuracies. 6. Conclusion As advancements in Flash memory technology continue it is important to also make improvements in the simulations used in order to quickly and accurately modeling these devices. Models such as this must continually be modified and upgraded to meet the ever-changing requirements. The method presented in this paper has been validated down to memory cells with channel lengths of 130 nm. Fig. 4. Results using device parameters from [6] simulation results; d results from [6] Vg = 8 V, Vb = 0–10 V.
Acknowledgement None.
Table 2 Tabular data extracted from Fig. 4 Time (s)
1 · 107
1 · 106
1 · 105
1 · 104
1 · 103
Vth from simulation (V) Vth from [6] (V)
3.499
3.499
3.244
2.045
0.243
3.50
3.50
3.00
1.25
0.25
current (Itun) of 6.765 · 1012 (A) with a tunnel electric field (Etun) of 9.026 · 10+6 (V/cm). Through visual it is apparent that there are deviations between the experimental data and the simulation results.
References [1] Y. Dan, R. Axley, F. Ho, Int. J. Electron. 84 (6) (1998) 561–581. [2] M. Lenxlinger, E. Snow, J. Appl. Phys. 40 (1969) 278–283. [3] Y. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill, Inc., 1987. [4] T. Claudio, M. Guido, IEEE Trans. CAD CAD-3 (2) (1984) 117–122. April. [5] S. Chung, C. Yih, H. Chen, G. Hong, IEEE IEDM 99–179 (1999) 7.7.1–7.7.4. [6] W. Lee, D. Lee, Y. Na, K. Kim, K. Ahn, K. Suh, Y. Roh, IEEE Electron. Dev. Lett. 23 (8) (2002) 476–478.
Negative-gate to substrate erase transient simulation for flash memory S. Wolfson b
a,*
, Fat D. Ho
b
a Redstone Technical Test Center, Redstone Arsenal, AL 35898, USA University of Alabama in Huntsville, Department of Electrical and Computer Engineering, Huntsville, AL 35899, USA
Received 27 May 2006; accepted 21 August 2006 Available online 11 September 2006
Abstract We present a detailed and accurate physics based transient simulation for modeling flash memory erasing. Typical cells are erased by moving electrons from the floating gate to the drain, source or substrate. This paper addresses substrate erasing using a negative gate bias voltage based on the approximate solution to Poisson’s equation. Substrate erasing using a negative gate bias voltage is one of the more prevalent ways to erase flash memory in currently available consumer products. Many papers have been published on this topic but rarely present detailed derivations and none using this exact set of equations to model this erasing process. 2006 Published by Elsevier B.V. Keywords: Flash memory; Hot-carriers; MOS memory circuits; Semiconductor device models; Simulation
1. Introduction In today’s market there is an increasing need for floating gate (i.e. Flash) memory that provides faster program/erase characteristics, use less power, and require less area. Through accurate simulation the effects of device scaling, supply voltage levels, doping concentration, programming/erase pulse rise time, programming/erase pulse duration and programming/erase pulse magnitudes can be analyzed prior to fabrication. This can greatly reduce the required design time, design cost and time to market for products using this technology. In previous generations of floating gate memory such as the Electrically Erasable Programmable Read-Only Memory (EEPROM), the erase process was accomplished by moving the electrons stored on the floating gate to the drain (or source). This method required an extended overlap area, referred to as the tunnel region, above the drain (or source) which limited the ability to scale the device and/or proved to be inefficient if device size was reduced. A substrate erase method is now used and has proved to be efficient while not having the negative *
characteristics mention when erasing through the drain (source). The following sections detail the derivations of the equations, the simulation sequence, and results achieved. This simulation uses a modified method originally developed for modeling the drain erasing of an EEPROM [1] based upon the approximate solution to Poisson’s Equation. 2. Background The basis for a majority of floating gate models is the capacitive equivalent circuit which is shown in Fig. 1 and the cross-sectional view of a floating gate device which is shown in Fig. 2 [1]. From Figs. 1 and 2, the derivations of the floating gate charge (Qfg), initial floating gate voltage (Vfg), and gate current (Itun) equations are possible. For this model the contact potentials were incorporated to increased accuracy (i.e. V 0g , V 0d , V 0s , and V 0b represent the terminal voltages plus the corresponding contact potentials). Likewise, Vg, Vd, Vs, and Vb represent the terminal voltages only. Qfg ¼ C t V fg C oxg ðV 0g Þ C ox ðUsp þ V 0b Þ C fgd ðV 0d Þ
Corresponding author. Tel.: +1 256 876 8713; fax: +1 256 955 8837. E-mail address: [email protected] (S. Wolfson).
0167-9317/$ - see front matter 2006 Published by Elsevier B.V. doi:10.1016/j.mee.2006.08.008
C fgs ðV 0s Þ
ð1Þ
102
S. Wolfson, F.D. Ho / Microelectronic Engineering 84 (2007) 101–104
Taking the derivative with respect to time of Eq. (1) produces an equation for Itun. dQfg ¼ I tun dt dV fg dV g dUsp dV b C oxg C ox C ox ¼ Ct dt dt dt dt
ð3Þ
Eq. (3) provides the important relationship between the floating gate charge and floating gate voltage to the terminal voltages. The following section uses this equation and derives the equations used to predict the floating gate charge and floating gate voltage as well as the threshold voltage shift with respect to time. 3. Equation derivations Fig. 1. Schematic representation of the floating gate capacitor equivalent circuit.
The primary equation used to model the erase current Itun is the well known Fowler–Nordheim (FN) tunneling equation [2]. As presented in Eq. (4a) and (4b), the current Itun has a strong dependence on the tunnel oxide electric field (Etun) which is shown in Eq. (5). bE 2 ð4aÞ I tun ¼ aE Atun ðEtun Þ exp if Etun > 0 Etun bE 2 ð4bÞ I tun ¼ aE Atun ðEtun Þ exp if Etun < 0 jEtun j where the FN parameters aE = 1.82 · 107 A/V2 and bE = 1.88 · 108 V/cm; Etun ¼
Fig. 2. Cross-sectional representation of a n-channel floating-gate memory cell.
where Coxg(eox/tox1)WL is the control gate to floating gate capacitance, Cox(eox/tox)Atun is the floating gate to substrate capacitance, Cfgd(eox/tox) WLold is the floating gate to drain capacitance, Cfgs(eox/tox)WLols is the floating gate to source capacitance, Atun = W(L Lold Lols) is the tunnel area, Ct = Coxg + Cox + Cfgd + Cfgs is the total capacitance, eox is the permittivity of the gate oxide (3.45 · 1013 F/cm) tox, tox1 is the interpoly oxide and tunnel oxide thicknesses, respectively, Lold, Lols is the drain and source overlap lengths, respectively, Usp is the surface potential of the channel region and W, L–Cell width and length, respectively. The equation for the initial floating gate voltage is easily produced by rearranging the terms in Eq. (1) and solving for Vfg. 1 V fg ¼ ½Qfg þ C oxg ðV 0g Þ þ C ox ðUsp þ V 0b Þ Ct þ C fgd ðV 0d Þ þ C fgs ðV 0s Þ
ð2Þ
V fg Usp tox
ð5Þ
From Eq. (5) it is apparent that accurately determining the channel surface potential is required. This is accomplished by using the approximate solution to Poisson’s equation for a two terminal MOS structure. This equation can be found in [3] and is shown in Eq. (6). In this particular memory cell the two terminal MOS structure is comprised of the floating gate, tunnel oxide, and substrate. This differs from the method presented in [1] which uses the floating gate, tunnel oxide, and drain implant material as the two terminal MOS structure. sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi Usp 2Ufp V fg ¼ V FBp þ Usp þ cp Usp þ Ut exp ð6Þ Ut where 0
V FBp ¼ Ufp :56 Cq0o -Flat-band voltage. ox q0o – Interface charge per unit area (5 · 109 C/cm2). Ut – Thermal at room temperature (0.0259 V). voltage Ufp ¼pUffiffiffiffit ffiln NnAi – Fermi potential. 2qe N A
cp ¼ C0 s – Body effect coefficient. ox C 0ox ¼ etoxox – Oxide capacitance per unit area. es–Permittivity of silicon (1.04 · 1012 F/cm). q–Magnitude of electronic charge (1.6 · 1019 C). NA–Substrate doping concentration. ND–Drain and source doping concentration.
S. Wolfson, F.D. Ho / Microelectronic Engineering 84 (2007) 101–104
The derivative with respect to time of Eq. (6) produces the following equation: h i Usp 2Ufp dUsp Ut dV fg dUsp cp dt 1 þ exp rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ þ ð7Þ dt dt 2 U 2U Usp þ Ut exp sp Ut fp Substituting equation (7) into Eq. (3) and solving for produces Eq. (8). dUsp ¼ dt
I tun þ
dV C oxg dtg
C t C ox þ C t
cp 2
C ox dVdtb
þ Usp 2Ufp
1þexp Ut qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Usp þUt exp
103
8. Calculate Etun(t + 1) and Itun(t + 1). 9. Update Qfg(Qfg(t + 1) = Qfg(t) tstepItun). 10. Update threshold voltage Vt(Vt(t + 1) = Vti Qfg/ Coxg). 11. Update simulation time (t = t + tstep). 12. If t < tstop, go to step 5.
dUsp dt
5. Results ð8Þ
Usp 2Ufp Ut
Since Eq. (8) is of the form df(x)/dt=f(x), the Runge– Kutta method can be used to find Usp at the next time interval (i.e. Usp(t + 1)). Eq. (7) can also be substituted into Eq. (5) to produce Eq. (9). rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi U 2U V FBp þ cp Usp þ Ut exp sp Ut fp Umsp Etun ¼ ð9Þ tox The following two equations are used to determining the initial threshold voltage and initial floating gate charge. The initial threshold voltage (Vti) with respect to the control gate can be determined using Eq. (10). This represents the threshold voltage assuming Qfg = 0. pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! 2qN A es j 2Ufp þ V sb j Ct V ti ¼ V FBp 2Ufp þ C oxg C 0ox
The accuracy of this simulation was validated through comparison to previously published experimental data. Fig. 3 shows the simulation results using parameters given in [5]. Through visual inspection, it is apparent that this simulation provides a very accurate representation on the threshold voltage shift when compared to the data contained in [5]. Table 1 compares some of the Vth data points between this simulation and the data presented in [5] at several time intervals throughout the erase process. The simulation shows a maximum tunnel current (Itun) of 8.398 · 1011 (A) with a tunnel electric field (Etun) of 9.347 · 10+6 (V/cm). Similar accuracy is demonstrated when compared to experimental data presented in [6]. The result of this simulation is presented as Fig. 4. Table 2 compares some of the Vth data points between this simulation and the data presented in [6]. The simulation shows a maximum tunnel
ð10Þ If the programmed cell (i.e. starting) threshold voltage (Vt) is given, the following equation is used to determine the initial value for Qfg. Qfg ¼ C oxg ðV ti V t Þ
ð11Þ
4. Simulation steps This section outlines the simulation steps and equations used to model the erase process. The desired result of the erase process is to determine the threshold voltage shift as charge is removed from the floating gate at each time interval. 1. Enter device parameters (W, L, Lold, Lols, NA, tox, tox1), time intervals (tstart, tstop, tstep), and initial terminal voltages (Vg, Vd, Vs, Vb), final terminal voltages (Vgmin, Vbmax), erase pulse slew rates (dVg/dt and dVb/dt). 2. Calculate device parameters, capacitances and initial Vfg. 3. Calculate initial threshold voltage (Vti). 4. Determine initial floating gate charge (Qfg). 5. Use method presented in [4] to determine initial Usp. 6. Use Runge–Kutta to find Usp(t + 1). 7. Update terminal voltages.
Fig. 3. Results using device parameters from [5] – Simulation results; d results from [5] Vg = 12 V, Vb = 0–6 V.
Table 1 Tabular data extracted from Fig. 3 Time (s)
1 · 107
1 · 106
1 · 105
1 · 104
1 · 103
Vth from simulation (V) Vth from [5] (V)
6.999
6.992
6.352
4.374
2.004
6.96
6.75
5.70
3.85
2.20
104
S. Wolfson, F.D. Ho / Microelectronic Engineering 84 (2007) 101–104
These deviations can be attributed to the small errors produce when using the parallel plate capacitance equations. Follow on work will be conducted to incorporate capacitor models based upon the surface potential which should remove these inaccuracies. 6. Conclusion As advancements in Flash memory technology continue it is important to also make improvements in the simulations used in order to quickly and accurately modeling these devices. Models such as this must continually be modified and upgraded to meet the ever-changing requirements. The method presented in this paper has been validated down to memory cells with channel lengths of 130 nm. Fig. 4. Results using device parameters from [6] simulation results; d results from [6] Vg = 8 V, Vb = 0–10 V.
Acknowledgement None.
Table 2 Tabular data extracted from Fig. 4 Time (s)
1 · 107
1 · 106
1 · 105
1 · 104
1 · 103
Vth from simulation (V) Vth from [6] (V)
3.499
3.499
3.244
2.045
0.243
3.50
3.50
3.00
1.25
0.25
current (Itun) of 6.765 · 1012 (A) with a tunnel electric field (Etun) of 9.026 · 10+6 (V/cm). Through visual it is apparent that there are deviations between the experimental data and the simulation results.
References [1] Y. Dan, R. Axley, F. Ho, Int. J. Electron. 84 (6) (1998) 561–581. [2] M. Lenxlinger, E. Snow, J. Appl. Phys. 40 (1969) 278–283. [3] Y. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill, Inc., 1987. [4] T. Claudio, M. Guido, IEEE Trans. CAD CAD-3 (2) (1984) 117–122. April. [5] S. Chung, C. Yih, H. Chen, G. Hong, IEEE IEDM 99–179 (1999) 7.7.1–7.7.4. [6] W. Lee, D. Lee, Y. Na, K. Kim, K. Ahn, K. Suh, Y. Roh, IEEE Electron. Dev. Lett. 23 (8) (2002) 476–478.