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A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS NAND flash application
Available online at www.sciencedirect.com
Solid-State Electronics 51 (2007) 1523–1528 www.elsevier.com/locate/sse
A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS NAND flash application Tzu-Hsuan Hsu a,b,*, Ya Chin King b, Jau-Yi Wu a, Yen Hao Shih a, Hang Ting Lue a, Erh-Kun Lai a, Kuang-Yeu Hsieh a, Rich Liu a, Chih-Yuan Lu a a b
Emerging Central Lab, Macronix International Co., Ltd., Park, Hsinchu 300, Taiwan, ROC Department of Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan, ROC
The review of this paper was arranged by Adrian M. Ionescu and Yusuf Leblebici
Abstract A novel channel-program and erase method is presented to replace the FN tunneling operation for SONOS cells in NAND architecture for the first time [Hsu TH, Wu JY, King YC, Lue HT, Shih YH, Lai EK, et al. A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS memory application. In: Tech digest 2006 European solid-state device research conference (ESSDERC); 2006. p. 222–5], [1]. The proposed operation utilizes substrate transient hot electron (STHE) injection and substrate transient hot-hole (STHH) injection for programming and erasing, respectively. Gate bias polarity serves to control whether hot electrons or hot holes are injected into the nitride storage layer. More efficient program and erase operations are achieved compared to the conventional Fowler–Nordheim (FN) tunneling method. The new technique operates at lower programming voltages and with shorter duration pulses, thus increases the programming throughput. Moreover, good program/erase disturb immunity, cycling endurance and data retention are demonstrated. Ó 2007 Elsevier Ltd. All rights reserved. Keywords: FN; STHH; STHE; SONOS; NAND; Memory
1. Introduction Nitride-based charge trapping flash memory device has become an important candidate for next generation flash memories because it has a simple structure that is perfectly compatible with CMOS fabrication process, has no erratic bits, no drain turn on and no storage node coupling issues. Its superior scaling capability is also suitable for high-density stand alone or embedded memory applications [2–8]. However, traditional SONOS memory with thin tunneling oxide (<30 A) [9] is prone to channel hole direct tunneling * Corresponding author. Address: Department of Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan, ROC. Tel.: +886 3 5786688x78017; fax: +886 3 5789087. E-mail address: [email protected] (T.-H. Hsu).
0038-1101/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2007.09.032
that causes poor data retention as shown in Fig. 1a. A thicker bottom oxide is desirable for better data retention. However, the thick bottom oxide leads to extremely low FN tunneling rate for NAND-type SONOS cells [10]. As illustrated in Fig. 1b, hole cannot inject into storage layer for erasing even at more than 10 MV/cm electrical field. A ‘‘hot carrier’’ injection scheme applicable to a NANDtype array is thus desirable for SONOS NAND flash memories. Several hot carrier injection schemes have been published for SONOS cells but unfortunately they cannot be applied to NAND architectures [11,12]. This is because programmed selection is hard to implement on conventional NAND array. In this paper, we propose a novel substrate transient hot electron (STHE) and substrate transient hot-hole (STHH) operation for the SONOS NAND array. The efficient
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program and erase performance is achieved by proper body and gate biasing conditions as well as the transient collecting time.
TOX VS=0V SiN BOX
VD=1V
Source
The samples are fabricated by standard CMOS technology with channel length and channel width of 0.14 and 0.1 lm, respectively. The samples are n-channel MOSFETs with an oxide/silicon–nitride/oxide (ONO) gate dielectric stack layer. The ONO thickness from bottom to top layers is 5.4 nm, 7 nm and 9 nm, respectively. The intrinsic junction breakdown (VBD) of this cell is 6 V. Fig. 2 shows the schematics of STHE program and STHH erase operational principles. The STHE and STHH are both performed by applying body bias, Vb, of 9 V, grounding the gate and floating the source and drain. Fig. 2a shows the diagram of substrate hot carrier generation and the injection sequence. With a high positive body bias, the forward biased S/D junctions are charged to Vb minus the built-in potential [12] as step 1. Once the body bias is removed, the S/D junctions are switched to reverse bias. The significant reverse bias causes a fast discharge and hot carriers are then generated by the transient avalanche junction breakdown as step 2. Afterward, the hot carrier can be extracted with different Vg bias voltages. For the programming scheme in Fig. 2b, positive Vg bias is utilized to efficiently collect hot electrons. On the contrary, negative Vg bias is applied for erasing operation, when hot hole is collected in the nitride layer. Contrary to previous studies [11,12], we demonstrate in this work that not only hot holes but also hot electrons can be injected with proper switching of Vg bias polarity. This is a strong evidence that electron and hole sources come from substrate hot carrier in our device, rather than from FN tunneling current. The Vb bias duration (Tb) and Vg bias duration, or the collecting time, (Tgc) are two important parameters that determine the charge injection efficiency. Very short Vb bias duration (Tb = 0.5 ls) is sufficient for hot carrier generation. This is because hot carriers can be
VG= -18V
VG=5V TOX VS=0V SiN BOX
2. Experimental
VD=0V
Source
Drain
Drain
P-sub
P-sub
(a)
(b)
Fig. 1. (a) Schematic illustration of the poor data retention caused by electrons leaking to the substrate for SONOS cells with very thin tunnel oxide (<30 A). (b) SONOS cells with thicker tunnel oxide (>50 A) provides better data retention. However, hole injection rate to the storage layer is very low even at 10 MV/cm E- field.
Start discharging
(b)
VG
Tox
90A
SiN
70A
Box
54A
n+
2 2
VD/VS
Gate
S
1 1
7
D
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n+
2 P-w
Hold Charge Collect
Vg 0 Tgc
(c)
1
VD/VS
S/D: floating VB 0
Hold Charge Collect
Vg -7
(a)
7
Τb
Vb 0
Tgc
Fig. 2. (a) Schematic illustration of the substrate transient hot carrier injection in SONOS cell. (b) The pulsing sequence of substrate transient hot electron (STHE) injection for programming operation. (c) The pulsing sequence of substrate transient hot-hole (STHH) injection for erasing operation.
a
Tgc=10μs, Tb=0.5μs
4.5
b
10-5 STHE-Program STHH-Erase
4.0
10-6
3.5
10-7 STHE-Program
3.0
I D (A)
Vt (V)
Vg= 9, Vb=9V ( STHE ) Vg=-9, Vb=9V ( STHH )
STHH-Erase
10-8
2.5
10-9
2.0
10
-10
10-11
1.5 0
2
4
6
8
10
12
# Program/Erase shot
14
16
18
0
1
2
3
4
5
VG (V)
Fig. 3. (a) Programming and erasing characteristics at various Vg bias (9 V/9 V), with Tgc = 10 ls and Tb = 0.5 ls. (b) The IV curves of substrate transient hot electron injection (open symbol) and substrate transient hot-hole injection (solid symbol). Parallel IV curve shift indicates uniform channel injections.
T.-H. Hsu et al. / Solid-State Electronics 51 (2007) 1523–1528
a
5
6
4
5
3
Tgc=0.1us Tgc=2us Tgc=10us Tgc=50us Tgc=100us Tgc=200us Tgc=500us Tgc=1ms Tgc=10ms
4
3
2
1
Vt (V)
Vt (V)
b
W/L=0.1/0.14μm,Vg=9V,Vb=9V, Tb=0.5μs (STHE)
7
1525
W/L=0.1/0.14mm,Vg=-9V,Vb=9V, Tb=0.5μs (STHH)
Tgc=0.1us Tgc=2us Tgc=10us Tgc=50us Tgc=100us Tgc=200us Tgc=500us Tgc=1ms Tgc=10ms
2
1
0
-1 0
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22
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# Program shot
6
8
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# Erase shot
Fig. 4. The operation speed of STHE (a) and STHH (b) injection is strongly related to transient collecting time (Tgc). Longer Tgc enhances the hot carrier collection in the storage layer.
efficiently collected during Vg bias time; hence, the Vb bias duration can be shortened to significantly reduce the power consumption. The low operation voltage in the proposed programming scheme can further save charge pumping overhead and simplify circuit design compared to conventional FN tunneling program and erase operation used in NAND arrays. 3. Results and discussions Fig. 3 shows the Vt shift and the I–V curve during STHE programming and STHH erasing operations. Different Vg bias levels were adopted for programming and erasing, respectively, while all other parameters remain constant (Vb = 9 V, Tgc = 10 ls and Tb = 0.5 ls). The I–V curves shift parallelly, suggesting that the channel is uniformly programmed and erased [13]. This is somewhat counter intuitive, since substrate transient hot carriers are gener-
ated near source and drain junctions [12]. This is probably due to that the substrate avalanche hot carriers have a wider spread and in a short channel device the local charge trapping regions merge into a continuous trapping layer. The speed of STHE and STHH injection depends strongly on the collecting time, as shown in Fig. 4. A longer collection pulse extracts more hot electrons/holes into the storage layer. By designing a proper collecting period (Tgc), substrate bias duration (Tb) can be shortened to achieve more efficient program and erase operation. The STHE program operations with different Vg/Vb bias conditions are compared in Fig. 5. The programming speed is increased by applying higher Vg and Vb biases. Programming speed of 200 ls for DVt = 2 V is achieved with Vg = 9 V and Vb = 9 V. As shown in Fig. 6, STHH erase efficiency is demonstrated at different Vg/Vb bias conditions. The erase speed is also increased with higher Vg and Vb biases. Erasing
7
5
Tgc=50μs, Tb=0.5μs (STHE) 6
4
Vg=3V,Vb=9V Vg=5V,Vb=9V Vg=7V,Vb=9V Vg=9V,Vb=9V Vg=9V,Vb=7V Vg=9V,Vb=5V Vg=9V,Vb=3V
4
3
Vt (V)
5
Vt (V)
Tgc=50μs, Tb=0.5μs (STHH)
Vg= -3V,Vb=9V Vg= -5V,Vb=9V Vg= -7V,Vb=9V Vg= -9V,Vb=9V Vg= -9V,Vb=7V Vg= -9V,Vb=5V
2
3 1
2
1
0
10-7
10-6
10-5
10-4
10-3
Program time (s)
Fig. 5. The program characteristics of the STHE method with different gate voltage and body voltage. Both gate and body bias can be used to modulate the programming efficiency. Programming time of 200 ls for DVt = 2 V is demonstrated with Vg = 9 V and Vb = 9 V.
10-7
10-6
10-5
10-4
10-3
Erase time (s)
Fig. 6. The erase characteristics of the STHH method under different gate voltage and body voltage conditions. Both gate and body bias can be used to modulate the erase efficiency. Erasing time of 350 ls for DVt = 2 V is obtained with Vg = 9 V and Vb = 9 V.
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a
4.5
b 10
-4
W/ L= 0.1 / 0.14 μm
10-5
4.0 10-6
Vg= 9V, Vb=9V, Tgc=100μs, Tb=0.5μs, STHE Program
Erased state (EV)
3.0
Programmed state (PV)
200 mV/dec
184 mV/dec
257 mV/dec
10-7
ID (A)
Vt (V)
3.5
10-8
EV(Initial) PV(Initial) EV(P/E=1) PV(P/E=1) EV(P/E=100) PV(P/E=100) EV(P/E=1K) PV(P/E=1K) EV(P/E=10K) PV(P/E=10K)
260 mV/dec
-9
10
2.5
Vg= -9V, Vb=9V, Tgc=100ms, Tb=0.5ms, STHH Erase 2.0
10-10 10-11 10-12
1.5 100
Initial
101
102
103
104
-1
0
1
2
# P/E Cycle
3
4
5
6
VG ( V )
Fig. 7. (a) 10 K cycling endurance performed by STHE program and STHH erase operations. (b) IV of programmed and erased states. After P/E cycling, the sub-threshold slopes are moderately degraded indicating some interface damage by hot holes.
speed of 350 ls for DVt = 2 V is obtained with Vg = 9 V and Vb = 9 V. It is clear from Figs. 5 and 6 that body bias is more sensitive for substrate transient hot carrier injection for both programming and erasing operations. For example, the cells can be programmed or erased only when body bias is higher than 7 V. This is also a proof that the hot carrier source comes from junction breakdown, since junction breakdown voltage (VBD) of this device is around 6 V. Once S/D junction potential is raised to a level >VBD, transient hot carriers are generated and programming and erasing achieved with moderate gate bias. In addition, the programming efficiency is higher than the erasing efficiency. This is because holes encounter a much higher barrier height (4.4 eV) than electrons. In summary, both program and erase speeds are much higher than FN tunneling for SONOS devices. Fig. 7a shows the cycling endurance of STHE program and STHH erase with an operation window of 2 V. Good endurance up to 10 K cycles is demonstrated. However, after 10 K cycling, the sub-threshold swing of programmed and erased state are moderately degraded as shown in
Fig. 7b, due to interface damage induced by hot holes. This is testified by the increase of charge pumping current (Icp) from cycled device. Fig. 8 shows that less than 5E11 cm2 eV1 Dit generate after 10K cycling which is superior than other hot hole erased nitride-trapped memories [14]. In addition, the moderate interface degradation mirrored in better retention characteristics shown in Fig. 10. It is believed that short discharge time of this novel scheme help to ease off interface damage. Fig. 9 illustrates the read disturbance under different cycling times. Excellent read disturb immunity is observed with >1000 s stress endurance for post 10 K-cycled cells. After 150 °C, >2 days baking test, no charge loss and charge gain is observed, as shown in Fig. 10. This is an inherent merit of nitride-trapped memory – it is immune to local damage and pinhole caused retention issues even after cycling stressing. This novel programming and erasing scheme can be implemented on a modified NAND structure with divided substrate bit line (DSB–NAND), for which the substrate is isolated by STI and each BL is connected to the corre-
10x10-12
3.0 P/E=1 P/E=100 P/E=1K P/E=10K
Vg= 5V, Vd= 1.0V 2.5
6x10-12
2.0
ΔVt (V)
Icp (A)
8x10-12
4x10-12
1.5
P/E= 1 P/E= 1K P/E= 10K
1.0
2x10-12
0.5 0 -2
-1
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7
VG (V )
Fig. 8. Charge pumping current (500 kHz) using stepping high pulses for cycled device.
0.0 Initial
1
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100
1000
Stress time (s)
Fig. 9. Read disturbance of STHE–STHH as a function of P/E cycling.
T.-H. Hsu et al. / Solid-State Electronics 51 (2007) 1523–1528
sponding divided substrate. Fig. 11a illustrates the proposed programming conditions in the DSB–NAND array architecture. A positive voltage of 9 V is applied to the selected WL and the unselected WL’s are grounded. BL voltages of 9 V and 0 V are applied on the selected cells and the unselected cells, respectively. Since the BL is connected to the substrate, the BL voltage can modulate the well potential of the DSB–NAND string with the turn on GSL transistor. The erase scheme is demonstrated in Fig. 11b. A positive bias of 9 V is applied on selected BL’s to charge the well potential. At this time, a negative voltage is applied to the selected WL to induce hot-hole injection. Since the erase operation is similar to the program operation except for the polarity of the gate voltage, random erase operation can be achieved. Consequently, random program and random erase can be realized with the STHE–STHH operation schemes, so that SONOS DSB–NAND arrays can be extended for both data and code Flash applications. Program and erase disturb immunity is demonstrated in Fig. 12. When programming, the neighboring cells A and B only experience bias on substrate and gate electrode, respectively, as shown in Fig. 12a. In the same way, in Fig. 12b, the applied bias only goes to substrate and gate for erasing on cells C and D. Therefore, the conditions for generating hot electron or hole are not met for the neighboring cells. This also eliminates the need for the conventional self-boosting scheme. This is very helpful to ease the peripheral loading and design complexity. The read operation is shown in Fig. 13. First, turn on the select transistors (GSL, SSL), then apply read voltage on selected WL and ground selected bit line while turn on all pass gate transistors and the source line. The sensing scheme is almost the same as conventional NAND method. Fig. 14 demonstrates the read current of a 16-string NAND array. The read current can be enhanced by increasing the Vpass voltage. For Vpass = 5 V and Vread = 1 V, the read current is larger than 3 lA.
5.0
W/L = 0.1 / 0.14μm, 150oC baking test 4.5 4.0
Vt (V)
3.5 3.0
Programmed state Erased state
2.5 2.0 1.5 1.0
Initial 100
101
102
103
104
105
106
107
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109
10 Year
Baking time (s)
Fig. 10. Good data retention can be maintained after 150 °C, 2 days baking test.
BL3=9V BL2=9V BL1=0V
BL3=9V BL2=9V BL1=0V GSL=11V
GSL=11V
WL1=0V
WL1=0V
WL2=9V
WL2= -9V
WL3=0V
WL3=0V
SSL=Off
SSL=Off
SL=Floating
SL=Floating
(b)
(a)
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Fig. 11. (a) Substrate transient hot electron (STHE) injection for programming operation can be implemented on NAND structure with divided substrate bit line (DSB–NAND). A positive voltage is applied to selected WL and BLs with pass gates and the unselected BLs are grounded. (b) Substrate transient hot-hole (STHH) injection for erasing operation can also be implemented on DSB–NAND. A negative voltage is applied to the selected WL with positive voltage to the selected BLs with pass gates while the unselected BLs are grounded.
(a) 0V
0V 9V
0V
4.5
GSL=11V
A B
WL1=0V
4.0
WL2= 9V
3.5
0V
SSL=Off SL=Floating
0V 9V
Vt (V)
WL3=0V
(b)
Neighbor cell Program / Erase disturb
Cell A/C disturb Cell B ( EVstate ), program disturb Cell D ( EVstate ), erase disturb Cell B ( PVstate ), program disturb Cell D ( PVstate ), erase disturb
3.0
0V
C D
GSL=11V
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WL1=0V
2.0
WL2= -9V WL3=0V SSL=Off SL=Floating
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1
10
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1000
Stress time (s)
(c)
Fig. 12. Good program and erase disturb immunity is demonstrated. Hence, complex self-boosting scheme is not required.
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operations are proposed for SONOS NAND memory applications. The fundamental limitations of high voltage operation and low tunneling efficiency are overcome by the proposed operational scheme. Excellent cycling endurance and data retention are demonstrated. Moreover, using a DSB–NAND structure both random bit program and random bit erase can be implemented for both data and code Flash memory applications.
BL=1V BL=1V BL=0V BL=1V GSL=7V WL1=Vpass WL2=Vread WL3=Vpass SSL=7V SL=1V
Fig. 13. To read, turn on select transistors (GSL, SSL) and apply read voltage on selected WL and SL. Sensing scheme is the same as conventional NAND.
8x10-6
Vpass= Vpass= Vpass= Vpass= Vpass= Vpass=
7x10-6 6x10-6
16- WLs string Vread= 1V EV= 1V
3V 4V 5V 6V 7V 8V
I D (A)
4x10-6 3x10-6 2x10-6 1x10-6 0
1
2
3
4
5
6
VG (V)
Fig. 14. The read current can be enhanced by increasing Vpass voltage. For Vpass = 5 V, and Vread = 1 V, the read current for a 16-string NAND array is larger than 3 lA.
Table 1 Performance comparison of DSB–NAND and standard NAND structure Structure
DSB–NAND STD–NAND
Performance Page program
Page read
p p
p p
Authors would like to thank technology development center of Macronix International Co. for the support of device fabrication and characterization. References
5x10-6
0
Acknowledgements
Good program inhibit p p
Small cell size p p
Random bit P/E p
Supply voltage < 10 V p
Table 1 briefly lists the comparison between standard NAND array and DSB NAND of this work. They all can perform page program, page read, with good program inhibition and small cell size. However, DSB NAND provides random bit program and erase and low voltage operation that are superior to traditional NAND Flash. A total solution that provides both NOR and NAND function is possible with the STHE–STHH operation. 4. Conclusion Novel substrate transient hot electron (STHE) programming and substrate transient hot-hole (STHH) erasing
[1] Hsu TH, Wu JY, King YC, Lue HT, Shih YH, Lai EK, et al. A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS memory application. In: Tech digest 2006 European solid-state device research conference (ESSDERC); 2006. p. 222–5. [2] Eitan B et al. NROM: a novel localized trapping, 2 bit non-volatile memory cell. IEEE Electron Dev Lett 2000;21:543–5. [3] Eitan B. 4-bit per cell NROM reliability. In IEDM Tech Digest; 2005. p. 547–50. [4] Hsu TH et al. Investigation of maximum current sensing window for two-side operation, 4-bit/cell MLC nitride-trapping non-volatile flash memories. IEEE Electron Dev Lett 2004;25:795–7. [5] Kim Kinam, Choi Jungdal. Future outlook of NAND flash technology for 40 nm node and beyond. IEEE NVSMW Tech Dig 2006:9–11. [6] Lue HT, Wang SY, Lai EK, Shih YH, Lai SC, Yang LW, et al. BE– SONOS: a bandgap engineered SONOS with excellent performance and reliability. In: Tech digest 2005 international electron devices meeting; 2005. p. 547–50. [7] Lue HT, Shih YH, Hsieh KY, Liu R, Lu CY. Novel soft erase and refill methods for a P+-poly gate nitride-trapping non-volatile memory device with excellent endurance and retention properties. In: Proceedings of the international reliability physics symposium (IRPS), session 2D-3; 2005. p. 168–74. [8] Kim K. Technology for sub-50 nm DRAM and NAND flash manufacturing. In: IEDM Tech. digest, session 13-5; 2005. p. 323–6. [9] Wang Yu, White MH. An analytical retention model for SONOS non-volatile memory devices in the excess electron state. In: Semiconductor device research symposium, 2003 international, 10–12 December; 2003. p. 156–7. [10] Shih Yen Hao et al. A novel 2-bit/cell nitride storage flash memory with greater than 1M P/E-cycle endurance. IEEE IEDM Tech Dig; 2004. p. 881–4. [11] Sim Jae Sung et al. BAVI-cell: a novel high-speed 50 nm SONOS memory with band-to-band tunneling initiated avalanche injection mechanism. In: VLSI Tech digest; 2005. p. 122–3. [12] Cho MK, Kim DM. Simultaneous hot-hole injection at drain and source for efficient erase and excellent endurance in SONOS flash EEPROM cells. IEEE Electron Dev Lett 2003;24:260–2. [13] Li C-NB, et al. A novel uniform channel-program erase (UCPE) flash EEPROM using an isolated P-well structure. In: IEEE IEDM Tech Digest; 2000. p. 779–82. [14] Shih Yen Hao et al. Highly reliable 2-bit/cell nitride-trapping flash memory using a novel array-nitride-sealing (ANS) ONO process. In: IEEE IEDM Tech Digest; 2005. p. 559–62.
Solid-State Electronics 51 (2007) 1523–1528 www.elsevier.com/locate/sse
A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS NAND flash application Tzu-Hsuan Hsu a,b,*, Ya Chin King b, Jau-Yi Wu a, Yen Hao Shih a, Hang Ting Lue a, Erh-Kun Lai a, Kuang-Yeu Hsieh a, Rich Liu a, Chih-Yuan Lu a a b
Emerging Central Lab, Macronix International Co., Ltd., Park, Hsinchu 300, Taiwan, ROC Department of Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan, ROC
The review of this paper was arranged by Adrian M. Ionescu and Yusuf Leblebici
Abstract A novel channel-program and erase method is presented to replace the FN tunneling operation for SONOS cells in NAND architecture for the first time [Hsu TH, Wu JY, King YC, Lue HT, Shih YH, Lai EK, et al. A novel channel-program–erase technique with substrate transient hot carrier injection for SONOS memory application. In: Tech digest 2006 European solid-state device research conference (ESSDERC); 2006. p. 222–5], [1]. The proposed operation utilizes substrate transient hot electron (STHE) injection and substrate transient hot-hole (STHH) injection for programming and erasing, respectively. Gate bias polarity serves to control whether hot electrons or hot holes are injected into the nitride storage layer. More efficient program and erase operations are achieved compared to the conventional Fowler–Nordheim (FN) tunneling method. The new technique operates at lower programming voltages and with shorter duration pulses, thus increases the programming throughput. Moreover, good program/erase disturb immunity, cycling endurance and data retention are demonstrated. Ó 2007 Elsevier Ltd. All rights reserved. Keywords: FN; STHH; STHE; SONOS; NAND; Memory
1. Introduction Nitride-based charge trapping flash memory device has become an important candidate for next generation flash memories because it has a simple structure that is perfectly compatible with CMOS fabrication process, has no erratic bits, no drain turn on and no storage node coupling issues. Its superior scaling capability is also suitable for high-density stand alone or embedded memory applications [2–8]. However, traditional SONOS memory with thin tunneling oxide (<30 A) [9] is prone to channel hole direct tunneling * Corresponding author. Address: Department of Electrical Engineering, National Tsing-Hua University, Hsinchu, Taiwan, ROC. Tel.: +886 3 5786688x78017; fax: +886 3 5789087. E-mail address: [email protected] (T.-H. Hsu).
0038-1101/$ - see front matter Ó 2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2007.09.032
that causes poor data retention as shown in Fig. 1a. A thicker bottom oxide is desirable for better data retention. However, the thick bottom oxide leads to extremely low FN tunneling rate for NAND-type SONOS cells [10]. As illustrated in Fig. 1b, hole cannot inject into storage layer for erasing even at more than 10 MV/cm electrical field. A ‘‘hot carrier’’ injection scheme applicable to a NANDtype array is thus desirable for SONOS NAND flash memories. Several hot carrier injection schemes have been published for SONOS cells but unfortunately they cannot be applied to NAND architectures [11,12]. This is because programmed selection is hard to implement on conventional NAND array. In this paper, we propose a novel substrate transient hot electron (STHE) and substrate transient hot-hole (STHH) operation for the SONOS NAND array. The efficient
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program and erase performance is achieved by proper body and gate biasing conditions as well as the transient collecting time.
TOX VS=0V SiN BOX
VD=1V
Source
The samples are fabricated by standard CMOS technology with channel length and channel width of 0.14 and 0.1 lm, respectively. The samples are n-channel MOSFETs with an oxide/silicon–nitride/oxide (ONO) gate dielectric stack layer. The ONO thickness from bottom to top layers is 5.4 nm, 7 nm and 9 nm, respectively. The intrinsic junction breakdown (VBD) of this cell is 6 V. Fig. 2 shows the schematics of STHE program and STHH erase operational principles. The STHE and STHH are both performed by applying body bias, Vb, of 9 V, grounding the gate and floating the source and drain. Fig. 2a shows the diagram of substrate hot carrier generation and the injection sequence. With a high positive body bias, the forward biased S/D junctions are charged to Vb minus the built-in potential [12] as step 1. Once the body bias is removed, the S/D junctions are switched to reverse bias. The significant reverse bias causes a fast discharge and hot carriers are then generated by the transient avalanche junction breakdown as step 2. Afterward, the hot carrier can be extracted with different Vg bias voltages. For the programming scheme in Fig. 2b, positive Vg bias is utilized to efficiently collect hot electrons. On the contrary, negative Vg bias is applied for erasing operation, when hot hole is collected in the nitride layer. Contrary to previous studies [11,12], we demonstrate in this work that not only hot holes but also hot electrons can be injected with proper switching of Vg bias polarity. This is a strong evidence that electron and hole sources come from substrate hot carrier in our device, rather than from FN tunneling current. The Vb bias duration (Tb) and Vg bias duration, or the collecting time, (Tgc) are two important parameters that determine the charge injection efficiency. Very short Vb bias duration (Tb = 0.5 ls) is sufficient for hot carrier generation. This is because hot carriers can be
VG= -18V
VG=5V TOX VS=0V SiN BOX
2. Experimental
VD=0V
Source
Drain
Drain
P-sub
P-sub
(a)
(b)
Fig. 1. (a) Schematic illustration of the poor data retention caused by electrons leaking to the substrate for SONOS cells with very thin tunnel oxide (<30 A). (b) SONOS cells with thicker tunnel oxide (>50 A) provides better data retention. However, hole injection rate to the storage layer is very low even at 10 MV/cm E- field.
Start discharging
(b)
VG
Tox
90A
SiN
70A
Box
54A
n+
2 2
VD/VS
Gate
S
1 1
7
D
7
Τb
Vb 0
n+
2 P-w
Hold Charge Collect
Vg 0 Tgc
(c)
1
VD/VS
S/D: floating VB 0
Hold Charge Collect
Vg -7
(a)
7
Τb
Vb 0
Tgc
Fig. 2. (a) Schematic illustration of the substrate transient hot carrier injection in SONOS cell. (b) The pulsing sequence of substrate transient hot electron (STHE) injection for programming operation. (c) The pulsing sequence of substrate transient hot-hole (STHH) injection for erasing operation.
a
Tgc=10μs, Tb=0.5μs
4.5
b
10-5 STHE-Program STHH-Erase
4.0
10-6
3.5
10-7 STHE-Program
3.0
I D (A)
Vt (V)
Vg= 9, Vb=9V ( STHE ) Vg=-9, Vb=9V ( STHH )
STHH-Erase
10-8
2.5
10-9
2.0
10
-10
10-11
1.5 0
2
4
6
8
10
12
# Program/Erase shot
14
16
18
0
1
2
3
4
5
VG (V)
Fig. 3. (a) Programming and erasing characteristics at various Vg bias (9 V/9 V), with Tgc = 10 ls and Tb = 0.5 ls. (b) The IV curves of substrate transient hot electron injection (open symbol) and substrate transient hot-hole injection (solid symbol). Parallel IV curve shift indicates uniform channel injections.
T.-H. Hsu et al. / Solid-State Electronics 51 (2007) 1523–1528
a
5
6
4
5
3
Tgc=0.1us Tgc=2us Tgc=10us Tgc=50us Tgc=100us Tgc=200us Tgc=500us Tgc=1ms Tgc=10ms
4
3
2
1
Vt (V)
Vt (V)
b
W/L=0.1/0.14μm,Vg=9V,Vb=9V, Tb=0.5μs (STHE)
7
1525
W/L=0.1/0.14mm,Vg=-9V,Vb=9V, Tb=0.5μs (STHH)
Tgc=0.1us Tgc=2us Tgc=10us Tgc=50us Tgc=100us Tgc=200us Tgc=500us Tgc=1ms Tgc=10ms
2
1
0
-1 0
2
4
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14
16
18
20
22
0
2
4
# Program shot
6
8
10
12
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16
18
20
22
# Erase shot
Fig. 4. The operation speed of STHE (a) and STHH (b) injection is strongly related to transient collecting time (Tgc). Longer Tgc enhances the hot carrier collection in the storage layer.
efficiently collected during Vg bias time; hence, the Vb bias duration can be shortened to significantly reduce the power consumption. The low operation voltage in the proposed programming scheme can further save charge pumping overhead and simplify circuit design compared to conventional FN tunneling program and erase operation used in NAND arrays. 3. Results and discussions Fig. 3 shows the Vt shift and the I–V curve during STHE programming and STHH erasing operations. Different Vg bias levels were adopted for programming and erasing, respectively, while all other parameters remain constant (Vb = 9 V, Tgc = 10 ls and Tb = 0.5 ls). The I–V curves shift parallelly, suggesting that the channel is uniformly programmed and erased [13]. This is somewhat counter intuitive, since substrate transient hot carriers are gener-
ated near source and drain junctions [12]. This is probably due to that the substrate avalanche hot carriers have a wider spread and in a short channel device the local charge trapping regions merge into a continuous trapping layer. The speed of STHE and STHH injection depends strongly on the collecting time, as shown in Fig. 4. A longer collection pulse extracts more hot electrons/holes into the storage layer. By designing a proper collecting period (Tgc), substrate bias duration (Tb) can be shortened to achieve more efficient program and erase operation. The STHE program operations with different Vg/Vb bias conditions are compared in Fig. 5. The programming speed is increased by applying higher Vg and Vb biases. Programming speed of 200 ls for DVt = 2 V is achieved with Vg = 9 V and Vb = 9 V. As shown in Fig. 6, STHH erase efficiency is demonstrated at different Vg/Vb bias conditions. The erase speed is also increased with higher Vg and Vb biases. Erasing
7
5
Tgc=50μs, Tb=0.5μs (STHE) 6
4
Vg=3V,Vb=9V Vg=5V,Vb=9V Vg=7V,Vb=9V Vg=9V,Vb=9V Vg=9V,Vb=7V Vg=9V,Vb=5V Vg=9V,Vb=3V
4
3
Vt (V)
5
Vt (V)
Tgc=50μs, Tb=0.5μs (STHH)
Vg= -3V,Vb=9V Vg= -5V,Vb=9V Vg= -7V,Vb=9V Vg= -9V,Vb=9V Vg= -9V,Vb=7V Vg= -9V,Vb=5V
2
3 1
2
1
0
10-7
10-6
10-5
10-4
10-3
Program time (s)
Fig. 5. The program characteristics of the STHE method with different gate voltage and body voltage. Both gate and body bias can be used to modulate the programming efficiency. Programming time of 200 ls for DVt = 2 V is demonstrated with Vg = 9 V and Vb = 9 V.
10-7
10-6
10-5
10-4
10-3
Erase time (s)
Fig. 6. The erase characteristics of the STHH method under different gate voltage and body voltage conditions. Both gate and body bias can be used to modulate the erase efficiency. Erasing time of 350 ls for DVt = 2 V is obtained with Vg = 9 V and Vb = 9 V.
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a
4.5
b 10
-4
W/ L= 0.1 / 0.14 μm
10-5
4.0 10-6
Vg= 9V, Vb=9V, Tgc=100μs, Tb=0.5μs, STHE Program
Erased state (EV)
3.0
Programmed state (PV)
200 mV/dec
184 mV/dec
257 mV/dec
10-7
ID (A)
Vt (V)
3.5
10-8
EV(Initial) PV(Initial) EV(P/E=1) PV(P/E=1) EV(P/E=100) PV(P/E=100) EV(P/E=1K) PV(P/E=1K) EV(P/E=10K) PV(P/E=10K)
260 mV/dec
-9
10
2.5
Vg= -9V, Vb=9V, Tgc=100ms, Tb=0.5ms, STHH Erase 2.0
10-10 10-11 10-12
1.5 100
Initial
101
102
103
104
-1
0
1
2
# P/E Cycle
3
4
5
6
VG ( V )
Fig. 7. (a) 10 K cycling endurance performed by STHE program and STHH erase operations. (b) IV of programmed and erased states. After P/E cycling, the sub-threshold slopes are moderately degraded indicating some interface damage by hot holes.
speed of 350 ls for DVt = 2 V is obtained with Vg = 9 V and Vb = 9 V. It is clear from Figs. 5 and 6 that body bias is more sensitive for substrate transient hot carrier injection for both programming and erasing operations. For example, the cells can be programmed or erased only when body bias is higher than 7 V. This is also a proof that the hot carrier source comes from junction breakdown, since junction breakdown voltage (VBD) of this device is around 6 V. Once S/D junction potential is raised to a level >VBD, transient hot carriers are generated and programming and erasing achieved with moderate gate bias. In addition, the programming efficiency is higher than the erasing efficiency. This is because holes encounter a much higher barrier height (4.4 eV) than electrons. In summary, both program and erase speeds are much higher than FN tunneling for SONOS devices. Fig. 7a shows the cycling endurance of STHE program and STHH erase with an operation window of 2 V. Good endurance up to 10 K cycles is demonstrated. However, after 10 K cycling, the sub-threshold swing of programmed and erased state are moderately degraded as shown in
Fig. 7b, due to interface damage induced by hot holes. This is testified by the increase of charge pumping current (Icp) from cycled device. Fig. 8 shows that less than 5E11 cm2 eV1 Dit generate after 10K cycling which is superior than other hot hole erased nitride-trapped memories [14]. In addition, the moderate interface degradation mirrored in better retention characteristics shown in Fig. 10. It is believed that short discharge time of this novel scheme help to ease off interface damage. Fig. 9 illustrates the read disturbance under different cycling times. Excellent read disturb immunity is observed with >1000 s stress endurance for post 10 K-cycled cells. After 150 °C, >2 days baking test, no charge loss and charge gain is observed, as shown in Fig. 10. This is an inherent merit of nitride-trapped memory – it is immune to local damage and pinhole caused retention issues even after cycling stressing. This novel programming and erasing scheme can be implemented on a modified NAND structure with divided substrate bit line (DSB–NAND), for which the substrate is isolated by STI and each BL is connected to the corre-
10x10-12
3.0 P/E=1 P/E=100 P/E=1K P/E=10K
Vg= 5V, Vd= 1.0V 2.5
6x10-12
2.0
ΔVt (V)
Icp (A)
8x10-12
4x10-12
1.5
P/E= 1 P/E= 1K P/E= 10K
1.0
2x10-12
0.5 0 -2
-1
0
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5
6
7
VG (V )
Fig. 8. Charge pumping current (500 kHz) using stepping high pulses for cycled device.
0.0 Initial
1
10
100
1000
Stress time (s)
Fig. 9. Read disturbance of STHE–STHH as a function of P/E cycling.
T.-H. Hsu et al. / Solid-State Electronics 51 (2007) 1523–1528
sponding divided substrate. Fig. 11a illustrates the proposed programming conditions in the DSB–NAND array architecture. A positive voltage of 9 V is applied to the selected WL and the unselected WL’s are grounded. BL voltages of 9 V and 0 V are applied on the selected cells and the unselected cells, respectively. Since the BL is connected to the substrate, the BL voltage can modulate the well potential of the DSB–NAND string with the turn on GSL transistor. The erase scheme is demonstrated in Fig. 11b. A positive bias of 9 V is applied on selected BL’s to charge the well potential. At this time, a negative voltage is applied to the selected WL to induce hot-hole injection. Since the erase operation is similar to the program operation except for the polarity of the gate voltage, random erase operation can be achieved. Consequently, random program and random erase can be realized with the STHE–STHH operation schemes, so that SONOS DSB–NAND arrays can be extended for both data and code Flash applications. Program and erase disturb immunity is demonstrated in Fig. 12. When programming, the neighboring cells A and B only experience bias on substrate and gate electrode, respectively, as shown in Fig. 12a. In the same way, in Fig. 12b, the applied bias only goes to substrate and gate for erasing on cells C and D. Therefore, the conditions for generating hot electron or hole are not met for the neighboring cells. This also eliminates the need for the conventional self-boosting scheme. This is very helpful to ease the peripheral loading and design complexity. The read operation is shown in Fig. 13. First, turn on the select transistors (GSL, SSL), then apply read voltage on selected WL and ground selected bit line while turn on all pass gate transistors and the source line. The sensing scheme is almost the same as conventional NAND method. Fig. 14 demonstrates the read current of a 16-string NAND array. The read current can be enhanced by increasing the Vpass voltage. For Vpass = 5 V and Vread = 1 V, the read current is larger than 3 lA.
5.0
W/L = 0.1 / 0.14μm, 150oC baking test 4.5 4.0
Vt (V)
3.5 3.0
Programmed state Erased state
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Initial 100
101
102
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105
106
107
108
109
10 Year
Baking time (s)
Fig. 10. Good data retention can be maintained after 150 °C, 2 days baking test.
BL3=9V BL2=9V BL1=0V
BL3=9V BL2=9V BL1=0V GSL=11V
GSL=11V
WL1=0V
WL1=0V
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WL3=0V
WL3=0V
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SL=Floating
(b)
(a)
1527
Fig. 11. (a) Substrate transient hot electron (STHE) injection for programming operation can be implemented on NAND structure with divided substrate bit line (DSB–NAND). A positive voltage is applied to selected WL and BLs with pass gates and the unselected BLs are grounded. (b) Substrate transient hot-hole (STHH) injection for erasing operation can also be implemented on DSB–NAND. A negative voltage is applied to the selected WL with positive voltage to the selected BLs with pass gates while the unselected BLs are grounded.
(a) 0V
0V 9V
0V
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WL2= 9V
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Neighbor cell Program / Erase disturb
Cell A/C disturb Cell B ( EVstate ), program disturb Cell D ( EVstate ), erase disturb Cell B ( PVstate ), program disturb Cell D ( PVstate ), erase disturb
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C D
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10
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1000
Stress time (s)
(c)
Fig. 12. Good program and erase disturb immunity is demonstrated. Hence, complex self-boosting scheme is not required.
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operations are proposed for SONOS NAND memory applications. The fundamental limitations of high voltage operation and low tunneling efficiency are overcome by the proposed operational scheme. Excellent cycling endurance and data retention are demonstrated. Moreover, using a DSB–NAND structure both random bit program and random bit erase can be implemented for both data and code Flash memory applications.
BL=1V BL=1V BL=0V BL=1V GSL=7V WL1=Vpass WL2=Vread WL3=Vpass SSL=7V SL=1V
Fig. 13. To read, turn on select transistors (GSL, SSL) and apply read voltage on selected WL and SL. Sensing scheme is the same as conventional NAND.
8x10-6
Vpass= Vpass= Vpass= Vpass= Vpass= Vpass=
7x10-6 6x10-6
16- WLs string Vread= 1V EV= 1V
3V 4V 5V 6V 7V 8V
I D (A)
4x10-6 3x10-6 2x10-6 1x10-6 0
1
2
3
4
5
6
VG (V)
Fig. 14. The read current can be enhanced by increasing Vpass voltage. For Vpass = 5 V, and Vread = 1 V, the read current for a 16-string NAND array is larger than 3 lA.
Table 1 Performance comparison of DSB–NAND and standard NAND structure Structure
DSB–NAND STD–NAND
Performance Page program
Page read
p p
p p
Authors would like to thank technology development center of Macronix International Co. for the support of device fabrication and characterization. References
5x10-6
0
Acknowledgements
Good program inhibit p p
Small cell size p p
Random bit P/E p
Supply voltage < 10 V p
Table 1 briefly lists the comparison between standard NAND array and DSB NAND of this work. They all can perform page program, page read, with good program inhibition and small cell size. However, DSB NAND provides random bit program and erase and low voltage operation that are superior to traditional NAND Flash. A total solution that provides both NOR and NAND function is possible with the STHE–STHH operation. 4. Conclusion Novel substrate transient hot electron (STHE) programming and substrate transient hot-hole (STHH) erasing
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