Transient simulation to analyze flash memory programming improvements due to Germanium content in the substrate using Nonquasi-Static techniques

Microelectronic Engineering 99 (2012) 23–27

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Transient simulation to analyze flash memory programming improvements due to Germanium content in the substrate using Nonquasi-Static techniques Scott C. Wolfson ⇑, Fat D. Ho University of Alabama in Huntsville, Department of Electrical and Computer Engineering, Huntsville, AL 35899, USA

a r t i c l e

i n f o

Article history: Received 2 February 2012 Received in revised form 18 April 2012 Accepted 10 May 2012 Available online 7 June 2012 Keywords: Flash memory MOS memory circuits Semiconductor device models Simulation

a b s t r a c t We present a detailed and accurate physics based method for modeling flash memory programming characteristics when the substrate contains different percentages of Germanium. Typical memory cells are programmed by moving electrons from the substrate to the floating gate. We determine this electron movement by considering the contributions attributed to the Nonquasi-Static gate current and tunneling currents while keeping the Germanium percentage as an independent variable. The simulations accuracy is further increased by using Nonquasi-Static methods to determine the drain and source currents as well as the device capacitance values. The goal of this paper is to highlight the physical parameters of the memory cell that are affected by Germanium and show the improvements that can be achieved by using Silicon–Germanium (SiGe) substrate material versus Silicon only. Several papers have been published on MOSFET’s with SiGe substrates but none have been published on the use of SiGe substrates to improve flash memory programming. Published by Elsevier B.V.

1. Introduction Many semiconductor modeling techniques have been implemented and upgraded over the years with tradeoffs in the areas of accuracy and execution time. The model presented in this paper is physics based and provides an upgrade to existing techniques by integrating the effects produces by Germanium content in the substrate material. The purpose of this model upgrade is twofold. Firstly, increasing the performance and density of floating gate memory is desired by the commercial, defense and space industries. The addition of Germanium to the substrate of transistors has produced measurable performance improvements. The intent of this paper is to demonstrate thought the use of device modeling that improvements can also be realized in floating gate devices. Secondly, the foundational equations and techniques are physics based versus empirical. This allows the effects of substrate material properties, temperature, device scaling, supply voltage levels, doping concentration, programming pulse rise time, programming pulse duration and programming pulse magnitudes can be analyzed prior to fabrication. This can aid in determining how design changes effect performance and can greatly reduce the required design time, design cost and time to market for products using this technology. The following sections detail the key parameters affected by the addition of Germanium to the substrate material, ⇑ Corresponding author. Tel.: +1 256 876 8713; fax: +1 256 876 8688. E-mail address: [email protected] (S.C. Wolfson). 0167-9317/$ - see front matter Published by Elsevier B.V. http://dx.doi.org/10.1016/j.mee.2012.05.014

top level equations used in the simulation development, simulation sequence and results achieved. 2. Background It is well known that Germanium (Ge) has many characteristics when compared to Silicon (Si) that are attractive to transistor designers. This includes a narrower bandgap (Eg), lower electron/ hole effective mass (mn/mp), lower electron affinity (qX), higher intrinsic carrier concentration (ni) and higher permittivity (es). Also, Ge can easily form covalent bonds with Si because they are both Class IV elements (i.e. four valence electrons). This characteristic allows Ge and Si to be combined in different percentages for the purpose of tailoring the performance of the device whether it is a transistor or a floating gate charge storage device. The values used for the above mentioned device parameters are shown in Tables 1 and 2 [1]: Eq. (1)–(9) were used to determine the device parameters based on the Ge percentage in the substrate material. These equations were derived using information from [1] and/or linear interpolation.

qX ¼ qXSi  ðqXSi  qXGe Þ  Eg ¼ Eg 0  aT 2 =ðT þ bÞ

  Ge% 100

ð1Þ ð2Þ

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Table 1 Summary of Si and Ge Parameters.

Eg (eV) mn (kg) mp (kg) qX (eV) ni (cm3) es (F/cm)

Si

Ge

1.1205 9.83  1031 7.37  1031 4.05 8.79  10+9 1.05  1012

0.6634 5.01  1031 3.37  1031 4 2.02  10+13 1.42  1012

Table 2 Bandgap Parameters.

Eg0 (eV) a (eV/K) b (K)

Si

Ge

1.166 0.000473 636

0.7437 0.000477 235

where:

Eg 0 ¼ Eg0Si  ðEg0Si  Eg0Ge Þ 

  Ge% 00 1

ð3Þ

a ¼ aSi  ðaSi  aGe Þ 

  Ge% 100

ð4Þ

b ¼ bSi  ðbSi  bGe Þ 

  Ge% 100

ð5Þ

mn ¼ mnSi  ðmnSi  mnGe Þ 

mp ¼ mpSi  ðmpSi  mpGe Þ 

es ¼ esSi  ðesSi



Ge% 100



  Ge% 100

  Ge%  esGe Þ  100

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Eg  2 ni ¼ 4ðð2pÞK j T=hj Þ3 ðmn mp Þ3=2 e KT

ð6Þ

as the Germanium percentage is increased. Also, the results achieved exactly matched the data presented in [1] for pure Si and pure Ge. These results are important because of the impact to the solution to Poisson’s equation and the Nonquasi-Static model used as a foundational component of this research. Although the bandbap and other parameters are not directly used in the Nonquasi-Static model, the intrinsic carrier concentration value appears in numerous locations and variation in the intrinsic carrier concentration produces changes to the calculated gate current. The following sections detail the equations used in the simulation development, simulation sequence and results achieved. The inclusion of the simulation sequence is meant to provide the reader with insight into the methods and numerical techniques used to achieve the results presented in this paper.

ð7Þ 3. Gate current equations

ð8Þ

ð9Þ

where: Kj = 1.38E-23 (J/K) – Boltzmann’s constant, K = 8.62E-5 (eV/K) – Boltzmann’s constant, hj = 6.63E-34 (Js) – Plank’s constant, T = 300 (K) – Temperature Figs. 1 and 2 show the effects of Ge content in the substrate material on Eg and ni using the equations from this section. As expected, the intrinsic carrier concentration increases exponentially

Fig. 1. Bandgap (Eg) versus %Ge.

Fig. 2. Intrinsic Carrier Concentration (ni) versus %Ge.

The Flash programming model presented in [2] was modified to account for changes in the amount of Germanium in the substrate and provide a comparison between the amounts of time required to achieve a desired threshold voltage versus Ge content in the substrate. The intent of this work is not to repeat the derivations presented in [2] but rather to highlight the top-level equations used to produce the results presented at the conclusion of this paper. As presented in [2], there are three major contributing components to the gate current. These components are tunneling electrons from the substrate, tunneling electrons from the source/ drain and current due to charge coupling between the substrate surface and the floating gate. The equations used to model the tunneling electrons from the substrate takes Fowler–Nordheim and direct tunneling components into account. Similarly, equations used to model the tunneling electrons from the source/drain are very similar to the ones used for substrate tunneling but have the following differences. The first difference is associated with the Metal–Oxide-Semiconductor (MOS) structure. The MOS structure used to model tunneling from the substrate is comprised of the floating gate section over the substrate, oxide material and the p-type (acceptor) substrate material. In contrast, the MOS structure to model the tunneling current from the source and drain is comprised of the floating gate section that overlaps the source and drain, oxide material and the n-type (donor) source/drain material. The second difference is associated with the surface potential and the oxide electric field. These two parameters are function of channel position and time in the substrate tunneling model as opposed to time only in the source/drain tunneling models.

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S.C. Wolfson, F.D. Ho / Microelectronic Engineering 99 (2012) 23–27 Table 3 Device Parameters Used for the Simulation.

Table 4 Approx. time to reach the desired threshold voltage of 6.91 V.

Process parameter

Symbol

Value

Units

%Ge

Time (ls)

Width Length Substate doping Control gate oxide thickness Floating gate oxide thickness Interface charge Maximum drift velocity Junction depth Overlap length Duffusion doping Oxide permitivity

W L’ NA tox1 tox qo’

0.8 0.6 5  10+17 2  106 1  106 5  109 5.5261  10+6 0.2 0.2 1  10+19 3.453  1013

lm lm

0 25 50

50.0 47.0 45.0

vmax xj LOLs, LOLd ND

eox

3

cm cm cm C/cm2 cm/s lm lm cm3 F/cm

The generic equations used to model the tunneling currents from both the substrate and the source/drain are presented in [2–4] and repeated here.

  b iG ¼ sgnðEox ÞaWLE2ox exp Eox

ð10aÞ

The numerical techniques and Nonquasi-Static methods presented in [6] were used to solve (12). It is also important to note that the inclusion of short/narrow effects, channel length modulation and mobility degradation in the Nonquasi-Static model was vital for producing the results presented in this paper. Each of the gate current components presented in this section are effected by increases in the intrinsic carrier concentration produced by Ge content in the substrate. In particular, the barrier height decreases and the oxide electric field increases. This produces larger tunneling currents. Similar gate current increases as a result of the increased intrinsic carrier concentration were also observed when modeling the Nonquasi-Static gate current component.

if Eox t ox > ub "

 3 # Eox tox 2 iG ¼ iG exp 1  1 

ub

ð10bÞ

Where: Eox – Oxide electric field (V/cm), a – Tunneling equation parameter, b – Tunneling equation parameter, W – Tunneling area width (cm), L – Tunneling area length (cm), ub – Barrier height (eV) The method used for deriving the charge coupling current equations originated from the Nonquasi-Static continuity equation presented in [5,6]. The generic equation is:

ð11Þ

where qg’, Gate charge per unit area (C/cm2); x – Channel position (cm); t – Time (s).Rearranging (11) produces the following:

d dt

Z 0

The transient nature of this model is based on knowing the floating gate voltage at the next time interval. The material presented in [2] details the derivations and equations used to determine the transient behavior of the floating gate voltage. In summary, the resulting generic equation for the floating gate voltage at t + 1 is:

V fg ðt þ 1Þ ¼ V fg ðtÞ þ

@qg 0 @iG ¼W @x @t

iG ¼ W

4. Floating gate voltage, floating gate charge and threshold voltage at the next time interval

L

q0G dx

ð12Þ

dVfg ðtÞ Dt dt

ð13Þ

This floating gate voltage is used to calculate the cumulative gate current using the equations from the previous section. The resulting gate current can now be used to update the floating gate charge and ultimately the memory cells new threshold voltage using the following equations.

Fig. 3. Simulation results showing the Threshold Voltage vs. Time with varying percentages of Ge in the substrate. (Vd = 4 V, Vs = 0 V, Vb = 3 V).

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Fig. 4. Simulation results showing the Gate Current vs. Time with varying percentages of Ge in the substrate.

Q fg ðtÞ ¼ Q fg ðt  1Þ  iG ðtÞDt V tcg ðtÞ ¼ V tcg

initial ð0Þ



Q fg ðtÞ C oxg

ð14Þ ð15Þ

5. Simulation steps This section outlines the simulation steps and equations used to model the programming process. The desired result of the programming process is to determine the threshold voltage shift as charge is added to the floating gate at each time interval. These simulation steps are identical to the ones presented in [2] and have been repeated for completeness. (1) Enter fabrication parameters, time intervals (tstart, tstop, tstep), and initial terminal voltages, final terminal voltages and programming pulse slew rates. (2) Calculate device parameters, capacitances and initial steady state values (3) Calculate initial threshold voltage (Vtcg) (4) Determine initial floating gate charge (Qfg) (5) Use bisection, trapezoidal integration and the Nonquasi-Static model to determine the gate current component as outlined on Section 3 (6) Update the device capacitances and the total capacitance (7) Calculate the gate current component due to tunneling from the substrate (8) Use bisection to calculate the gate current components due to tunneling from the source and drain terminal overlap regions (9) Sum the tunneling gate current components with the Nonquasi-Static gate current to determine the total gate current iG (10) Calculate the floating gate voltage at the next time interval (11) Update Qfg (12) Update the threshold voltage Vtcg (13) Update terminal voltages (14) Increment simulation time (t = t + Dt) (15) If t < tstop, go to step 5

6. Results Simulations were performed to demonstrate that programming speeds can be increased by using a SiGe substrate material. The simulation runs presented were executed with a 0%, 25% and 50% Ge content in the substrate. As expected, the increase in the Germanium content in the substrate produces an increase in the intrinsic carrier concentration which results in a shorter programming time. The memory cell parameters used to perform the comparison were taken from the material presented in [3] and summarized in Table 3. Also, the experimental data presented in [3] was used to validate the accuracy of the modeling techniques used in this paper and in [2] when a pure Si substrate is considered. The simulation results presented in Fig. 3 show the different shifts in the memory cells threshold voltage during the programming process. The programming speed increase due to Ge content is easily observed through visual inspection. A tabular listing of these results is presented in Table 4. The simulation results presented in Fig. 4 demonstrate that increases in the Ge content in the substrate material produces an initial increase in the gate current. This is root cause of the decrease in the amount of time required for the threshold voltage of the memory cell to reach a desired level. Similar results were attained when performing this same analysis on memory cells using an 180 nm process and the validity of this process is expected to remain viable at channel lengths decrease due to the models heavy reliance on physical parameters, limited used of assumptions and the inclusion of small/narrow channel effects. 7. Conclusion As mentioned in the introduction, many semiconductor modeling techniques have been put into practice and adapted/upgrade as technology has advanced and increased accuracy is essential. In the area of floating gate memory, the established modeling techniques are based on probabilities. Our research has determined that this method is deficient when analyzing the effects of Germanium. This led to the use and adaptation of the modeling technique presented

S.C. Wolfson, F.D. Ho / Microelectronic Engineering 99 (2012) 23–27

in [2]. By using this technique we were able to produce results comparable with the referenced experimental data for a Si base floating gate device and concluded that accurate results were only achieved when the contributions of the tunneling current at every point in the channel region starting at the source and ending at the drain, the effects of the surface potential change across the channel region on the oxide E-field and charge coupling currents were included. Previous research which analyzes the effects on the erase process due to Ge content in the substrate has also been performed [7]. Although the cell structure and programming pulse slew rates are different in [7], a performance increase was observed. These small reductions in the amount of time required to program and erase a memory cell becomes significant when considering the cumulative amount of programming and erase events that occur while using products such as personal computers and cell phones. As technology trends towards faster and denser floating gate memory it is imperative that the models used to simulate their performance are maintained and upgraded. This will allow the designer to determine how the component of interest will operate in a relevant environment prior to the fabrication process. It is our conclusion that using SiGe substrate material is a viable method for improving the performance of flash memory and this

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analysis would not have been achievable without physics based modeling. Our model assumes ambient conditions and leaves many areas open for further research. For example, it is currently unknown how temperature variations, degradation due to program/erase cycles and other conditions affect the performance and reliability of Flash devices designed with SiGe substrate material. Future plans for this model include upgrades that account for these effects as well as maintaining accurate results at shorter channel lengths. References [1] B. Van Zeghbroeck, Principles of Semiconductor Devices, (http:// ecee.colorado.edu/~bart/book/). [2] S. Wolfson, F. Ho, Flash Program modeling using nonquasi-static and tunneling techniques, Microelectronic Engineering, (http://dx.doi.org/10.1016/j.mee. 2011.12.019). [3] D. Esseni et al. Flexible Hot-Electron Programming of Flash Memories, IEEE 0–7803-4774-9, 1998, pp. IEDM 98–991 to 98–994. [4] K. Schuegraf, C. Hu, Electron Devices 41 (1994) 761–767. [5] Y. Tsividis, Operation and Modeling of the MOS Transistor, Oxford University Press, Inc., 1999. [6] M. Payton, A Physically-Derived Large-Signal Nonquasi-Static MOSFET Model for Computer Aided Device and Circuit Analysis, 2004, Master’s Thesis, The University of Alabama in Huntsville, School of Graduate Studies, Huntsville, Alabama. [7] S. Wolfson, F. Ho, IEEE Trans. Electron Device 57 (2010) 2499–2503.