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Ideal projection lithography using a multilayer resist process
World Abstracts on Microelectronics and Reliability
399
A submicron CMOS/SOS process for VLSI. RoY MADDOX, NANCY CASEY, CAROL SALLEE, FRIEDA KINOSHITA, ROB IMERSON and GENE WHITCOMB. Solid St. Technol., 240 (April 1982). A Computer aided CMOS/SOS process design for submicron channel length FETs is presented. Electron beam lithography is used in conjunction with optical lithography in order to achieve the dimensional objectives where needed while still maintaining a reasonable lithographic throughput. The method of interfacing the two lithographic systems is presented along with alignment accuracy data. Future modifications on the alignment interface and the process with respect to lithographic methodology is presented. The use of the image reversal technique for e-beam exposure of an optical resist is presented and the benefits of the sloped line (gate) profile discussed with respect to submicron device performance.
Thermal-wave microscopy. ALLAN ROSENCWAIG. Solid St. Teehnol., 91 (March 1982). The technique of thermal-wave microscopy is described. The capability of this technique to detect and image subsurface areas is discussed. Semiconductor manufacturing applications, including non-destructive depth profiling and doped region characterization are illustrated.
The use of molybdenum in semiconductor devices. CHRISTOPHER LANGRIDGE. Semiconductor Int., 149 (April 1982). The use of molybdenum as a thermal expansion buffer is playing an important role in the determination of reliability and performance in semiconductor devices in spite of inherent difficulties in working with this material. Selection of various surface coatings of pure materials used in conjunction with correct process and part design are allowing molybdenum to be employed not only economically but with high quality results.
Wafer steppers: considering the issues. PIETER S. BURGGRAAF. Semiconductor Int., 57 (April 1982). User-proven resolution, registration and throughput information on top-of-the-line wafer steppers is hard to locate. Thus potential buyers must carefully examine system specifications, fitting them to their own processing needs. Because specifications are often ambiguous, this is a difficult and risky task.
Semiconductor processing. A. KESTENBAUM. Semiconductor Int., 121 (April 1982). Sophisticated laser semiconductor applications have been found, and their successful use has once again ignited an interest in how lasers can play an important role in semiconductor processing. In recent developments, both active and inactive parts of circuits can be treated as laser applications expand past handling and separation techniques. The silicon process balancing act for VLSI. RICHARD B. FAIR. Solid St. Technol., 220 (April 1982). The act of heating and cooling a silicon wafer ~n order to perform thermal diffusion and oxidation can introduce or produce point defects, dissolved impurities, microdefects and strain. In addition, the silicon surface bonding arrangements can be altered. To produce device quality surface layers it is necessary to balance the high temperature processes with respect to their impact on defect growth, oxygen precipitation, and impurity gettering. These phenomena are strongly influenced by how the dynamic balance of vacancies and silicon self-interstitials is maintained during high temperature processing.
Advances in VLSI plasma etching. DAVID K. LAM. Solid St. Technok, 215 (April 1982). Much progress has been made in the application of plasma etching technology in VLSI fabrication. This paper reviews and explains the trend toward single-wafer processing and automation. Two recent innovations in the continued evolution of plasma etching equipment are presented. These are automatic electrode spacing and process programming. The theoretical basis and the practical solution are discussed.
Chip-package substrate cushions dense, high-speed circuitries. MAH EL REFAIE. Electronics, 135 (14 July 1982). Fine lines and vias mark this elastomer-coated interconnection layer; friendly to chip-carriers and TAB, it masters density and heat dissipation. Ideal projection lithography using a multilayer resist process. E. DAVID LIU, MICHAEL M. O'TOOLE and MARK S. CHANG. Solid St. Technol., 66 (May 1982). Linewidth control using a tri-layer resist system on wafers with topography is investigated. An absorbing dye is incorporated in the bottom layer to improve the usable resolution. Resist patterns of 1 gm lines and spaces over aluminized topography are demonstrated using a projection aligner. The advantages of a multilayer system are investigated using an exposure and development simulation program for optical lithography. The relative contributions of planarization and reflection suppression are discussed. Simulations indicate that the next generation of aligners will be capable of submicron resolution in the production of VLSI circuits.
Positive resist material requirements for VLSI device fabrication. Part I. DAVID J. ELLIOTT. Solid St. Technol., 116 (May 1982). The functional properties of positive photoresist systems that are needed in VLSI microlithography are Multi-chamber dry etching system. HIDEAKI ITAKURA, reviewed. These properties include wide imaging process HIROYOSHIKOMIYAand KATSUM1UKAI. Solid St. Technol., 209 latitude, good adhesion, resistance to etching environment (April 1982). A new type plasma etching system for fabricating and good exposure throughput. Other types of imaging VLSI was developed. This system gives both high precision materials that are also used in VLSIC microlithography are and a relatively high throughput. The etching characteristics of discussed in Part II. this system were investigated for poly-Si, SiO2 and A1. Both good uniformity and good reproducibility were obtained. Thermal-conduction module cradles and cools up to 133 LSI This system has potential to be used in a production line for chips. D. R. BARBOUR,S. OKTAY and R. A. RINNE. Electronics, etching fine patterns of 1 lam. 143 (16 June 1982). Designed around a 33-layer ceramic substrate, this package combines conduction and forced conUV exposure, systems and control. TED C. BETTES. vection to dissipate 300 W. Semiconductor Int., 83 (April 1982). UV exposure of photoresist is still the most commonly used photolithographic Lithography for VLSI: an overview. JAY K. HASSANand HOMI process in microelectronics manufacture and will continue to G. SARKARY. Solid St. Technol., 49 (May 1982). The conbe for quite some time. UV exposure control is vital for tinuing trend in semiconductor technology to submicron obtaining the reproducible results necessary for the manudevice geometries, coupled with the anticipated productivity facture of today's high density circuits. demand of VLSI, dictates major technology innovations in exposure systems, dry etching capabilities, materials and Bonding refractory sputtering targets. G. J. HALE and W. G. processes. Lithography tools must be viewed in the light of GATES. Semiconductor Int., 163 (April 1982). A new bonding "best choice" for the situation and time. The trade-off among technique for brittle, crack-prone sputter targets has been productivity, tool capability and cost is key to the developdeveloped to assist in the deposition of various semiconductor ment and manufacturing lithography strategy. This discusand wear-resistant materials. sion provides an extensive review of the major components
399
A submicron CMOS/SOS process for VLSI. RoY MADDOX, NANCY CASEY, CAROL SALLEE, FRIEDA KINOSHITA, ROB IMERSON and GENE WHITCOMB. Solid St. Technol., 240 (April 1982). A Computer aided CMOS/SOS process design for submicron channel length FETs is presented. Electron beam lithography is used in conjunction with optical lithography in order to achieve the dimensional objectives where needed while still maintaining a reasonable lithographic throughput. The method of interfacing the two lithographic systems is presented along with alignment accuracy data. Future modifications on the alignment interface and the process with respect to lithographic methodology is presented. The use of the image reversal technique for e-beam exposure of an optical resist is presented and the benefits of the sloped line (gate) profile discussed with respect to submicron device performance.
Thermal-wave microscopy. ALLAN ROSENCWAIG. Solid St. Teehnol., 91 (March 1982). The technique of thermal-wave microscopy is described. The capability of this technique to detect and image subsurface areas is discussed. Semiconductor manufacturing applications, including non-destructive depth profiling and doped region characterization are illustrated.
The use of molybdenum in semiconductor devices. CHRISTOPHER LANGRIDGE. Semiconductor Int., 149 (April 1982). The use of molybdenum as a thermal expansion buffer is playing an important role in the determination of reliability and performance in semiconductor devices in spite of inherent difficulties in working with this material. Selection of various surface coatings of pure materials used in conjunction with correct process and part design are allowing molybdenum to be employed not only economically but with high quality results.
Wafer steppers: considering the issues. PIETER S. BURGGRAAF. Semiconductor Int., 57 (April 1982). User-proven resolution, registration and throughput information on top-of-the-line wafer steppers is hard to locate. Thus potential buyers must carefully examine system specifications, fitting them to their own processing needs. Because specifications are often ambiguous, this is a difficult and risky task.
Semiconductor processing. A. KESTENBAUM. Semiconductor Int., 121 (April 1982). Sophisticated laser semiconductor applications have been found, and their successful use has once again ignited an interest in how lasers can play an important role in semiconductor processing. In recent developments, both active and inactive parts of circuits can be treated as laser applications expand past handling and separation techniques. The silicon process balancing act for VLSI. RICHARD B. FAIR. Solid St. Technol., 220 (April 1982). The act of heating and cooling a silicon wafer ~n order to perform thermal diffusion and oxidation can introduce or produce point defects, dissolved impurities, microdefects and strain. In addition, the silicon surface bonding arrangements can be altered. To produce device quality surface layers it is necessary to balance the high temperature processes with respect to their impact on defect growth, oxygen precipitation, and impurity gettering. These phenomena are strongly influenced by how the dynamic balance of vacancies and silicon self-interstitials is maintained during high temperature processing.
Advances in VLSI plasma etching. DAVID K. LAM. Solid St. Technok, 215 (April 1982). Much progress has been made in the application of plasma etching technology in VLSI fabrication. This paper reviews and explains the trend toward single-wafer processing and automation. Two recent innovations in the continued evolution of plasma etching equipment are presented. These are automatic electrode spacing and process programming. The theoretical basis and the practical solution are discussed.
Chip-package substrate cushions dense, high-speed circuitries. MAH EL REFAIE. Electronics, 135 (14 July 1982). Fine lines and vias mark this elastomer-coated interconnection layer; friendly to chip-carriers and TAB, it masters density and heat dissipation. Ideal projection lithography using a multilayer resist process. E. DAVID LIU, MICHAEL M. O'TOOLE and MARK S. CHANG. Solid St. Technol., 66 (May 1982). Linewidth control using a tri-layer resist system on wafers with topography is investigated. An absorbing dye is incorporated in the bottom layer to improve the usable resolution. Resist patterns of 1 gm lines and spaces over aluminized topography are demonstrated using a projection aligner. The advantages of a multilayer system are investigated using an exposure and development simulation program for optical lithography. The relative contributions of planarization and reflection suppression are discussed. Simulations indicate that the next generation of aligners will be capable of submicron resolution in the production of VLSI circuits.
Positive resist material requirements for VLSI device fabrication. Part I. DAVID J. ELLIOTT. Solid St. Technol., 116 (May 1982). The functional properties of positive photoresist systems that are needed in VLSI microlithography are Multi-chamber dry etching system. HIDEAKI ITAKURA, reviewed. These properties include wide imaging process HIROYOSHIKOMIYAand KATSUM1UKAI. Solid St. Technol., 209 latitude, good adhesion, resistance to etching environment (April 1982). A new type plasma etching system for fabricating and good exposure throughput. Other types of imaging VLSI was developed. This system gives both high precision materials that are also used in VLSIC microlithography are and a relatively high throughput. The etching characteristics of discussed in Part II. this system were investigated for poly-Si, SiO2 and A1. Both good uniformity and good reproducibility were obtained. Thermal-conduction module cradles and cools up to 133 LSI This system has potential to be used in a production line for chips. D. R. BARBOUR,S. OKTAY and R. A. RINNE. Electronics, etching fine patterns of 1 lam. 143 (16 June 1982). Designed around a 33-layer ceramic substrate, this package combines conduction and forced conUV exposure, systems and control. TED C. BETTES. vection to dissipate 300 W. Semiconductor Int., 83 (April 1982). UV exposure of photoresist is still the most commonly used photolithographic Lithography for VLSI: an overview. JAY K. HASSANand HOMI process in microelectronics manufacture and will continue to G. SARKARY. Solid St. Technol., 49 (May 1982). The conbe for quite some time. UV exposure control is vital for tinuing trend in semiconductor technology to submicron obtaining the reproducible results necessary for the manudevice geometries, coupled with the anticipated productivity facture of today's high density circuits. demand of VLSI, dictates major technology innovations in exposure systems, dry etching capabilities, materials and Bonding refractory sputtering targets. G. J. HALE and W. G. processes. Lithography tools must be viewed in the light of GATES. Semiconductor Int., 163 (April 1982). A new bonding "best choice" for the situation and time. The trade-off among technique for brittle, crack-prone sputter targets has been productivity, tool capability and cost is key to the developdeveloped to assist in the deposition of various semiconductor ment and manufacturing lithography strategy. This discusand wear-resistant materials. sion provides an extensive review of the major components