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Multilayer-resist lithography
World Abstracts on Microelectronics and Reliability are a source of channel or body leakage in MOS technology and the influence of these defects on generation lifetime is process dependent. Enhanced-gettering mechanisms associated with treated bulk wafers and improved processing performedtoobtaindesireddeviceperformancearediscussed,
Trends in wafer fab and their driving economic forces. W. R. BOTTOMS and J. S. WENSTRAND. Solid St. Technol. 173 (August 1983). The success of a merchant semiconductor manufacturer, like any business, can be measured in terms of return on investment. This article examines the economic impact of some of the prominent trends in "front end" wafer lab: changes resulting in reduced investment, lower operating costs, and increased output on a per circuit function basis, Automation will be a recurring theme because it has all three effects and, thus, is a very large leverage factor for semiconductor manufacturers. This paper is divided into three major sections: Investment, Operating Costs and Increased Output. Major trends in equipment and lab design will be discussed in relation to each. The investment and operating cost breakdowns are based on a composite of statistics gathered from several semiconductor manufacturers. The numbers are typical of a 5000 5 in wafers per week fab manufacturing 64 K DRAMs. Wafer inspection automation: current and future needs. K. HARRIS,P. SANDLANDand R. SINGLETON.Solid St. Technol. 199 (August 1983). There is a need for micro-pattern inspection of in-process wafers in order to monitor the ongoing pattern quality. In the context of volume wafer production, this need is currently being addressed by a variety of manual and semiautomated equipment. There is a continuing trend towards automation. A profile of current needs and practices as well as possible future solutions to pattern inspection and measurement has been developed after consulting with numerous individuals in the industry. Needs that will develop in the near future and some possible solutions are considered. Computer Aided Processing in the photo area is discussed, Technological advances in physical vapor deposition, GUENTHER HERKLOTZand HANS ELIGEHAUSEN.IEEE Trans. Components Hybrids Mfg Technol. CHMT-6 (2) 173 (June 1983). In the production of contact materials physical vapor deposition (PVD) technology is widely used. After a short description of the different PVD processes, the influences of the most important process parameters on the plating quality will be discussed. Also some technological applications will be cited, Silicon-wafer process evaluation using minority-carrier diffusion-length measurement by the SPV method. A . M . GOODMAN, L. A. GOODMANand H. F. GOSSENBERGER.RCA Ret,. 44, 326 (June 1983). Measurement of the minoritycarrier diffusion length L by the constant-magnitude steadystate surface photovoltage (SPV) method has become an important tool within RCA for evaluating the effect (on L) of silicon device fabrication steps. We present first a simplified description of the method and the practical information required for implementing this measurement technique. Substrate selection, sample preparation, data evaluation, and the limitations of the method are discussed in detail. Next, we describe the use of the SPV technique to monitor the unintentional introduction of heavy metal impurities at five different steps during wafer processing. The causes of wafer contamination are: (1) inadequate wafer cleaning, (2) handling wafers with stainless-steel tweezers, (3) frictional contact between wafers and metallic components in the end stations of ion implanters, (4) a malfunctioning boron-doping source and (5) impurities introduced during epitaxial layer growth. The beneficial effect of adding 1-1-1 trichloroethane (TCA) to a furnace ambient is assessed by using the SPV technique and also by counting the number of crystalline defects delineated with Wright etch.
591
Multilayer-resist lithography. PIETER S. BURGGRAAF.Semiconductor Int. 48 (June 1983). For several years multilayerresist techniques have been developed with the idea of extending the limits of optical aligners. Today, is multilayerresist technology still an R & D effort or is it good for production wafer fabrication 9. Bake effects in positive photoresist. TOM BATCHELDER and Joan PIATT. Solid St. Technol. 211 (August 1983). The advent of in-line hotplate baking of photoresist has made precise adjustment of the resist dissolution rate ratio possible by thermolytic as well as photochemical processes. Post Exposure Bake (PEB) prior to development permits elimination of standing waves, increased contrast and improved adhesion. When this process is coupled with a low temperature resist softbake (~75°C), the disadvantages of PEB, decreased photospeed and reduced critical dimension control can be overcome. When this process is applied, 1.251~m lines and spaces can be obtained over 1.0~tm high oxide steps and 0.8 ~.m equal lines and spaces can be resolved using mature, industry accepted equipment. Critical dimension control is also found to be excellent across the wafer and from wafer to wafer. A novel approach to silicon gate CMOS device scaling. JAN H. KING.Solid St. Electron. 26 (9) 879 (1983). A new approach is reported for fabricating scaled Si-gate CMOS devices using medium temperature ( 2 900°C) LPCVD deposited SiO~ as the dielectric interlayer. The film can be deposited from 850 to 1000°C using a graded temperature profile and optimum pressure. A maximum of 100 wafers with 8 ~ variation of thickness per run has been achieved using the process decribed in this paper. The medium-temperature LPCVD SiO2 film exhibited step-coverage as good as the conventional low temperature PSG film. Since the new film requires no high temperature treatment, the conventional Si-gate CMOS diffusion process has been used to obtain the micron and submicron junction depths that are required to fabricate scaled CMOS devices. Such a processing approach, converting a 5-6~tm geometry CMOS process to a 3 ~m geometry CMOS process, is described. An investigation of the factors that influence the deposit/etch balance in a radiant-heated silicon epitaxial reactor. J. F. CORBOYand R. PAGLIARO,JR., RCA Rev. 44, 231 (June 1983). As the physical dimensions of integrated circuits become smaller and the thickness of the active device regions decreases, epitaxial films of a more perfect crystalline quality are required. High-quality epitaxial deposits can be prepared inthecommerciallyavailableradiant-heatedreactor(Applied Materials AMC-7900). Using the radiant-heated configuration, the thermal gradients normal to the substrate can be minimized. Maintenance in this reactor must be carefully programmed to avoid accumulation of deposits on the reactor bell jar which would attenuate the radiant energy. Despite the drawbacks associated with this approach,, this reactor is widely used in the semiconductor industry where deposits with good crystalline perfection are required. Little is to be found in the literature, however, on the impact of the variables of total gas flow, location of the substrate on the susceptor, and susceptor rotation on the local deposition/etch rates and uniformity of the deposit resistivity. To develop an understanding of these factors, the reactor was operated in an experimental mode with no susceptor rotation. The results of this study and the implications with respect to operation of the reactor in the normal rotating-susceptor mode are discussed.
Imaging latch-up sites in LSI CMOS with a laser photoscanner. DANIELJ. BURNSand JEFFREYM. KENDALL.IEEE 21st Ann. Proc. Reliab. Phys. 118 (1983). A non-destructive laser photoscanning technique has been used to analyze
Trends in wafer fab and their driving economic forces. W. R. BOTTOMS and J. S. WENSTRAND. Solid St. Technol. 173 (August 1983). The success of a merchant semiconductor manufacturer, like any business, can be measured in terms of return on investment. This article examines the economic impact of some of the prominent trends in "front end" wafer lab: changes resulting in reduced investment, lower operating costs, and increased output on a per circuit function basis, Automation will be a recurring theme because it has all three effects and, thus, is a very large leverage factor for semiconductor manufacturers. This paper is divided into three major sections: Investment, Operating Costs and Increased Output. Major trends in equipment and lab design will be discussed in relation to each. The investment and operating cost breakdowns are based on a composite of statistics gathered from several semiconductor manufacturers. The numbers are typical of a 5000 5 in wafers per week fab manufacturing 64 K DRAMs. Wafer inspection automation: current and future needs. K. HARRIS,P. SANDLANDand R. SINGLETON.Solid St. Technol. 199 (August 1983). There is a need for micro-pattern inspection of in-process wafers in order to monitor the ongoing pattern quality. In the context of volume wafer production, this need is currently being addressed by a variety of manual and semiautomated equipment. There is a continuing trend towards automation. A profile of current needs and practices as well as possible future solutions to pattern inspection and measurement has been developed after consulting with numerous individuals in the industry. Needs that will develop in the near future and some possible solutions are considered. Computer Aided Processing in the photo area is discussed, Technological advances in physical vapor deposition, GUENTHER HERKLOTZand HANS ELIGEHAUSEN.IEEE Trans. Components Hybrids Mfg Technol. CHMT-6 (2) 173 (June 1983). In the production of contact materials physical vapor deposition (PVD) technology is widely used. After a short description of the different PVD processes, the influences of the most important process parameters on the plating quality will be discussed. Also some technological applications will be cited, Silicon-wafer process evaluation using minority-carrier diffusion-length measurement by the SPV method. A . M . GOODMAN, L. A. GOODMANand H. F. GOSSENBERGER.RCA Ret,. 44, 326 (June 1983). Measurement of the minoritycarrier diffusion length L by the constant-magnitude steadystate surface photovoltage (SPV) method has become an important tool within RCA for evaluating the effect (on L) of silicon device fabrication steps. We present first a simplified description of the method and the practical information required for implementing this measurement technique. Substrate selection, sample preparation, data evaluation, and the limitations of the method are discussed in detail. Next, we describe the use of the SPV technique to monitor the unintentional introduction of heavy metal impurities at five different steps during wafer processing. The causes of wafer contamination are: (1) inadequate wafer cleaning, (2) handling wafers with stainless-steel tweezers, (3) frictional contact between wafers and metallic components in the end stations of ion implanters, (4) a malfunctioning boron-doping source and (5) impurities introduced during epitaxial layer growth. The beneficial effect of adding 1-1-1 trichloroethane (TCA) to a furnace ambient is assessed by using the SPV technique and also by counting the number of crystalline defects delineated with Wright etch.
591
Multilayer-resist lithography. PIETER S. BURGGRAAF.Semiconductor Int. 48 (June 1983). For several years multilayerresist techniques have been developed with the idea of extending the limits of optical aligners. Today, is multilayerresist technology still an R & D effort or is it good for production wafer fabrication 9. Bake effects in positive photoresist. TOM BATCHELDER and Joan PIATT. Solid St. Technol. 211 (August 1983). The advent of in-line hotplate baking of photoresist has made precise adjustment of the resist dissolution rate ratio possible by thermolytic as well as photochemical processes. Post Exposure Bake (PEB) prior to development permits elimination of standing waves, increased contrast and improved adhesion. When this process is coupled with a low temperature resist softbake (~75°C), the disadvantages of PEB, decreased photospeed and reduced critical dimension control can be overcome. When this process is applied, 1.251~m lines and spaces can be obtained over 1.0~tm high oxide steps and 0.8 ~.m equal lines and spaces can be resolved using mature, industry accepted equipment. Critical dimension control is also found to be excellent across the wafer and from wafer to wafer. A novel approach to silicon gate CMOS device scaling. JAN H. KING.Solid St. Electron. 26 (9) 879 (1983). A new approach is reported for fabricating scaled Si-gate CMOS devices using medium temperature ( 2 900°C) LPCVD deposited SiO~ as the dielectric interlayer. The film can be deposited from 850 to 1000°C using a graded temperature profile and optimum pressure. A maximum of 100 wafers with 8 ~ variation of thickness per run has been achieved using the process decribed in this paper. The medium-temperature LPCVD SiO2 film exhibited step-coverage as good as the conventional low temperature PSG film. Since the new film requires no high temperature treatment, the conventional Si-gate CMOS diffusion process has been used to obtain the micron and submicron junction depths that are required to fabricate scaled CMOS devices. Such a processing approach, converting a 5-6~tm geometry CMOS process to a 3 ~m geometry CMOS process, is described. An investigation of the factors that influence the deposit/etch balance in a radiant-heated silicon epitaxial reactor. J. F. CORBOYand R. PAGLIARO,JR., RCA Rev. 44, 231 (June 1983). As the physical dimensions of integrated circuits become smaller and the thickness of the active device regions decreases, epitaxial films of a more perfect crystalline quality are required. High-quality epitaxial deposits can be prepared inthecommerciallyavailableradiant-heatedreactor(Applied Materials AMC-7900). Using the radiant-heated configuration, the thermal gradients normal to the substrate can be minimized. Maintenance in this reactor must be carefully programmed to avoid accumulation of deposits on the reactor bell jar which would attenuate the radiant energy. Despite the drawbacks associated with this approach,, this reactor is widely used in the semiconductor industry where deposits with good crystalline perfection are required. Little is to be found in the literature, however, on the impact of the variables of total gas flow, location of the substrate on the susceptor, and susceptor rotation on the local deposition/etch rates and uniformity of the deposit resistivity. To develop an understanding of these factors, the reactor was operated in an experimental mode with no susceptor rotation. The results of this study and the implications with respect to operation of the reactor in the normal rotating-susceptor mode are discussed.
Imaging latch-up sites in LSI CMOS with a laser photoscanner. DANIELJ. BURNSand JEFFREYM. KENDALL.IEEE 21st Ann. Proc. Reliab. Phys. 118 (1983). A non-destructive laser photoscanning technique has been used to analyze