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Impact of channel doping on Schottky barrier height and investigation on p-SB MOSFETs performance
Materials Science and Engineering B 154–155 (2008) 159–162
Contents lists available at ScienceDirect
Materials Science and Engineering B journal homepage: www.elsevier.com/locate/mseb
Impact of channel doping on Schottky barrier height and investigation on p-SB MOSFETs performance G. Larrieu a,∗ , E. Dubois a , D. Yarekha a , N. Breil a , N. Reckinger b , X. Tang b , J. Ratajczak c , A. Laszcz c a
IEMN, UMR CNRS 8520, Avenue Poincaré, Cité Scientifique, 59652 Villeneuve d’Ascq Cedex, France UCL, Place du Levant, 3, Maxwell Building, B-1348 Louvain-la-Neuve, Belgium c Institute of Electron Technology, Al. Lotników 32/46, 02-668 Warsaw, Poland b
a r t i c l e
i n f o
Article history: Received 5 May 2008 Received in revised form 25 September 2008 Accepted 9 October 2008 Keywords: Schottky barrier MOSFETs Schottky barrier lowering Platinum silicide
a b s t r a c t This paper proposes to study the impact of a moderate variation of the channel doping level on the electrical performance of p-type Schottky-barrier (SB) MOSFETs. First, it has been found that a moderate increase of the acceptors doping level leads to a reduction of the Schottky-barrier height (SBH) but does not affect the silicide reaction. In the case of PtSi, the SBH on p-type silicon at 5 × 1015 cm−3 is 0.15 eV whereas an increase of the doping level by two decades decreases the barrier by 60 meV. The integration of PtSi MOSFETs on moderately doped channel (5 × 1017 cm−3 ) was successfully achieved, demonstrating an overall 60% improvement in current drive at Lg = 100 nm. This enhanced performance is attributed to the barrier height reduction related to the beneficial band bending induced by p-type dopants. The considered doping levels are still in a sufficiently low range not to affect the carrier mobility in the channel. A complete study, including comparison of Ion , Ioff , immunity against short channel effects (Swing and DIBL), is presented. © 2008 Elsevier B.V. All rights reserved.
1. Introduction Metallic source/drain MOSFETs have aroused a renewed interest due to their capabilities to solve challenges associated to S/D CMOS scaling, especially in the case of ultra-thin SOI and multiplegate thin body MOSFETs, owing to its interesting properties (low Rcontact , low Rsheet and infinite abruptness) and drastic process simplification (no S/D implantation). Although, promising results have been reported for p-MOSFETs using platinum silicide (PtSi) [1–3], the gain in S/D sheet resistance has been overwhelmed by the contact resistance at the source/channel interface due to a Schottky barrier (SB) in excess of 0.1 eV. To be competitive, the Schottky barrier height (SBH) should be below 0.1 eV [4] but currently, using PtSi or ErSi2−x , the SBH saturates at 0.15 eV [5], in the best case. Several techniques, including defects passivation using an interfacial layer [6] or dopant segregation [7–9], modulate the SBH to reach the sub-0.1 eV target. However, these techniques lead to an increase of process complexity or to difficulties of integration in a self-aligned process. A moderate variation of the channel doping can have an impact on the Schottky barrier height. Lousberg [10] found that a moderate increase of n-type doping reduced the SBH for electrons
∗ Corresponding author. E-mail address: [email protected] (G. Larrieu). 0921-5107/$ – see front matter © 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2008.10.014
of PtSi/n-Si and had a beneficial effect on the performance of long channel p-SB MOSFETs. This article investigates the impact of the substrate doping level on PtSi/p-Si Schottky barrier height and its influence on the p-MOSFETs performance. 2. Impact of moderate doped substrate on Schottky barrier height We present in this section a study of the impact of the substrate doping level on PtSi/p-Si diodes Schottky barrier height. The samples were fabricated using p-type substrates with doping levels of 1015 , 1016 and 5 × 1017 cm−3 , respectively. A de-oxidation step was used immediately prior silicidation in order to remove the silicon native dioxide. This was classically achieved by dipping samples into a bath of fluorhydric acid (HF:H2 O 1:100), followed by a rinse in de-ionized water and blow dry under a nitrogen flux. Samples were immediately loaded in the evaporation machine. After reaching a load-lock vacuum of 10−7 mbar, samples were submitted to a gentle Ar+ plasma etch at 60 eV for 30 s to definitely remove residual silicon dioxide. Samples were then transferred into the deposition chamber under a base vacuum less than 10−8 mbar. A 15-nm thick layer of platinum was subsequently deposited by ebeam evaporation at a rate of 0.1 nm/s. The silicidation reaction was finally processed by rapid thermal annealing (RTA) at 300 ◦ C for 120 s. No significant difference in the microstructure of the
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silicide layers has been noticed with the doping level of the substrate. From TEM cross sections (not shown), the silicide layers have the same thickness, grain size and interface roughness. The experimental protocol used for the barrier height extraction couples experiments data from back-to-back diodes structures with a transport model including thermionic, tunnel emission and barrier lowering due to image charge induction [5]. For the low substrate doping level (1 × 1015 cm−3 ), a barrier height of 0.15 eV is measured (Fig. 1a). For a moderate doping level (1016 and 5 × 1017 cm−3 ), the barrier height falls below 0.08 eV (Fig. 1b and c). The extracted
silicon resistance, related to the gap between the contacts, also decreases, following the substrate doping level. From a value of 104 at 1015 cm−3 , this resistance decreases to 27 at 1016 cm−3 , and to 12 at 5 × 1017 cm−3 . A moderate change in the substrate doping level translates into a substantial decrease of the barrier height related to the band bending induced by p-type dopants through a mechanism of image force. The exact value of the barrier is difficult to ascertain because current remains limited by the series resistance even at a temperature as low as 110 K. Because our injection model does not predict any current decrease with temperature as far as the barrier remains below 80 meV, this last figure can be considered as an upper bound. 3. Impact of moderate doped substrate on Schottky barrier height This section reports on the impact of a moderate increase of the channel doping level on device performance. We used p-type Unibond SOI wafers with (1 0 0) orientation and a doping concentration of 5 × 1015 cm−3 with an active silicon thickness of 50 nm and a buried oxide (BOX) thickness of 145 nm. Some SOI wafers have been implanted with boron at 10 keV with a dose of 8 × 1012 cm−2 followed by an activation annealing at 1000 ◦ C for 20 min in a nitrogen atmosphere. Under these conditions, the resulting doping level in the SOI layer approaches 5 × 1017 cm−3 . The active SOI layer was subsequently thinned down to 17 nm by chemical etching [11]. The SiO2 gate oxide and the tungsten gate are 2.2 and 60 nm thick,
Fig. 1. Experimental and calculated Arrhenius plot using the thermionic field emission transport model including barrier lowering, for a substrate doping of (a) 1 × 1015 at/cm3 , (b) 1 × 1016 at/cm3 , and (c) 5 × 1017 at/cm3 .
Fig. 2. (a) Measured IDS –VGS (log scale) and (b) IDS –VDS characteristics of 500 nm gate long p-type SB-MOSFET, with PtSi S/D contacts on low and moderate doped SOI channel.
G. Larrieu et al. / Materials Science and Engineering B 154–155 (2008) 159–162
161
Fig. 4. Comparison of Ion and Ioff as a function of gate length obtained on lightly and moderately doped channel devices.
Fig. 3. (a) Measured IDS –VGS (log scale) and (b) IDS –VDS characteristics of 110 nm gate long p-type SB-MOSFET, with PtSi S/D contacts on low and moderate doped SOI channel.
respectively. The spacer width is 15 nm and the S/D PtSi silicide thickness is 12 nm. A forming gas thermal step at 450 ◦ C for 5 min under N2 /H2 was used to anneal out defects. Electrical measurements were performed by probing directly onto the silicide S/D areas. Figs. 2 and 3 present the Id –Vg in logarithmic scale and the Id –Vd curves obtained on devices with gate lengths of 500 nm (Fig. 2) and 110 nm (Fig. 3) on lightly doping (LD) and moderately doping (MD) substrate. A perceptible flattening of the Id –Vg characteristics can be observed at transition between the subthreshold and the weak accumulation regimes for the lightly doped channel. This effect is clearly the signature of an excessively high Schottky barrier height that limits the injection of carriers at the source/channel junction. The sharp down-bending of the Id –Vd curves at low VDS is another manifestation of this effect. Although much less pronounced for a 500 nm gate length, the observation holds also for these characteristic. It is essentially because the channel resistance tends to dominate the total resistance at long gate length. Conversely, the current in aggressively scaled devices is ultimately limited by the contact resistance and is therefore more exposed to a loss of injection efficiency governed by the Schottky potential barrier at the source/channel junction. According to the characteristics obtained with a moderate channel doping, the current level is not limited nor flattened at the transition between the subthreshold and the weak accumulation regime. This remark also holds for the Id –Vd counterpart for which no slope down-bending is detected at low VDS . The improvement brought by the increase of the channel doping
level can be directly related to the reduction of the Schottky barrier height. Note that the reduction of carrier mobility in the channel due to the increase of carrier scattering by ionized impurities is not visible because it is largely compensated by the reduction of the contact resistance. In the case of the 500 nm gate long SB-MOSFET, classical Id –Vg curves, for both channel flavours, are obtained with a subthreshold swing close to the low bound of 60 mV/dec at 300 K and drain induced barrier lowering effect (DIBL) is not observed. The off-state current is maintained in the pA range and an Ion /Ioff ratio exceeding 106 is obtained at Vg = Vd = −1.6 V. The threshold voltage for the moderate doped channel is measured at −0.28 V which is close to the expected value for the tungsten midgap gate (−0.3 V) whereas the threshold voltage for the lightly doped channel is measured at −0.18 V. For a shorter gate length device (110 nm), a good overall performance is maintained for the MD channel device. The characteristic below threshold voltage is not degraded (swing = 72 mV/dec and DIBL = 37 mV/V) and the Ion /Ioff ratio is around 3 × 104 . For the LD channel device, the effect of the SBH on the characteristics becomes predominant. The current injection is limited by the barrier which leads to a drastic reduction of the maximum current drive visible on the Id –Vd characteristics (Fig. 3b).
Fig. 5. Immunity against short channel effects (subthreshold swing and DIBL) as function of gate length obtained on lightly and moderately doped channel devices.
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Fig. 4 shows the on-state and off-state currents as a function of the physical gate length for the LD and MD channels. The variation of Ion follows a typical 1/LG law but data clearly appear to be much less scattered with MD channel when compared to results obtained on a LD substrate. The average Ion trend at Lg = 100 nm is 280 and 180 A/m at Vd = −1.6 V and Vg = −2 V. This figure reveals that the SBH reduction provides a 60% improvement in terms of current drive. The off-state current for the two doping flavours is in the nA range and increases moderately with gate length scaling. Fig. 5 characterizes the immunity against short channel effects. There is no marked difference with results obtained for the lightly doped substrate. The subthreshold swing remains close to the theoretical value of 60 mV/dec at room temperature. DIBL does not increase above 60 mV/V. 4. Conclusion In conclusion, we have demonstrated that a moderate increase of a uniform doping level of p-Si substrate reduces the SBH of PtSi contact below 90 meV due to image charge induction. The formation of the silicide is not affected by the low modification of the doping level. The integration of PtSi p-MOSFETs on moderately doped channel (5 × 1017 cm−3 ) has been achieved, demonstrating an overall 60% improvement in current drive at Lg = 110 nm. The flattening on the Id –Vg characteristics inherent to the SBMOSFET is cured and no current limitation is observed down to 100 nm gate length device. Lastly, immunity against short channel effect seems
to be independent of a moderate increase of the substrate doping level. Acknowledgement This work was supported by European Commission through the METAMOS project (METallic source/drain Architecture for Advanced MOS technology, IST-FP6-016677). References [1] J. Kedzierski, P. Xuan, E.H. Anderson, J. Bokor, T.J. King, C. Hu, IEDM Tech. Dig. (2000) 57–60. [2] G. Larrieu, E. Dubois, IEEE Trans. Electron Device 52 (December) (2005) 2720–2726. [3] M. Fritze, C. Chen, S. Calawa, D. Yost, B. Wheeler, P. Wyatt, C. Keast, J. Snyder, J. Larson, IEEE Electron Device Lett. 25 (4) (2004) 220–222. [4] D. Connelly, C. Faulkner, D.E. Grupp, IEEE Trans. Electron Devices 50 (March) (2004) 98–104. [5] E. Dubois, G. Larrieu, J. Appl. Phys. 96 (July (1)) (2004) 729–737. [6] M. Tao, D. Udeshi, S. Agarwal, E. Maldonado, W.P. Kirk, Solid State Electron. 48 (February (2)) (2004) 335–338. [7] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, J. Koga, Symp. VLSI Technol. 168 (2004). [8] M. Zhang, J. Knoch, Q.T. Zhao, U. Breuer, S. Mantl, Solid State Electron. 50 (2006) 594–600. [9] G. Larrieu, E. Dubois, R. Valentin, N. Breil, F. Danneville, G. Dambrine, J.P. Raskin, J.C. Pesant, Proceedings of the 2007 IEEE International Electron Devices Meeting, IEDM 2007, Washington, DC, USA, December 10–12, 2007, pp. 147–150. [10] G.P. Lousberg, H.Y. Yu, B. Froment, E. Augendre, A. De Keersgieter, A. Lauwers, M.-F. Li, P. Absil, M. Jurczak, S. Biesemans, in: Proceedings of the ESSDERC06. [11] X. Tang, N. Reckinger, G. Larrieu, E. Dubois, D. Flandre, J.P. Raskin, B. Nysten, A.M. Jonas, V. Bayot, Nanotechnology 19 (16) (2008), 165703-1-7.
Contents lists available at ScienceDirect
Materials Science and Engineering B journal homepage: www.elsevier.com/locate/mseb
Impact of channel doping on Schottky barrier height and investigation on p-SB MOSFETs performance G. Larrieu a,∗ , E. Dubois a , D. Yarekha a , N. Breil a , N. Reckinger b , X. Tang b , J. Ratajczak c , A. Laszcz c a
IEMN, UMR CNRS 8520, Avenue Poincaré, Cité Scientifique, 59652 Villeneuve d’Ascq Cedex, France UCL, Place du Levant, 3, Maxwell Building, B-1348 Louvain-la-Neuve, Belgium c Institute of Electron Technology, Al. Lotników 32/46, 02-668 Warsaw, Poland b
a r t i c l e
i n f o
Article history: Received 5 May 2008 Received in revised form 25 September 2008 Accepted 9 October 2008 Keywords: Schottky barrier MOSFETs Schottky barrier lowering Platinum silicide
a b s t r a c t This paper proposes to study the impact of a moderate variation of the channel doping level on the electrical performance of p-type Schottky-barrier (SB) MOSFETs. First, it has been found that a moderate increase of the acceptors doping level leads to a reduction of the Schottky-barrier height (SBH) but does not affect the silicide reaction. In the case of PtSi, the SBH on p-type silicon at 5 × 1015 cm−3 is 0.15 eV whereas an increase of the doping level by two decades decreases the barrier by 60 meV. The integration of PtSi MOSFETs on moderately doped channel (5 × 1017 cm−3 ) was successfully achieved, demonstrating an overall 60% improvement in current drive at Lg = 100 nm. This enhanced performance is attributed to the barrier height reduction related to the beneficial band bending induced by p-type dopants. The considered doping levels are still in a sufficiently low range not to affect the carrier mobility in the channel. A complete study, including comparison of Ion , Ioff , immunity against short channel effects (Swing and DIBL), is presented. © 2008 Elsevier B.V. All rights reserved.
1. Introduction Metallic source/drain MOSFETs have aroused a renewed interest due to their capabilities to solve challenges associated to S/D CMOS scaling, especially in the case of ultra-thin SOI and multiplegate thin body MOSFETs, owing to its interesting properties (low Rcontact , low Rsheet and infinite abruptness) and drastic process simplification (no S/D implantation). Although, promising results have been reported for p-MOSFETs using platinum silicide (PtSi) [1–3], the gain in S/D sheet resistance has been overwhelmed by the contact resistance at the source/channel interface due to a Schottky barrier (SB) in excess of 0.1 eV. To be competitive, the Schottky barrier height (SBH) should be below 0.1 eV [4] but currently, using PtSi or ErSi2−x , the SBH saturates at 0.15 eV [5], in the best case. Several techniques, including defects passivation using an interfacial layer [6] or dopant segregation [7–9], modulate the SBH to reach the sub-0.1 eV target. However, these techniques lead to an increase of process complexity or to difficulties of integration in a self-aligned process. A moderate variation of the channel doping can have an impact on the Schottky barrier height. Lousberg [10] found that a moderate increase of n-type doping reduced the SBH for electrons
∗ Corresponding author. E-mail address: [email protected] (G. Larrieu). 0921-5107/$ – see front matter © 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.mseb.2008.10.014
of PtSi/n-Si and had a beneficial effect on the performance of long channel p-SB MOSFETs. This article investigates the impact of the substrate doping level on PtSi/p-Si Schottky barrier height and its influence on the p-MOSFETs performance. 2. Impact of moderate doped substrate on Schottky barrier height We present in this section a study of the impact of the substrate doping level on PtSi/p-Si diodes Schottky barrier height. The samples were fabricated using p-type substrates with doping levels of 1015 , 1016 and 5 × 1017 cm−3 , respectively. A de-oxidation step was used immediately prior silicidation in order to remove the silicon native dioxide. This was classically achieved by dipping samples into a bath of fluorhydric acid (HF:H2 O 1:100), followed by a rinse in de-ionized water and blow dry under a nitrogen flux. Samples were immediately loaded in the evaporation machine. After reaching a load-lock vacuum of 10−7 mbar, samples were submitted to a gentle Ar+ plasma etch at 60 eV for 30 s to definitely remove residual silicon dioxide. Samples were then transferred into the deposition chamber under a base vacuum less than 10−8 mbar. A 15-nm thick layer of platinum was subsequently deposited by ebeam evaporation at a rate of 0.1 nm/s. The silicidation reaction was finally processed by rapid thermal annealing (RTA) at 300 ◦ C for 120 s. No significant difference in the microstructure of the
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silicide layers has been noticed with the doping level of the substrate. From TEM cross sections (not shown), the silicide layers have the same thickness, grain size and interface roughness. The experimental protocol used for the barrier height extraction couples experiments data from back-to-back diodes structures with a transport model including thermionic, tunnel emission and barrier lowering due to image charge induction [5]. For the low substrate doping level (1 × 1015 cm−3 ), a barrier height of 0.15 eV is measured (Fig. 1a). For a moderate doping level (1016 and 5 × 1017 cm−3 ), the barrier height falls below 0.08 eV (Fig. 1b and c). The extracted
silicon resistance, related to the gap between the contacts, also decreases, following the substrate doping level. From a value of 104 at 1015 cm−3 , this resistance decreases to 27 at 1016 cm−3 , and to 12 at 5 × 1017 cm−3 . A moderate change in the substrate doping level translates into a substantial decrease of the barrier height related to the band bending induced by p-type dopants through a mechanism of image force. The exact value of the barrier is difficult to ascertain because current remains limited by the series resistance even at a temperature as low as 110 K. Because our injection model does not predict any current decrease with temperature as far as the barrier remains below 80 meV, this last figure can be considered as an upper bound. 3. Impact of moderate doped substrate on Schottky barrier height This section reports on the impact of a moderate increase of the channel doping level on device performance. We used p-type Unibond SOI wafers with (1 0 0) orientation and a doping concentration of 5 × 1015 cm−3 with an active silicon thickness of 50 nm and a buried oxide (BOX) thickness of 145 nm. Some SOI wafers have been implanted with boron at 10 keV with a dose of 8 × 1012 cm−2 followed by an activation annealing at 1000 ◦ C for 20 min in a nitrogen atmosphere. Under these conditions, the resulting doping level in the SOI layer approaches 5 × 1017 cm−3 . The active SOI layer was subsequently thinned down to 17 nm by chemical etching [11]. The SiO2 gate oxide and the tungsten gate are 2.2 and 60 nm thick,
Fig. 1. Experimental and calculated Arrhenius plot using the thermionic field emission transport model including barrier lowering, for a substrate doping of (a) 1 × 1015 at/cm3 , (b) 1 × 1016 at/cm3 , and (c) 5 × 1017 at/cm3 .
Fig. 2. (a) Measured IDS –VGS (log scale) and (b) IDS –VDS characteristics of 500 nm gate long p-type SB-MOSFET, with PtSi S/D contacts on low and moderate doped SOI channel.
G. Larrieu et al. / Materials Science and Engineering B 154–155 (2008) 159–162
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Fig. 4. Comparison of Ion and Ioff as a function of gate length obtained on lightly and moderately doped channel devices.
Fig. 3. (a) Measured IDS –VGS (log scale) and (b) IDS –VDS characteristics of 110 nm gate long p-type SB-MOSFET, with PtSi S/D contacts on low and moderate doped SOI channel.
respectively. The spacer width is 15 nm and the S/D PtSi silicide thickness is 12 nm. A forming gas thermal step at 450 ◦ C for 5 min under N2 /H2 was used to anneal out defects. Electrical measurements were performed by probing directly onto the silicide S/D areas. Figs. 2 and 3 present the Id –Vg in logarithmic scale and the Id –Vd curves obtained on devices with gate lengths of 500 nm (Fig. 2) and 110 nm (Fig. 3) on lightly doping (LD) and moderately doping (MD) substrate. A perceptible flattening of the Id –Vg characteristics can be observed at transition between the subthreshold and the weak accumulation regimes for the lightly doped channel. This effect is clearly the signature of an excessively high Schottky barrier height that limits the injection of carriers at the source/channel junction. The sharp down-bending of the Id –Vd curves at low VDS is another manifestation of this effect. Although much less pronounced for a 500 nm gate length, the observation holds also for these characteristic. It is essentially because the channel resistance tends to dominate the total resistance at long gate length. Conversely, the current in aggressively scaled devices is ultimately limited by the contact resistance and is therefore more exposed to a loss of injection efficiency governed by the Schottky potential barrier at the source/channel junction. According to the characteristics obtained with a moderate channel doping, the current level is not limited nor flattened at the transition between the subthreshold and the weak accumulation regime. This remark also holds for the Id –Vd counterpart for which no slope down-bending is detected at low VDS . The improvement brought by the increase of the channel doping
level can be directly related to the reduction of the Schottky barrier height. Note that the reduction of carrier mobility in the channel due to the increase of carrier scattering by ionized impurities is not visible because it is largely compensated by the reduction of the contact resistance. In the case of the 500 nm gate long SB-MOSFET, classical Id –Vg curves, for both channel flavours, are obtained with a subthreshold swing close to the low bound of 60 mV/dec at 300 K and drain induced barrier lowering effect (DIBL) is not observed. The off-state current is maintained in the pA range and an Ion /Ioff ratio exceeding 106 is obtained at Vg = Vd = −1.6 V. The threshold voltage for the moderate doped channel is measured at −0.28 V which is close to the expected value for the tungsten midgap gate (−0.3 V) whereas the threshold voltage for the lightly doped channel is measured at −0.18 V. For a shorter gate length device (110 nm), a good overall performance is maintained for the MD channel device. The characteristic below threshold voltage is not degraded (swing = 72 mV/dec and DIBL = 37 mV/V) and the Ion /Ioff ratio is around 3 × 104 . For the LD channel device, the effect of the SBH on the characteristics becomes predominant. The current injection is limited by the barrier which leads to a drastic reduction of the maximum current drive visible on the Id –Vd characteristics (Fig. 3b).
Fig. 5. Immunity against short channel effects (subthreshold swing and DIBL) as function of gate length obtained on lightly and moderately doped channel devices.
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Fig. 4 shows the on-state and off-state currents as a function of the physical gate length for the LD and MD channels. The variation of Ion follows a typical 1/LG law but data clearly appear to be much less scattered with MD channel when compared to results obtained on a LD substrate. The average Ion trend at Lg = 100 nm is 280 and 180 A/m at Vd = −1.6 V and Vg = −2 V. This figure reveals that the SBH reduction provides a 60% improvement in terms of current drive. The off-state current for the two doping flavours is in the nA range and increases moderately with gate length scaling. Fig. 5 characterizes the immunity against short channel effects. There is no marked difference with results obtained for the lightly doped substrate. The subthreshold swing remains close to the theoretical value of 60 mV/dec at room temperature. DIBL does not increase above 60 mV/V. 4. Conclusion In conclusion, we have demonstrated that a moderate increase of a uniform doping level of p-Si substrate reduces the SBH of PtSi contact below 90 meV due to image charge induction. The formation of the silicide is not affected by the low modification of the doping level. The integration of PtSi p-MOSFETs on moderately doped channel (5 × 1017 cm−3 ) has been achieved, demonstrating an overall 60% improvement in current drive at Lg = 110 nm. The flattening on the Id –Vg characteristics inherent to the SBMOSFET is cured and no current limitation is observed down to 100 nm gate length device. Lastly, immunity against short channel effect seems
to be independent of a moderate increase of the substrate doping level. Acknowledgement This work was supported by European Commission through the METAMOS project (METallic source/drain Architecture for Advanced MOS technology, IST-FP6-016677). References [1] J. Kedzierski, P. Xuan, E.H. Anderson, J. Bokor, T.J. King, C. Hu, IEDM Tech. Dig. (2000) 57–60. [2] G. Larrieu, E. Dubois, IEEE Trans. Electron Device 52 (December) (2005) 2720–2726. [3] M. Fritze, C. Chen, S. Calawa, D. Yost, B. Wheeler, P. Wyatt, C. Keast, J. Snyder, J. Larson, IEEE Electron Device Lett. 25 (4) (2004) 220–222. [4] D. Connelly, C. Faulkner, D.E. Grupp, IEEE Trans. Electron Devices 50 (March) (2004) 98–104. [5] E. Dubois, G. Larrieu, J. Appl. Phys. 96 (July (1)) (2004) 729–737. [6] M. Tao, D. Udeshi, S. Agarwal, E. Maldonado, W.P. Kirk, Solid State Electron. 48 (February (2)) (2004) 335–338. [7] A. Kinoshita, Y. Tsuchiya, A. Yagishita, K. Uchida, J. Koga, Symp. VLSI Technol. 168 (2004). [8] M. Zhang, J. Knoch, Q.T. Zhao, U. Breuer, S. Mantl, Solid State Electron. 50 (2006) 594–600. [9] G. Larrieu, E. Dubois, R. Valentin, N. Breil, F. Danneville, G. Dambrine, J.P. Raskin, J.C. Pesant, Proceedings of the 2007 IEEE International Electron Devices Meeting, IEDM 2007, Washington, DC, USA, December 10–12, 2007, pp. 147–150. [10] G.P. Lousberg, H.Y. Yu, B. Froment, E. Augendre, A. De Keersgieter, A. Lauwers, M.-F. Li, P. Absil, M. Jurczak, S. Biesemans, in: Proceedings of the ESSDERC06. [11] X. Tang, N. Reckinger, G. Larrieu, E. Dubois, D. Flandre, J.P. Raskin, B. Nysten, A.M. Jonas, V. Bayot, Nanotechnology 19 (16) (2008), 165703-1-7.