Impact of gate dielectric constant variation on tunnel field-effect transistors (TFETs)

Solid-State Electronics 116 (2016) 88–94

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Impact of gate dielectric constant variation on tunnel field-effect transistors (TFETs) Seung Kyu Kim, Woo Young Choi ⇑ Department of Electronic Eng., Sogang Univ., 1 Sinsu-dong, Mapo-gu, Seoul 04107, Republic of Korea

a r t i c l e

i n f o

Article history: Received 12 August 2015 Received in revised form 5 November 2015 Accepted 29 November 2015 Available online 17 December 2015 Keywords: Tunnel field effect transistors (TFETs) High-j material Variation Gate dielectric constant variation

a b s t r a c t The influence of gate dielectric constant variation on tunnel field-effect transistors (TFETs) has been investigated. High-j materials in polycrystalline nature induce localized gate dielectric constant variation. According to the simulation results, TFETs show larger standard deviation of threshold voltage (Vth), subthreshold swing (SS) and saturation current (Id,sat) than metal–oxide–semiconductor FETs (MOSFETs). It has been revealed that local gate dielectric constant variation should be considered to evaluate the total variation of TFETs. This is because the gate insulator near the source region dominates TFET performance. Also, the ideas have been proposed in order to reduce the gate dielectric constant variation. Ó 2015 Elsevier Ltd. All rights reserved.

1. Introduction A tunnel field-effect transistor (TFET) has been considered as one of the most promising emerging electron devices. It shows smaller sub-threshold swing (SS) and lower power consumption than a metal–oxide–semiconductor FET (MOSFET) [1–3]. However, low on-current makes the commercialization of TFETs difficult. One solution to boosting on-current is the introduction of high-j materials to gate insulator [4]. It has been reported that amorphous high-j gate dielectric can be converted into polycrystalline phase during post-deposition annealing treatments [5,6]. It induces a new performance variation source: gate dielectric constant variation. This manuscript investigates the influence of ‘‘localized” gate dielectric constant variation of TFETs due to the polycrystalline nature of high-j materials for the first time. This work is different than previous studies in that they discussed ‘‘global” gate dielectric constant variation of TFETs [4,7]. Each grain has a random orientation which leads to the dielectric constant variation [8–10]. Thus, the equivalent oxide thickness (EOT) of gate insulator varies over the channel region, which results in the variation of SS, turn-on voltage (VTurn-on), threshold voltage (Vth) and saturation current (Id,sat) of TFETs. Because TFETs show larger SS variation than MOSFETs, VTurn-on has been introduced for TFETs in order to evaluate the effects exclusive of SS variation [11]. VTurn-on is defined as the gate voltage (VG) when drain current

⇑ Corresponding author. Tel.: +82 705 8467; fax: +82 2 705 8467. E-mail address: [email protected] (W.Y. Choi). http://dx.doi.org/10.1016/j.sse.2015.11.037 0038-1101/Ó 2015 Elsevier Ltd. All rights reserved.

exceeds leakage current (Ileak). The definitions of Vth, Voff, VTurn-on, SS and Id,sat are summarized in Table 1. In this paper, from the viewpoint of the standard deviation of SS (rSS), VTurn-on (rVTurn-on) and Vth (rVth), the gate dielectric constant variation of TFETs will be investigated with the variation of the grain size of high-j materials (Lgrain), the standard deviation of dielectric constant (rj) and the physical thickness of an interfacial layer (tSiO2). 2. Model derivation Fig. 1a and b shows the simulated structure of a silicon-oninsulator (SOI) TFET and a MOSFET, respectively. Three dimensional device simulation has been performed by using Synopsys Sentaurus [12]. Nonlocal band-to-band tunneling, Oldslotboom model for band-gap narrowing, Shockley–Read–Hall (SRH) recombination, and Fermi–Dirac model have been used [13]. Since the quantization effects push the carriers away from the semiconductor–oxide interface in the silicon thin film, the modified local density approximation (MLDA) model have been applied to calculate the confined carrier distributions that occur near semiconductor– oxide interfaces [14]. The band-to-band tunneling model has been carefully calibrated referring to the experimental data [15]. Device design parameters of the simulated structures are summarized in Table 2. For fair comparison between a TFET and a MOSFET, they have the same device parameters except for the three parameters: source doping type, channel doping concentration and gate workfunction. Different source doping types are attributed to different device operating principles. A MOSFET has higher channel doping

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S.K. Kim, W.Y. Choi / Solid-State Electronics 116 (2016) 88–94 Table 1 Performance parameter definitions for TFETs and MOSFETs. Vth Voff VTurn-on SS Id,sat

Vth is defined as VG when ID = Ith = 10 nA/lm Voff is defined as VG when ID = Ith = 0.1 nA/lm VTurn-on is defined as VG when ID exceeds Ileak SS calculated as SSeff = (Vth Voff)/log(Ith/Ioff) ID extracted at VD = VG = 1.0 V

concentration than a TFET in order to suppress short-channel effects [11]. The gate work-function of a TFET is adjusted higher than that of a MOSFET in order to make VTurn-on higher than 0 V. In this manuscript, it has been assumed that the dielectric constants of grains are distributed in a Gaussian profile within 3r due to the lack of experimental data from literature. Generated dielectric constants are allocated for individual grains to reflect random grain orientation fluctuation [8]. Although there are various grain shapes and sizes in experimental cases, the same-sized grains are assumed in order to focus on gate dielectric constant variation effects. Thus, the length of grain (Lgrain) represents the grain size. Fig. 1c shows an example of generated dielectric constant profiles following Gaussian distribution shown in Fig. 1d. Fig. 2 shows the transfer curves of 100 generated TFET and MOSFET samples at low and high drain voltage (VD), respectively, when Lgrain is 14 nm, rj is 2.5 and tSiO2 is 0 nm referring to the experimental data [16–18]. Table 3 summarizes the extracted rVth, rVTurn-on, rSS and r(log(Id,sat)) values. Interestingly, the value of rVth’s in TFETs are 15.76 mV and 10.70 mV at low and high VD, respectively, which are much higher than MOSFETs. Also, the gate dielectric constant variation of TFETs is comparable with other variation resources [11,22]. It means that a local gate dielectric constant variation is an important issue in the case of TFETs, which is contrary to the long channel MOSFET case [8]. It should be noted that TFET shows much larger rVth value than rVTurn-on value due to their large rSS. TFETs show larger rSS than MOSFETs, which is originated from lateral energy band profile modulation effects [19]. Some

analogous studies were reported using hetero-gate-dielectric TFETs [7,20]. The gate dielectric constant variation induces the localized fluctuation of gate-to-channel capacitance and energy band profiles. Both of them lead to lateral energy band profile modulation effects on channel region. Because TFETs utilize band-to-band tunneling at a narrow source-to-channel junction region, it results in the fluctuation of tunneling barrier width (Wb) on which band-to-band tunneling current is exponentially dependent. It has been reported that the SS of TFETs is much related to the transition abruptness of Wb [20]. Thus, SS of TFETs are more susceptible to energy band distortion induced by gate dielectric constant variation than that of MOSFETs. In the same sense, the fluctuation of Wb leads to larger Id,sat variation in TFETs [21,22]. We extracted r. (g(Id,sat)) to evaluate the saturation current variation as well as r(log(Id,sat)) of TFETs, which showed larger value than MOSFETs as shown in Table 3. In the second place, rVturn-on of TFETs is compared with rVth of MOSFETs in order to evaluate the gate dielectric constant variation effects without regard to large rSS of TFETs. As shown in Table 2,

Table 2 Device design parameters. TFET Channel length (Lch) Channel width (Wch) High-j material thickness (thigh-j) SOI layer thickness (tSOI) Drain doping concentration Source doping concentration Channel doping concentration Gate work-function

MOSFET 56 nm 56 nm 6 nm 15 nm 20

10

cm

3

(n-type)

1020 cm

3

(p-type)

1020 cm

1016 cm

3

(p-type)

2  1018 cm

4.20 eV

3

(n-type) 3

(p-type)

4.06 eV

Fig. 1. Simulation structure of (a) a TFET and (b) a MOSFET. (c) One example of generated dielectric constant profiles when Lgrain is 7 nm. (d) Gaussian distribution of dielectric constant values.

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Fig. 2. Transfer curves of the randomly generated 100 TFET and MOSFET samples (dark gray lines). The case of (a) TFETs at VD = 0.1 V, (b) TFETs at VD = 1.0 V, (c) MOSFETs at VD = 0.1 V and (d) MOSFETs at VD = 1.0 V. Black lines are extracted from control devices which have no gate dielectric constant variation.

rVturn-on of TFETs is larger than rVth of MOSFETs. It is because Vth of

Table 3 Parameter variation of TFETs and MOSFETs.

rVth(low VD) rVth(high VD) rVTurn-on(low VD) rVTurn-on(high VD) rSS(low VD) rSS(high VD) r(log(Id,sat))

TFETs

MOSFETs

15.76 mV 10.70 mV 3.68 mV 2.77 mV 4.97 mV/decade 3.27 mV/decade 0.062

2.59 mV 2.47 mV – – 0.39 mV/decade 0.35 mV/decade 0.010

Note: Low VD means 0.1 V while high VD means 1.0 V.

MOSFETs is determined by average gate dielectric constant of the whole channel area while only the dielectric constant values near the source-to-channel junction determines rVturn-on of TFETs due to band-to-band tunneling occurring at narrow area of the channel between channel and source region. Fig. 3 shows the twodimensional vector field of TFETs and MOSFETs current flow in the case of generated dielectric constant profile. Fig. 3b shows the contour of current density of TFETs at VG around Vturn-on of TFETs and Fig. 3c shows the contour of current density of MOSFETs at VG around Vth of MOSFETs. Fig. 3d and e represent the twodimensional vector field of TFET and MOSFET current flow. A TFET

Fig. 3. (a) One example of generated dielectric constant profiles when Lgrain is 14 nm. Current density contours of (b) a TFET and (c) a MOSFET at VD = 0.1 V and VG = 0.2 V. The dashed areas correspond to Fig. 3a. Two-dimensional current vector field of dashed area in (d) a TFET and (e) a MOSFET, respectively.

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Fig. 4. Dielectric constant distributions of (a) the lowest and (b) the highest Vth case out of the 100 TFET samples. Dielectric constant distributions of (c) the lowest and (d) the highest Vth case out of the 100 MOSFET samples.

Fig. 5. The uniplanar contours of conduction band profiles corresponding the dielectric constant variations from Fig. 4 at VG around Vth (VG = 0.4 V). The localized gate-tochannel capacitance variation induces localized fluctuations of conduction bands. (a) The lowest and (b) the highest Vth case out of the 100 TFET samples and (c) the lowest and (d) the highest Vth case out of the 100 MOSFET samples.

shows the highest current density around a portion of source-tochannel junction whose dielectric constant is the highest because the TFET current mainly flows through the narrowest tunneling barrier. Moreover, the TFET current flow is rarely affected by the dielectric constants over the channel region. It shows the local gate

dielectric constant placed around the source-to-channel junction region is critical to rVturn-on. Likewise, in the case of MOSFETs, the surface channel barrier under the grains with low gate dielectric constant becomes high and the current flow is routed around high surface barrier. However, the MOSFET current flow is affected

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Fig. 6. Correlation and correlation coefficient between average j on the whole channel region and Vth in (a) the TFET and (b) the MOSFET samples, respectively. Correlation and correlation coefficient between average j of the region near to the source-channel junction and Vth in (c) the TFET and (d) the MOSFET samples, respectively. Near to the source-channel junction means that it is within 14 nm, which is the size of the single grain used for the simulation.

by the gate dielectric constant variation over the wide area of the channel. Thus, Vth of MOSFETs can be easily averaged out than Vturn-on of TFETs due to average-out effects. Fig. 2 and Table 3 show that rVth and rSS increase as VD decreases. It is because the tunneling junction is more controlled by the gate through the gate dielectrics under low VD. However, the tunneling junction is controlled relatively more by drain without going through the gate oxide under high VD. Fig. 4 shows the extreme cases out of the 100 TFET and MOSFET samples. Also, Fig. 5 shows the uniplanar contours of conduction band profiles corresponding the dielectric constant variations from Fig. 4 at VG around Vth. Fig. 5a and b shows the gate dielectric constant distributions of the lowest and highest Vth case of TFETs, respectively. They also represent the cases of the smallest and the largest SS. If grains with high dielectric constant are located concentrically near the source-to-channel junction region, conduction band of channel under those grains becomes low as shown in Fig. 5a and b. It results in abrupt changes of Wb as a function of VG. Average gate dielectric constant values near the source-to-channel junction region determine SS and drain current. Likewise, in the case of MOSFETs, the gate dielectric constant variation induces the localized fluctuation of gate-to-channel capacitance and energy band profiles. As mentioned before, Fig. 5c and d represent the surface channel barrier under the grains when a high gate dielectric constant becomes low [8]. However, the gate dielectric constant variation over the wide area of the channel affects MOSFET performance variation. Fig. 4c and d show the gate dielectric constant distributions of the lowest and highest Vth case of MOSFETs,

respectively. They represent the cases when the average gate dielectric constant values over the channel are the largest and smallest, respectively. Thanks to this average-out effect, MOSFETs are more robust to gate dielectric constant variation than TFETs. Fig. 6a and b shows the correlation between Vth and the average dielectric constant of the whole channel region of TFETs and MOSFETs, respectively. MOSFETs show higher correlation than TFETs. On the other hands, as shown in Fig. 6c and d, TFETs show higher correlation between Vth and the average dielectric constant near to the source-to-channel junction than MOSFETs. In order to suppress the gate dielectric constant variation of TFETs, a few device parameters have been adjusted: Lgrain, rj and tSiO2. Fig. 7 shows rVTurn-on of TFETs and rVth of MOSFETs are robust to gate dielectric constant variation and smaller than rVth of TFETs. rVth of TFETs can be reduced by lowering rSS. First, Fig. 7a and d shows rVth and rSS with the variation of Lgrain, respectively. As grains become smaller, the number of grains around the source-to-channel junction region increases and gate dielectric constant variation becomes more averaged out, which means smaller rVth. Second, Fig. 7b and e shows rVth and rSS with the variation of rj. The reduction of rj leads to narrower distribution of gate dielectric constant. It makes both rSS and rVth smaller. Last, in terms of tSiO2, two independent effects compete with each other. As tSiO2 increases, SS degrades due to increase of EOT, which is reflecting the increasing portion of rSS. In the same situation, the portion of the high-j materials to EOT becomes smaller and this causes the reducing portion of rSS. The different trends between low VD and high VD when tSiO2 is smaller than 0.4 nm are because

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Fig. 7. Trends of rVth with respect to (a) grain size, (b) rj and (c) tSiO2. Trends of rSS with respect to (d) grain size, (e) rj and (f) tSiO2.

Fig. 8. Variation of rVth, rVturn-on and rSS depending on the downscaling of TFETs and MOSFETs at VD = 0.1 V and 1.0 V. (a) rVth, rVTurn-on and (b) rSS in the case of co-scaling of gate length (Lch) and width (Wch). (c) rVth, rVTurn-on and (d) rSS in the case of gate-length-only scaling. (e) rVth, rVTurn-on and (f) rSS in the case of gate-width-only scaling.

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of the increasing portion is greater than reducing portion in low VD while it is opposite in high VD. SS variation is more sensitive due to higher gate controllability under low VD. Although these trends become same when tSiO2 is larger than 0.4 nm as the portion of the high-j materials to EOT decreases sufficiently, Fig. 7c and f shows that tSiO2 adjustment is not an effective solution to gate dielectric constant variation at the sacrifice of on-current. When Lgrain, rj and tSiO2 are optimized to be 4 nm, 1.0 and 0 nm, respectively, rVth of TFETs at low and high VD become 3.99 and 2.41 mV, respectively. Fig. 8 shows the influence of gate dielectric constant variation on TFETs and MOSFETs as device size becomes smaller. Fig. 8a and b shows rVth, rVTurn-on and rSS when both gate length and width vary in proportion. As both dimensions decrease, local gate dielectric constant variation effects worsen. For more detailed analysis, Fig. 8c and d shows the case of gate-length-only scaling while Fig. 8e and f shows the case of gate-width-only scaling. In the case of MOSFETs, both gate length scaling and gate width scaling affect the local gate dielectric constant variation. It is because the rVth of MOSFETs are determined by whole channel region. In otherwise, it is observed that only the gate width scaling affects local gate dielectric constant variation effects of TFETs. It can be explained by the fact that the dielectric constant values near the source region determines rVTurn-on and rSS of TFETs. In the case of TFETs, gate-width scaling changes the area of the source-near region unlike gate-length-scaling.

3. Summary Local gate dielectric constant variation effects due to the random grain orientation of high-j dielectrics have been discussed. It is observed that TFETs are more sensitive to local gate dielectric constant variation than MOSFETs. It is because band-to-band tunneling occurring in a narrow area of the channel induces larger rSS. Unlike MOSFETs, in the case of TFETs, local gate dielectric constant variation should be considered for the accurate evaluation of performance variation. In order to reduce the local gate dielectric constant variation, the deposition and annealing process of high-j materials needs to be improved to achieve the reduction of Lgrain and rj.

Acknowledgments This work was supported in part by the NRF of South Korea funded by the MSIP under Grant NRF-2015003565 (Mid-Career Researcher Program) and in part by the MOTIE/KSRC under Grant 10044842 (Future Semiconductor Device Technology Development Program).

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