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Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer
Microelectronics Reliability 54 (2014) 1712–1717
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer K. Shubhakar a,b,c,⇑, N. Raghavan a, S.S. Kushvaha c,1, M. Bosman c, Z.R. Wang b, S.J. O’Shea c, K.L. Pey a a
Singapore University of Technology and Design (SUTD), Singapore 138682, Singapore Division of Microelectronics, School of EEE, Nanyang Technological University (NTU), Singapore 639798, Singapore c Institute of Materials Research and Engg. (IMRE), A*STAR, 3 Research Link, Singapore 117602, Singapore b
a r t i c l e
i n f o
Article history: Received 30 July 2014 Accepted 31 July 2014 Available online 1 September 2014 Keywords: High-j Dielectric Nanoscale characterization Grain boundaries Interfacial layer Reliability
a b s t r a c t Using nanometer-resolution characterization techniques, we present a study of the local structural and electrical properties of grain boundaries (GBs) in polycrystalline high-j (HK) dielectric and their role on the reliability of underlying interfacial layer (IL). A detailed understanding of this analysis requires characterization of HK/IL dielectrics with nanometer scale resolution. In this work, we present the impact of surface roughness, thickness and GBs containing high density of defects, in polycrystalline HfO2 dielectric on the performance of underlying SiOx (x 6 2) IL using atomic force microscopy and simulation (device and statistical) results. Our results show SiOx IL beneath the GBs and thinner HfO2 dielectric experiences enhanced electric field and is likely to trigger the breakdown of the SiOx IL. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction
2. Experiments
The analysis of degradation and breakdown (BD) phenomenon in polycrystalline HfO2/SiOx dielectric stack is complex due to the polycrystalline, defective nature of HfO2 and the presence of SiOx interfacial layer (IL). Grain boundaries (GBs) in polycrystalline high-j (HK) dielectrics contain high density of electrically active defects, which results in locally varying electrical properties. The GBs favors accumulation of traps, triggering formation of percolation path [1–4]. These GBs pose a major concern in the reliability of HK and IL in dielectric stacks in advanced CMOS technology. Hence, a detailed understanding on the role of GB in the degradation and breakdown of HK and IL layers is essential. As the degradation and eventual BD in dielectric stacks occur locally at a nanometer length scale, it is essential to study the individual layers in dielectric stacks at a nano-level resolution. Atomic force microscopy (AFM) is used extensively for the characterization of thin HK dielectrics with nanometer resolution [5–8]. In this work, AFM is used as a nanoscale characterization tool to study the effect of GBs on underlying SiOx IL in the HfO2/SiOx dielectric stack.
In this work, AFM has been used to characterize the morphology and electrical properties of the HfO2/SiOx dielectric stacks. AFM experiments were carried out in ultra-high vacuum (1010 Torr). Post-deposition annealed (600 °C) HfO2 (4–5 nm)/SiOx (1 nm)/ Si samples, which were fabricated using atomic layer deposition, were used in this study. Si and conducting platinum-wire AFM tips (apex diameter 50 nm) were used in tapping mode and conductive-AFM (C-AFM), respectively. The topography, current profile, spectroscopy (current–voltage (I–V) and current–time (I–t) trends) obtained from AFM experiments were used to analyze the role of GBs on the performance of underlying SiOx IL. COMSOL Multiphysics [9], a finite element method simulation tool, was used in our work for a two dimensional (2-D) simulation study of the electrical potential distribution at the grain and GB locations in HfO2 and the corresponding locations at the underlying SiOx IL. A Kinetic Monte Carlo (KMC) model considering the thermodynamics and kinetics of bond breaking was applied to simulate the time-dependent generation of oxygen vacancy defects in the dual-layer stack considering the modified rate of vacancy generation at the GB region due to enhanced local permittivity (higher vacancy concentration increases local material permittivity [10,11]).
⇑ Corresponding author at: Singapore University of Technology and Design (SUTD), Singapore 138682, Singapore. Tel.: +65 9086 3660. E-mail address: [email protected] (K. Shubhakar). 1 Present address: CSIR National Physical Laboratory, New Delhi 110012, India. http://dx.doi.org/10.1016/j.microrel.2014.07.154 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
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3. Results and discussion 3.1. Experimental results A TEM cross-section of a metal/HfO2 (4–5 nm)/SiOx (1 nm)/ Si structure in Fig. 1(a) shows the morphology of the polycrystalline HfO2 dielectric. A thin layer of SiOx (1 nm) was formed at the interface of the HfO2 and Si during post-annealing process. Fig. 1(b) shows the tapping mode-AFM image of the surface of the annealed (600 °C) HfO2 dielectric films over a 300 300 nm2 area, showing a granular surface roughness. The increase in the surface roughness with annealing is believed to be due to the effect of polycrystallization nature of the HfO2 dielectric. Fig. 1(c) shows a schematic of the effect of surface roughness variation in HfO2 on SiOx IL. The IL region which experiences enhanced electric field due to the thinner HfO2 is highlighted (dotted square region) in Fig. 1(c). Fig. 2(a) shows the line profile of the HfO2 dielectric film along the line X1–X2 in Fig. 1(b), indicative of the morphological inhomogeneity. The larger thickness fluctuation after the annealing [12] could affect the performance and reliability of the HK dielectric. Variation of the surface roughness of the HK film can affect not only the local voltage drop across HK, but also across the underlying IL in the HK/IL dielectric stack. The voltage drop across the HK layer (VHK) and the IL layer (VIL) are approximately given by Eqs. (1) and (2), respectively, where tIL and tHK are the physical thicknesses of the IL and HK layer respectively, k is the relative permittivity and Vox is the overall voltage drop across the HK/IL dielectric stack (Vox = VIL + VHK) [13].
1 kHK tIL þ 1 kIL t HK 1 kIL t HK þ 1 V IL ¼ V ox kHK t IL
V HK ¼ V ox
Fig. 2. (a) Line profiles of topography along the line, X1–X2 and (b) variation of the voltage across HK (HfO2) and IL (SiOx) with HK thickness variation. Dotted vertical line represents the expected thickness (4 nm) of the HfO2.
ð1Þ ð2Þ
The calculated voltage drop across HK layer and IL layer with
jHK = 25 for HfO2 and jIL = 3.9 for SiO2 IL (used to simulate our SiOx) is shown in Fig. 2(b). Data shows there is a much higher elec-
tric field across the thinner IL (SiOx) than the HK (HfO2) layer, and that thickness variations result in inhomogeneous distribution of voltage across the SiOx IL. In particular, the SiOx IL below the physically thinner HfO2 experiences enhanced electric field and could initiate the degradation of the SiOx IL, influencing the BD event at this location.
Fig. 1. (a) TEM micrograph and (b) tapping-mode AFM image of HfO2 (4–5 nm)/SiOx (1 nm) on Si-substrate, annealed at 600 °C. (c) Schematic showing the effect of thinner HfO2 on underlying SiOx IL layer. Dotted square region represents the enhanced electric field at SiOx IL due to thinner HfO2.
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In C-AFM, the conducting Pt-wire tip senses the electrical information of the dielectric at every pixel while scanning the topographical image, with a constant voltage bias applied to the sample. Hence, the topographical and electrical properties of the dielectric can be collected simultaneously at the nanometer length scale. Fig. 3(a) and (b) shows C-AFM topography and corresponding current map of the HfO2/SiOx dielectric stack obtained at a bias of +5 V. Bright spots on the C-AFM current map as shown in Fig. 3(b) at the GB locations correspond to the depressed locations on the topographical image (Fig. 3(a)). The results clearly show an increased leakage current at the GB locations (white dashed lines) due to enhanced TAT through the high concentration of pre-existing traps present at the GBs. Fig. 3(c) shows a schematic representing the effect of thinner HfO2 and lower resistance at GBs on underlying SiOx IL in the HfO2/SiOx stack. Both effects lead to enhanced field across the IL directly below the GB (dotted square region). The breakdown strength of the HfO2/SiOx dielectric stack was examined via ramped voltage stress (RVS) using C-AFM. During RVS, the bias voltage was ramped from 0 to +6 V. RVS was done at different locations of the dielectric sample. An example of this I–V characteristic inhomogeneity is shown in Fig. 4(a) which illustrates the non-uniform electrical characteristics of the HfO2/SiOx stack. It appears that the locations with higher conductivity are GBs. Fig. 4(b) shows a plot of constant voltage stressing (CVS) at +6 V on different locations consisting of grain and GB regions, and shows that the degradation and BD occur relatively faster at a number of locations that were probably (the tip will drift during the experiment, so the location is slightly uncertain) close to or on the GBs [12]. Fig. 5(a) and (b) show the topography and current map in a first scan obtained at +6 V, respectively. Fig. 5(c) and (d) shows the current maps over the same area in the subsequent sec-
ond and third scans, respectively (at +6 V). The magnitude of the leakage current and conducting region along the GB increases upon uniform stressing, indicating a higher rate of stress-induced trap generation compared to the grain regions. Fig. 6(a) shows a quantitative analysis of the C-AFM leakage current images and clearly shows an increase in the leakage current and faster degradation along the GBs upon stressing and supports the results shown in Fig. 4. Fig. 6(b) shows the voltage across HfO2 and SiOx layers near grain and GB regions of HfO2 upon stressing and it is observed that the voltage across the SiOx IL underneath the GB increases at a faster rate than that of below the grain region. The voltages across HfO2 and SiOx were estimated with respect to the degradation rates S1 and S2 at the grain and GB of HfO2 layer, respectively (considering the voltage across the HfO2 layer is inversely proportional to the conductance observed in Fig. 6(a)). Higher trap generation rate at the GBs on successive scans compared to that of grain regions indicates enhanced degradation of SiOx IL underlying GBs leading to earlier BD at these locations [12]. 3.2. Simulation results The electrical properties of grains and GBs were analyzed using simulation of the electrical potential distribution at the grain and GB locations in HK and the corresponding locations at the underlying IL. The 2-D ‘‘Electrostatics’’ application mode in COMSOL Multiphysics tool [9] was used for our simulation study. The software provides a computer aided design interface to define the geometry, a sophisticated mesh generation capability, and solves for potential and electric field over a defined geometric domain [9]. Here, the effect of GBs on the thin underlying SiOx IL is demonstrated with the help of a 2-D structure of HfO2/SiO2 with a top metal electrode and Si substrate, and a voltage bias of +1.5 V applied to the top
Fig. 3. (a) C-AFM topography, (b) corresponding current map (at +5 V) of HfO2/SiOx dielectric stack depicting the grain and GB profile. (c) Schematic showing the effect of thinner HfO2 and larger defect density at GBs. Both effects lead to enhanced field across the SiOx IL underneath the GBs (dotted square region).
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Fig. 4. (a) C-AFM I–V characteristics at different locations on the dielectric and (b) leakage current evolution with time under constant voltage stress of +6 V at different locations on the dielectric [12].
metal electrode. The schematic of the HfO2/SiO2 dielectric stack model is shown in Fig. 7(a). The GB in the HfO2 dielectric was modeled with a higher permittivity (j1 = 30 for GB1 and 35 for GB2) than that of grain regions (j2 = 25) [14]. GB1 shows slightly more conductivity than GB2. The permittivity of the SiO2 layer (j3) is
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Fig. 6. (a) Degradation rate at grain and GB with successive scans (upon stressing). The data (distribution of leakage current over a 5 5 nm2 area of Fig. 5) was normalized to the minimum current (50 pA) observed over the grain region on the first scan. (b) Voltage across HfO2 and SiOx at grain and GB locations with successive scans.
Fig. 5. (a) CAFM topography and corresponding leakage current profile at +6 V after the (b) 1st scan, (c) 2nd scan, and (d) 3rd scan [12].
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Fig. 7. (a) Schematics of the simulation model representing grain, GB in HK and IL, adopted in COMSOL simulation study [12]. (b) Electric field distribution across HK and IL, showing higher electric field across the IL below the GB path in the HK [12]. (c) Line profile of electric potential across IL.
considered as 3.9 [15]. Fig. 7(b) shows the simulation results for the electric field across the HK/IL dielectric stack. The dotted area shows a location with higher electric field across the IL beneath the GBs associated with the low resistance path in the HfO2 layer. It should be noted that the IL beneath the GBs become oxygen deficient layer [16,17] and its dielectric constant might be higher than 3.9. Fig. 7(c) shows the line plot of the electric potential profile across the IL, highlighting the increased voltage at the GB locations GB1 and GB2. It is observed that there is an expected increase in conductivity and a corresponding decrease in the voltage drop across the GB in the HK, resulting in larger voltage drop across IL below the GB region. As a result, the electric field lines curve towards the IL layer, indicating an enhanced electric field at the IL located below the GB, as shown in Fig. 7(c). It should be highlighted that the field contours become denser at the IL below the GB showing further enhanced electric field at the IL. Raghavan et al. proposed a physics-based Kinetic Monte Carlo (KMC) model considering the thermodynamics and kinetics of trap generation and simulated the trap evolution process in a HK/IL stack [14]. This simulation model uses square cell structures and the results are based on 300–1000 cycles of trails [14]. The simulation model helps to understand the trends for TDDB at GB and grain locations and also its effect on the underlying IL. Simulations are carried out for different ratios of the trap generation rate at grain and GB of 1:2.5, 1:3 and 1:5. Trap generation rate at GB and grain regions are modeled with different j values (jGB > jG) [14,18]. Fig. 8 shows the resulting histogram plot of relative number of BD events across the HK/IL stack. The results reveal that the
Fig. 8. Histogram plot of the relative number of BD events HK/IL dielectric stack column for the defect generation rate ratio of bulk to GB degradation –1:2.5, 1:3 and 1:5. The BD path prefers GB locations (although BD can still occur over a grain) as the ratio increases which is directly related to BD of underlying SiOx IL. The dotted regions show the GB location.
non-uniform distribution of BD events and the frequency of BD events at the GB increases as the GBs degrade. Hence, the distribution of the BD location in the IL becomes more non-uniform as the ratio of G:GB defect generation rate increases (more BD events
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SiOx IL beneath the thinner HfO2 film and GB sites results in the faster BD of the SiOx IL layer, triggering the overall BD of the HfO2/SiOx dielectric stacks. Acknowledgement This work is funded by the SUTD-ZJU Research Grant RP1300104. K. Shubhakar is grateful to Nanyang Technological University (NTU) for the Research Student Scholarship (RSS). References
Fig. 9. Plot of the percentage BD events at IL layer below GB v/s defect generation rate at G and GB. It is clear that as the defect generation rate at GB increases the BD events are more likely to occur at the IL below the GB.
occurring in the IL just beneath the GB in the HK). Trap generation rate in the GB plays a major role in governing the shape of the statistical failure time distribution of HK/IL dielectric stack. The results obtained for the grain and GB degradation trends from the C-AFM experiments are in good agreement with the stochastic simulation results and support the concept of breakdown of polycrystalline HK dielectric stacks at the IL layer beneath the GB sites. Using this simulation model, we plot the profile of BD events at IL layer below GB with respect to defect generation rate at grain and GB, as shown in Fig. 9. It is evident that as the defect generation rate at GB increases, the BD events at the IL are more localized around the GB columns highlighting a clear correlation of increased probability of IL BD beneath the degraded GBs. 4. Conclusions Nanometer scale AFM analysis and simulation results show the effect of the surface roughness and conductivity at GBs of HfO2 film on the local voltage drop across HfO2 and the underlying SiOx IL in a HfO2/SiOx dielectric stack. An enhanced electric field across the
[1] McKenna K, Schluger A. Appl Phys Lett 2009;95:222111. [2] Bersuker G, Yum J, Vandelli L, Padovani A, Larcher L, Iglesias V, et al. Solid-State Electron 2011;65-66:146–50. [3] McKenna K, Shluger A, Iglesias V, Porti M, Nafría M, Lanza M, et al. Microelectron Eng 2011;88:1272–5. [4] Raghavan N, Pey KL, Li X. Appl Phys Lett 2009;95:222903. [5] Lanza M, Iglesias V, Porti M, Nafria M, Aymerich X. Nanoscale Res Lett 2011;6:108. [6] Masuduzzaman M, Xie S, Chung J, Varghese D, Rodriguez J, Krishnan S, et al. Appl Phys Lett 2012;101:153511. [7] Iglesias V, Lanza M, Zhang K, Bayerl A, Porti M, Nafria M, et al. Appl Phys Lett 2011;99:103510. [8] Shubhakar K, Pey KL, Bosman M, Kushvaha SS, O’Shea SJ, et al. J Vac Sci Technol B 2014;32:03D125. 1–7. [9] COMSOL Multiphysics. http://www.comsol.com. [10] Bamzai KK, Koohpayeh SM, Kaur B, Fort D, Abell JS. Ferroelectrics 2008;377:1–21. [11] Pires MA, Israel C, Iwamoto W, Urbano RR, Aguero O, Torriani I, et al. Phys Rev B (Condens Matter Mater Phys) 2006;73. 224404-1. [12] Shubhakar K, Pey KL, Raghavan N, Kushvaha SS, Bosman M, Wang Z, et al. Microelectron Eng 2013;109:364–9. [13] Autran JL, Munteanu D, Houssa M. High-j gate dielectrics. Taylor and Francis; 2003 [chapter-3.4]. [14] Raghavan N, Pey KL, Shubhakar K, Wu X, Liu WH, Bosman M. Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-j gate dielectric stacks. In: IEEE International Reliability Physics Symposium (IRPS), 2012. p. 6A.1.1–11. [15] Verweij JF, Klootwijk JH. Microelectron J 1996;27(7):611–22. [16] Ghobar O, Bauza D, Guillaumot B. Proc IIRW 2007:94–8. [17] Bersuker G, Heh D, Young C, Park H, Khanel P, Larcher L, et al. Breakdown in the metal/high-k gate stack: identifying the ‘‘weak link’’ in the multilayer dielectric. In: IEEE International Electron Devices Meeting (IEDM), 2008. p. 1– 4. [18] Waser R, Hagenbeck R. Acta Mater 2000;48:797.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Impact of local structural and electrical properties of grain boundaries in polycrystalline HfO2 on reliability of SiOx interfacial layer K. Shubhakar a,b,c,⇑, N. Raghavan a, S.S. Kushvaha c,1, M. Bosman c, Z.R. Wang b, S.J. O’Shea c, K.L. Pey a a
Singapore University of Technology and Design (SUTD), Singapore 138682, Singapore Division of Microelectronics, School of EEE, Nanyang Technological University (NTU), Singapore 639798, Singapore c Institute of Materials Research and Engg. (IMRE), A*STAR, 3 Research Link, Singapore 117602, Singapore b
a r t i c l e
i n f o
Article history: Received 30 July 2014 Accepted 31 July 2014 Available online 1 September 2014 Keywords: High-j Dielectric Nanoscale characterization Grain boundaries Interfacial layer Reliability
a b s t r a c t Using nanometer-resolution characterization techniques, we present a study of the local structural and electrical properties of grain boundaries (GBs) in polycrystalline high-j (HK) dielectric and their role on the reliability of underlying interfacial layer (IL). A detailed understanding of this analysis requires characterization of HK/IL dielectrics with nanometer scale resolution. In this work, we present the impact of surface roughness, thickness and GBs containing high density of defects, in polycrystalline HfO2 dielectric on the performance of underlying SiOx (x 6 2) IL using atomic force microscopy and simulation (device and statistical) results. Our results show SiOx IL beneath the GBs and thinner HfO2 dielectric experiences enhanced electric field and is likely to trigger the breakdown of the SiOx IL. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction
2. Experiments
The analysis of degradation and breakdown (BD) phenomenon in polycrystalline HfO2/SiOx dielectric stack is complex due to the polycrystalline, defective nature of HfO2 and the presence of SiOx interfacial layer (IL). Grain boundaries (GBs) in polycrystalline high-j (HK) dielectrics contain high density of electrically active defects, which results in locally varying electrical properties. The GBs favors accumulation of traps, triggering formation of percolation path [1–4]. These GBs pose a major concern in the reliability of HK and IL in dielectric stacks in advanced CMOS technology. Hence, a detailed understanding on the role of GB in the degradation and breakdown of HK and IL layers is essential. As the degradation and eventual BD in dielectric stacks occur locally at a nanometer length scale, it is essential to study the individual layers in dielectric stacks at a nano-level resolution. Atomic force microscopy (AFM) is used extensively for the characterization of thin HK dielectrics with nanometer resolution [5–8]. In this work, AFM is used as a nanoscale characterization tool to study the effect of GBs on underlying SiOx IL in the HfO2/SiOx dielectric stack.
In this work, AFM has been used to characterize the morphology and electrical properties of the HfO2/SiOx dielectric stacks. AFM experiments were carried out in ultra-high vacuum (1010 Torr). Post-deposition annealed (600 °C) HfO2 (4–5 nm)/SiOx (1 nm)/ Si samples, which were fabricated using atomic layer deposition, were used in this study. Si and conducting platinum-wire AFM tips (apex diameter 50 nm) were used in tapping mode and conductive-AFM (C-AFM), respectively. The topography, current profile, spectroscopy (current–voltage (I–V) and current–time (I–t) trends) obtained from AFM experiments were used to analyze the role of GBs on the performance of underlying SiOx IL. COMSOL Multiphysics [9], a finite element method simulation tool, was used in our work for a two dimensional (2-D) simulation study of the electrical potential distribution at the grain and GB locations in HfO2 and the corresponding locations at the underlying SiOx IL. A Kinetic Monte Carlo (KMC) model considering the thermodynamics and kinetics of bond breaking was applied to simulate the time-dependent generation of oxygen vacancy defects in the dual-layer stack considering the modified rate of vacancy generation at the GB region due to enhanced local permittivity (higher vacancy concentration increases local material permittivity [10,11]).
⇑ Corresponding author at: Singapore University of Technology and Design (SUTD), Singapore 138682, Singapore. Tel.: +65 9086 3660. E-mail address: [email protected] (K. Shubhakar). 1 Present address: CSIR National Physical Laboratory, New Delhi 110012, India. http://dx.doi.org/10.1016/j.microrel.2014.07.154 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
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3. Results and discussion 3.1. Experimental results A TEM cross-section of a metal/HfO2 (4–5 nm)/SiOx (1 nm)/ Si structure in Fig. 1(a) shows the morphology of the polycrystalline HfO2 dielectric. A thin layer of SiOx (1 nm) was formed at the interface of the HfO2 and Si during post-annealing process. Fig. 1(b) shows the tapping mode-AFM image of the surface of the annealed (600 °C) HfO2 dielectric films over a 300 300 nm2 area, showing a granular surface roughness. The increase in the surface roughness with annealing is believed to be due to the effect of polycrystallization nature of the HfO2 dielectric. Fig. 1(c) shows a schematic of the effect of surface roughness variation in HfO2 on SiOx IL. The IL region which experiences enhanced electric field due to the thinner HfO2 is highlighted (dotted square region) in Fig. 1(c). Fig. 2(a) shows the line profile of the HfO2 dielectric film along the line X1–X2 in Fig. 1(b), indicative of the morphological inhomogeneity. The larger thickness fluctuation after the annealing [12] could affect the performance and reliability of the HK dielectric. Variation of the surface roughness of the HK film can affect not only the local voltage drop across HK, but also across the underlying IL in the HK/IL dielectric stack. The voltage drop across the HK layer (VHK) and the IL layer (VIL) are approximately given by Eqs. (1) and (2), respectively, where tIL and tHK are the physical thicknesses of the IL and HK layer respectively, k is the relative permittivity and Vox is the overall voltage drop across the HK/IL dielectric stack (Vox = VIL + VHK) [13].
1 kHK tIL þ 1 kIL t HK 1 kIL t HK þ 1 V IL ¼ V ox kHK t IL
V HK ¼ V ox
Fig. 2. (a) Line profiles of topography along the line, X1–X2 and (b) variation of the voltage across HK (HfO2) and IL (SiOx) with HK thickness variation. Dotted vertical line represents the expected thickness (4 nm) of the HfO2.
ð1Þ ð2Þ
The calculated voltage drop across HK layer and IL layer with
jHK = 25 for HfO2 and jIL = 3.9 for SiO2 IL (used to simulate our SiOx) is shown in Fig. 2(b). Data shows there is a much higher elec-
tric field across the thinner IL (SiOx) than the HK (HfO2) layer, and that thickness variations result in inhomogeneous distribution of voltage across the SiOx IL. In particular, the SiOx IL below the physically thinner HfO2 experiences enhanced electric field and could initiate the degradation of the SiOx IL, influencing the BD event at this location.
Fig. 1. (a) TEM micrograph and (b) tapping-mode AFM image of HfO2 (4–5 nm)/SiOx (1 nm) on Si-substrate, annealed at 600 °C. (c) Schematic showing the effect of thinner HfO2 on underlying SiOx IL layer. Dotted square region represents the enhanced electric field at SiOx IL due to thinner HfO2.
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In C-AFM, the conducting Pt-wire tip senses the electrical information of the dielectric at every pixel while scanning the topographical image, with a constant voltage bias applied to the sample. Hence, the topographical and electrical properties of the dielectric can be collected simultaneously at the nanometer length scale. Fig. 3(a) and (b) shows C-AFM topography and corresponding current map of the HfO2/SiOx dielectric stack obtained at a bias of +5 V. Bright spots on the C-AFM current map as shown in Fig. 3(b) at the GB locations correspond to the depressed locations on the topographical image (Fig. 3(a)). The results clearly show an increased leakage current at the GB locations (white dashed lines) due to enhanced TAT through the high concentration of pre-existing traps present at the GBs. Fig. 3(c) shows a schematic representing the effect of thinner HfO2 and lower resistance at GBs on underlying SiOx IL in the HfO2/SiOx stack. Both effects lead to enhanced field across the IL directly below the GB (dotted square region). The breakdown strength of the HfO2/SiOx dielectric stack was examined via ramped voltage stress (RVS) using C-AFM. During RVS, the bias voltage was ramped from 0 to +6 V. RVS was done at different locations of the dielectric sample. An example of this I–V characteristic inhomogeneity is shown in Fig. 4(a) which illustrates the non-uniform electrical characteristics of the HfO2/SiOx stack. It appears that the locations with higher conductivity are GBs. Fig. 4(b) shows a plot of constant voltage stressing (CVS) at +6 V on different locations consisting of grain and GB regions, and shows that the degradation and BD occur relatively faster at a number of locations that were probably (the tip will drift during the experiment, so the location is slightly uncertain) close to or on the GBs [12]. Fig. 5(a) and (b) show the topography and current map in a first scan obtained at +6 V, respectively. Fig. 5(c) and (d) shows the current maps over the same area in the subsequent sec-
ond and third scans, respectively (at +6 V). The magnitude of the leakage current and conducting region along the GB increases upon uniform stressing, indicating a higher rate of stress-induced trap generation compared to the grain regions. Fig. 6(a) shows a quantitative analysis of the C-AFM leakage current images and clearly shows an increase in the leakage current and faster degradation along the GBs upon stressing and supports the results shown in Fig. 4. Fig. 6(b) shows the voltage across HfO2 and SiOx layers near grain and GB regions of HfO2 upon stressing and it is observed that the voltage across the SiOx IL underneath the GB increases at a faster rate than that of below the grain region. The voltages across HfO2 and SiOx were estimated with respect to the degradation rates S1 and S2 at the grain and GB of HfO2 layer, respectively (considering the voltage across the HfO2 layer is inversely proportional to the conductance observed in Fig. 6(a)). Higher trap generation rate at the GBs on successive scans compared to that of grain regions indicates enhanced degradation of SiOx IL underlying GBs leading to earlier BD at these locations [12]. 3.2. Simulation results The electrical properties of grains and GBs were analyzed using simulation of the electrical potential distribution at the grain and GB locations in HK and the corresponding locations at the underlying IL. The 2-D ‘‘Electrostatics’’ application mode in COMSOL Multiphysics tool [9] was used for our simulation study. The software provides a computer aided design interface to define the geometry, a sophisticated mesh generation capability, and solves for potential and electric field over a defined geometric domain [9]. Here, the effect of GBs on the thin underlying SiOx IL is demonstrated with the help of a 2-D structure of HfO2/SiO2 with a top metal electrode and Si substrate, and a voltage bias of +1.5 V applied to the top
Fig. 3. (a) C-AFM topography, (b) corresponding current map (at +5 V) of HfO2/SiOx dielectric stack depicting the grain and GB profile. (c) Schematic showing the effect of thinner HfO2 and larger defect density at GBs. Both effects lead to enhanced field across the SiOx IL underneath the GBs (dotted square region).
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Fig. 4. (a) C-AFM I–V characteristics at different locations on the dielectric and (b) leakage current evolution with time under constant voltage stress of +6 V at different locations on the dielectric [12].
metal electrode. The schematic of the HfO2/SiO2 dielectric stack model is shown in Fig. 7(a). The GB in the HfO2 dielectric was modeled with a higher permittivity (j1 = 30 for GB1 and 35 for GB2) than that of grain regions (j2 = 25) [14]. GB1 shows slightly more conductivity than GB2. The permittivity of the SiO2 layer (j3) is
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Fig. 6. (a) Degradation rate at grain and GB with successive scans (upon stressing). The data (distribution of leakage current over a 5 5 nm2 area of Fig. 5) was normalized to the minimum current (50 pA) observed over the grain region on the first scan. (b) Voltage across HfO2 and SiOx at grain and GB locations with successive scans.
Fig. 5. (a) CAFM topography and corresponding leakage current profile at +6 V after the (b) 1st scan, (c) 2nd scan, and (d) 3rd scan [12].
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Fig. 7. (a) Schematics of the simulation model representing grain, GB in HK and IL, adopted in COMSOL simulation study [12]. (b) Electric field distribution across HK and IL, showing higher electric field across the IL below the GB path in the HK [12]. (c) Line profile of electric potential across IL.
considered as 3.9 [15]. Fig. 7(b) shows the simulation results for the electric field across the HK/IL dielectric stack. The dotted area shows a location with higher electric field across the IL beneath the GBs associated with the low resistance path in the HfO2 layer. It should be noted that the IL beneath the GBs become oxygen deficient layer [16,17] and its dielectric constant might be higher than 3.9. Fig. 7(c) shows the line plot of the electric potential profile across the IL, highlighting the increased voltage at the GB locations GB1 and GB2. It is observed that there is an expected increase in conductivity and a corresponding decrease in the voltage drop across the GB in the HK, resulting in larger voltage drop across IL below the GB region. As a result, the electric field lines curve towards the IL layer, indicating an enhanced electric field at the IL located below the GB, as shown in Fig. 7(c). It should be highlighted that the field contours become denser at the IL below the GB showing further enhanced electric field at the IL. Raghavan et al. proposed a physics-based Kinetic Monte Carlo (KMC) model considering the thermodynamics and kinetics of trap generation and simulated the trap evolution process in a HK/IL stack [14]. This simulation model uses square cell structures and the results are based on 300–1000 cycles of trails [14]. The simulation model helps to understand the trends for TDDB at GB and grain locations and also its effect on the underlying IL. Simulations are carried out for different ratios of the trap generation rate at grain and GB of 1:2.5, 1:3 and 1:5. Trap generation rate at GB and grain regions are modeled with different j values (jGB > jG) [14,18]. Fig. 8 shows the resulting histogram plot of relative number of BD events across the HK/IL stack. The results reveal that the
Fig. 8. Histogram plot of the relative number of BD events HK/IL dielectric stack column for the defect generation rate ratio of bulk to GB degradation –1:2.5, 1:3 and 1:5. The BD path prefers GB locations (although BD can still occur over a grain) as the ratio increases which is directly related to BD of underlying SiOx IL. The dotted regions show the GB location.
non-uniform distribution of BD events and the frequency of BD events at the GB increases as the GBs degrade. Hence, the distribution of the BD location in the IL becomes more non-uniform as the ratio of G:GB defect generation rate increases (more BD events
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SiOx IL beneath the thinner HfO2 film and GB sites results in the faster BD of the SiOx IL layer, triggering the overall BD of the HfO2/SiOx dielectric stacks. Acknowledgement This work is funded by the SUTD-ZJU Research Grant RP1300104. K. Shubhakar is grateful to Nanyang Technological University (NTU) for the Research Student Scholarship (RSS). References
Fig. 9. Plot of the percentage BD events at IL layer below GB v/s defect generation rate at G and GB. It is clear that as the defect generation rate at GB increases the BD events are more likely to occur at the IL below the GB.
occurring in the IL just beneath the GB in the HK). Trap generation rate in the GB plays a major role in governing the shape of the statistical failure time distribution of HK/IL dielectric stack. The results obtained for the grain and GB degradation trends from the C-AFM experiments are in good agreement with the stochastic simulation results and support the concept of breakdown of polycrystalline HK dielectric stacks at the IL layer beneath the GB sites. Using this simulation model, we plot the profile of BD events at IL layer below GB with respect to defect generation rate at grain and GB, as shown in Fig. 9. It is evident that as the defect generation rate at GB increases, the BD events at the IL are more localized around the GB columns highlighting a clear correlation of increased probability of IL BD beneath the degraded GBs. 4. Conclusions Nanometer scale AFM analysis and simulation results show the effect of the surface roughness and conductivity at GBs of HfO2 film on the local voltage drop across HfO2 and the underlying SiOx IL in a HfO2/SiOx dielectric stack. An enhanced electric field across the
[1] McKenna K, Schluger A. Appl Phys Lett 2009;95:222111. [2] Bersuker G, Yum J, Vandelli L, Padovani A, Larcher L, Iglesias V, et al. Solid-State Electron 2011;65-66:146–50. [3] McKenna K, Shluger A, Iglesias V, Porti M, Nafría M, Lanza M, et al. Microelectron Eng 2011;88:1272–5. [4] Raghavan N, Pey KL, Li X. Appl Phys Lett 2009;95:222903. [5] Lanza M, Iglesias V, Porti M, Nafria M, Aymerich X. Nanoscale Res Lett 2011;6:108. [6] Masuduzzaman M, Xie S, Chung J, Varghese D, Rodriguez J, Krishnan S, et al. Appl Phys Lett 2012;101:153511. [7] Iglesias V, Lanza M, Zhang K, Bayerl A, Porti M, Nafria M, et al. Appl Phys Lett 2011;99:103510. [8] Shubhakar K, Pey KL, Bosman M, Kushvaha SS, O’Shea SJ, et al. J Vac Sci Technol B 2014;32:03D125. 1–7. [9] COMSOL Multiphysics. http://www.comsol.com. [10] Bamzai KK, Koohpayeh SM, Kaur B, Fort D, Abell JS. Ferroelectrics 2008;377:1–21. [11] Pires MA, Israel C, Iwamoto W, Urbano RR, Aguero O, Torriani I, et al. Phys Rev B (Condens Matter Mater Phys) 2006;73. 224404-1. [12] Shubhakar K, Pey KL, Raghavan N, Kushvaha SS, Bosman M, Wang Z, et al. Microelectron Eng 2013;109:364–9. [13] Autran JL, Munteanu D, Houssa M. High-j gate dielectrics. Taylor and Francis; 2003 [chapter-3.4]. [14] Raghavan N, Pey KL, Shubhakar K, Wu X, Liu WH, Bosman M. Role of grain boundary percolative defects and localized trap generation on the reliability statistics of high-j gate dielectric stacks. In: IEEE International Reliability Physics Symposium (IRPS), 2012. p. 6A.1.1–11. [15] Verweij JF, Klootwijk JH. Microelectron J 1996;27(7):611–22. [16] Ghobar O, Bauza D, Guillaumot B. Proc IIRW 2007:94–8. [17] Bersuker G, Heh D, Young C, Park H, Khanel P, Larcher L, et al. Breakdown in the metal/high-k gate stack: identifying the ‘‘weak link’’ in the multilayer dielectric. In: IEEE International Electron Devices Meeting (IEDM), 2008. p. 1– 4. [18] Waser R, Hagenbeck R. Acta Mater 2000;48:797.