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Impact of substrate on performance of band gap engineered graphene field effect transistor
Accepted Manuscript Impact of substrate on performance of band gap engineered graphene field effect transistor Durgesh Laxman Tiwari, K. Sivasankaran PII:
S0749-6036(17)32258-9
DOI:
10.1016/j.spmi.2017.11.004
Reference:
YSPMI 5339
To appear in:
Superlattices and Microstructures
Received Date: 22 September 2017 Revised Date:
2 November 2017
Accepted Date: 2 November 2017
Please cite this article as: D.L. Tiwari, K. Sivasankaran, Impact of substrate on performance of band gap engineered graphene field effect transistor, Superlattices and Microstructures (2017), doi: 10.1016/ j.spmi.2017.11.004. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
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Impact of Substrate on Performance of Band Gap engineered Graphene Field Effect Transistor Durgesh Laxman Tiwari and K. Sivasankaran*
Vellore, Tamilnadu, India
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Department of Micro and Nanoelectronics, School of Electronics Engineering VIT University Corresponding Author: [email protected]*
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Abstract:
In this paper, we investigate the graphene field effect transistor (G-FET) to enhance the drain
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current saturation and to minimize the drain conductance (gd) using numerical simulation. This work focus on suppressing the drain conductance using silicon substrate. We studied the impact of different substrate on the performance of band gap engineered G-FET device. We used a nonequilibrium green function with mode space (NEGF_MS) to model the transport behavior of carriers for 10 nm channel length G-FET device. We compared the drain current saturation of GFET at higher drain voltage regime on silicon, SiC, and the SiO2 substrate. This paper clearly
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demonstrates the effect of substrate on an electric field near drain region of G-FET device. It is shown that the substrate of G-FET is not only creating a band gap in graphene, which is important for current saturation and gd minimization, but also selection of suitable substrate can suppress generation of carrier concentration near drain region is also important.
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Introduction:
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Keyword: Graphene, Drain conductance, NEGF_MS, carrier concentration, current saturation.
Graphene is one atomic thick two-dimensional material consists of two atoms per unit cell. The px and py orbital of carbon atom make sp2 hybridization with the neighboring carbon atom in graphene, which is responsible for the high mechanical strength of graphene material. The pz orbital electron in graphene participates in electrical conductivity. Due to linear dispersion relation, the effective mass of electron in graphene become negligible, and it shows higher carrier mobility. The high carrier mobility and large saturation velocity make it most prominent material for radio frequency (RF) and analog application. Graphene materials have an enormous potential towards electronics application, but due to poor current saturation, it’s hard to use as
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field effect transistor for RF application. Great experiment and theoretical work have been done to improve the current saturation in high voltage region for G-FET device [1, 2]. Due to the zero band-gap in graphene band to band tunneling is high and current saturation becomes difficult. G-FET Operation in a thermionic region is possible when VGSVDS band
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to band tunneling, get start and saturation become weak [3]. By creating a band gap in graphene, we can improve the drain current saturation up to some extent. Unfortunately, large area graphene is zero band gap material and creating a band gap we need to cut the graphene in ribbon form which is quite difficult for large area fabrication. There is another way to improve
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the drain current saturation in graphene field effect transistor by keeping constant carrier concentration in the drain region. Therefore for more improvement and stable performance drain
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carrier concentrations should be constant throughout drain region and it is possible by selecting a suitable substrate which improves drain current saturation. The effect of nonpolar substrate on graphene electronics for radio frequency application is more promising as compared to the polar substrate [4]. A latest experimental paper has been demonstrated that silicon is the best substrate for graphene electronics for suppression of drain conductance as well as large area fabrication [5].
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Experimentally fT has been achieved up to 1.42 THz for 56 nm gate lengths [6], but the large difference between fT and fmax is the biggest problem for graphene transistor. In this paper, we simulated top gate graphene field effect transistor and analyzed its performance on silicon, SiC and the SiO2 substrate. We compare the gapped graphene performance on SiC substrate with
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gapless and gapped graphene on a silicon substrate. The minimization of drain conductance has a direct impact on current saturation therefore by creating a band-gap in graphene people are
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trying to achieve good current saturation [7]. This work demonstrates that creating a band-gap is the not only solution to achieve a current saturation but using a suitable substrate for graphene electronics is also important which can minimize the carrier generation near the drain region. The device simulation performed using SILVACO ATLAS device simulator [8].
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Device Structure and Simulation Setup:
Fig.1 Schematic view of top gate graphene field effect transistor.
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Figure 1 shows the schematic view of G-FET considered for the study. The various device and material parameters considered for the simulation are listed in Table 1 and 2. Table: 1 Device parameter for simulation of G-FET
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Channel Length (LCh) Oxide thickness (tox) Channel Thickness (Graphene) Source, Drain and Gate Contact Source Length (LS) Drain Length (LD)
10 nm 3 nm 0.35 nm Palladium 10 nm 10 nm
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Table: 2 Material parameter for graphene on different substrate. on SiO2 substrate
on SiC substrate
on Si Substrate
Band-gap Electron Mobility Carrier density Permittivity Affinity
0.0 eV [9] 40,000 cm2v-1s-1 [12] 1012 cm-2 [12] 3.3 [15] 4.248 [17]
0.26 eV [10] 18,1000 cm2v-1s-1[13] 3x1011 cm-2 [14] 3.3 [16] 4.248 [17]
0.0 eV [11] 2,000 cm2v-1s-1 [11] 1.1x1011 cm-2 [11] 3.3 [16] 4.248 [17]
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Electrical Properties
Graphene is not an inbuilt material in SILVACO ATLAS tool. Therefore, we used user defined function to define graphene material [18]. To incorporate the 2-D nature of electron transport in G-FET device, we used 1DY geometry method for Schrödinger solution. The 1DY geometry is used to activate the confinement of electron motion in the Y direction. In this paper, we used NEGF_MS model to simulate device for 10nm channel length. We assumed ballistic transport in
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graphene for 10nm length scale, and used Von-Neumann boundary condition near the source and drain contact region. A self-consistent solution of Schrödinger-Poisson equation in NEGF method with effective mass approximation is most accurate for graphene device simulation. In NEGF_MS method self-energy term is the most important which takes care of graphene-metal
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contact up to atomic scale limit [19]. The atomistic approach of NEGF method helps to find the hidden behavior of graphene transistor for sub 10 nm length scale which is not possible by any other transport method. Self-consistent solution of Schrödinger-Poisson equation is used to find the charge and potential distribution along the channel. The potential values are used to find the
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Green’s function, retarded Green’s function and advanced Green function along the channel of the device and all these values are used to find transmission, current and carrier concentration of
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the device along the channel in most accurate form. We have activated Schrödinger-Poisson method for a self-consistent solution in ATLAS device simulator. The equation 1 and 2 are in the matrix form, and the size of the matrix depends on the number of basis element and nodal points in a given meshing condition. We used 3C-SiC as a user define material for graphene of 0.35 nm thick channel and set the relevant parameters as given in Table 1 and 2 to simulate the G-FET device.
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The Green’s function formalism can be expressed as [20] G[( E + i 0 + ) I − H + IUg − ∑ S − ∑ D ] = I ⋅
(1)
where H represents the Hamiltonian matrix in mode space with diagonal and off diagonal
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elements, and off diagonal elements corresponds to the hopping energy of electron from one lattice site to another lattice site. E corresponds to electron or hole energy and I, Ug represent the
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identity matrix and potential energy of channel respectively. ∑S and ∑D stand for self-energy term for source and drain contact which is important for an incoming and outgoing electron from source and drain region.
[
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T = Trace Γ s G R Γ D G R† ⋅
(2)
Equation 2 represents the transmission matrix of the device which consists of broadening of energy level, Γ S and Γ D . Broadening term near the source and drain contact with retarded and advanced Green's function explains the motion of electron from source to drain through the channel region. The current equation can be obtained by using Landauer formalism which
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consists of transmission and Fermi function difference between the source and drain contact as shown in Equation 3. 2q h
∞
∫ T (E )[( f (E ) − L
f R (E ))]dE ⋅
(3)
0
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I =
Carrier density in the device is taken care by equation 4, where L is channel length, G 〈 mn represent the less than Green's function for m and n state, Ψ m and Ψn represent the mth and nth wave function. In general G 〈 mn is the correlation function between two state m and n and the
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diagonal term of correlation function gives the information of carrier density as a function of energy in the system. n( x, y) = −i / L∑ ∫ G〈 mn ( E)Ψm ( y)Ψn ( y)dE / 2π ⋅
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mn
(4)
Reference (Vds=0.5V)
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Simulation (Vds=0.5V)
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Drain Current(ID) [µA]
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Gate Voltage(VGS) [V]
Fig.2 ID-VG characteristics of graphene FET device for SiO2 substrate
Fig.2 shows the simulation comparison of published result for G-FET device on SiO2 substrate. We used NEGF_MS electron transport model to match reference result [21]. Our simulated result based on effective mass Hamiltonian and the reference result is based on nearestneighbour tight binding Hamiltonian. For the modeling of the device with transverse confinement, it is more important to use Von-Neumann boundary condition near contact region. By assuming the ballistic transport of electron for 10 nm channel length we used Von-Neumann
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boundary condition near the source and drain contact region. In ATLAS, we specified REFLECT statement to activate Von-Neumann boundary condition.
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Result and Discussion:
A. Effect of drain carrier density on current saturation Fig.3 shows the comparison of drain current saturation on silicon and SiO2 substrate for 10 nm channel length. We can see that for VGS
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based graphene FET but in the case of Silicon substrate based G-FET current saturation is excellent. By creating a band gap in a graphene, we can solve the problem of poor current
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saturation up to some extent by suppressing the band to band tunneling in zero band-gap G-FET. But for better result and stable performance, we have to choose a silicon substrate for graphene electronics. In the case of the silicon substrate, the same polarity charge ion as like channel generates at the drain-substrate interface due to applied drain voltage. This charge carrier increases with the increase of drain bias and prevents the generation of drain carrier concentrations. Below Fig.4 explains the mechanism behind the better performance of silicon
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substrate over SiO2 for G-FET. Due to applied negative drain voltage positive ion gets induce from the silicon substrate to prevent the shifting of Fermi level in conduction band as shown by upward pulling arrow. This pulling of bands near drain region is responsible for maintaining constant carrier concentration in drain region to improve the current saturation. Region I, II, III
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corresponds to linear, saturation and hole inversion or electron inversion region for dc output characteristics of G-FET. A drain voltage increases the saturation area is large in the case of
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silicon substrate G-FET as compared to SiO2 substrate G-FET. In a case of SiO2 substrate based G-FET, there is no induced charge ion from the substrate to suppress the drain carrier concentration. Therefore, saturation area (region II) is less in SiO2 substrate G-FET.
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Fig.3 ID-VDS characteristics for 10nm channel length on Si and SiO2 substrate for different gate voltages (0.45V, 0.50V, 0.55V). Suppression of drain carrier generation on the drain is a very important aspect for graphene field effect transistor, in particular for analog and radio frequency applications. Therefore for more elaboration, we plotted the drain carrier concentrations vs. drain region of G-FET device on
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different drain bias as shown in Fig.5. Analysis of carrier density by using mode space approach is most accurate and efficient way because computational time is very less as compare to real space approach [22]. The solution of Schrödinger equation for Eigen function and Eigen energy in decoupled mode space for each subband on every nodal point is the important part of transport
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method to capture a variation of carrier concentration in the drain region. The Fig.5 graph indicates that in the case of the SiO2 substrate carrier density increased linearly throughout drain region for higher drain voltage which corresponds to weak current saturation as shown in Fig.3
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near higher drain voltages (0.5, 0.4). Simulation result indicates the poor saturation is more dominating for small positive gate voltages (0.45, 0.50). In the case of n-channel for higher drain voltage region, the lateral carrier density modulation effect on G-FET current saturation is more in SiO2 based G-FET [23]. In the event of the silicon substrate, the carrier concentration is constant throughout drain even in a case of higher drain voltages (0.5, 0.4) because lateral carrier density modulation gets suppressed due to induced positive charge from silicon substrate near the drain region.
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Fig.4 Silicon and SiO2 substrate based top gate G-FET with output characteristics I, II and III corresponds to linear, saturation and hole inversion region respectively.
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Vds=0.4V(Si-Sub.) Vds=0.5V(Si-Sub.)
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Vds=0.5V(SiO2-Sub.)
0.0010 0.0008 0.0006
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Charge Concentration(C/Cm^2)
Vds=0.4V(SiO2-Sub.)
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Distance(µm)
Fig.5 Charge concentration versus Distance along the channel in drain region for 10 nm channel length for SiO2 and Silicon for different VDS. B. Effect of band-gap on current saturation We also studied the effect of the band gap of graphene on the current saturation and compared with zero band gap graphene G-FET on a silicon substrate. DC output characteristics show that in the case of zero band gap current saturation is poor on the silicon substrate as compared to
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non-zero band gap G-FET for high drain voltage region as shown in Fig. 6a. There is minuscule non-saturation of the drain current in case of G-FET with a silicon substrate as shown in Fig6.a, however, this can be eliminated by introducing a band gap in graphene. Fig.6b shows that the problem of current saturation is not solved completely after introducing a band gap in graphene
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on SiC substrate G-FET in higher drain voltage region. From Fig.7 we can observe that at 0.8V Vds supply, charge carrier concentration is linearly increasing in case of gapped graphene G-FET on SiC substrate which is not observed in case of zero band gap G-FET on a silicon substrate. Therefore we can say that silicon substrate suppresses the carrier generation in G-FET near the
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drain region.
However, for gapless G-FET on a silicon substrate, the drain current is increased with increasing
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drain voltage. The drain current increment in gapless G-FET on a silicon substrate is not very sharp as like in a case of gapped graphene on SiC substrate. The non-saturation of current on a silicon substrate gapless G-FET is due to the zero band gap of graphene channel in which electron band to band tunneling phenomena dominates [24], therefore after introducing a band gap of 0.26 eV in graphene channel drain current saturation becomes better in case of silicon. 50
Drain Current(ID) [µA]
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Eg=0.26eV,Vgs=0.50V
Eg=0.0eV,Vgs=0.45V Eg=0.26eV,Vgs=0.45V
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Drain Voltage(VDS) [V]
Fig.6(a)
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Fig.6(a) Comparison of ID vs VDS of gapped and gapless graphene on silicon substrate (b) ID vs VDS graph of gapped graphene with band gap of 0.26 eV on SiC substrate.
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Vds=0.8V(Si-Sub.) Vds=0.8V(SiC-Sub.)
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0.000025 0.000020 0.000015 0.000010 0.000005 0.000000 0.020
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Distance(µm)
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Fig.7 Charge concentration vs Distance along the channel in the drain region of G-FET device for gapped and gapless graphene on SiC and Si respectively.
The energy band diagram of gapless and gapped graphene channel on silicon substrate G-FET
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device for 0.45V and 0.60V gate and drain voltage respectively shown in Fig. 8. The energy gap between conduction band and valence band reduces the band to band tunneling possibility near the source and drain region. Therefore current saturation becomes better as shown in Fig.6a for gapped graphene channel FET as compared to gapless graphene channel FET on silicon
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substrate. Therefore for proper saturation, we need to use gapped graphene on silicon substrate because gapped graphene suppresses band to band tunneling and silicon substrate prevent the
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generation of a carrier in the drain region of G-FET device.
Fig8.(a)
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Fig8.(b)
Fig8. (a) Energy band diagram of gapless graphene G-FET on a silicon substrate, (b) Energy band diagram of gapped graphene G-FET on a silicon substrate. Figure 9 shows the transfer characteristics of G-FET on different substrate with 10 nm channel length by using NEGF_MS method. We compared the transfer characteristics for
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gapless graphene on the SiO2 substrate with gapped graphene on SiC substrate. Fig.9 demonstrates that in the case of gapped graphene device, the off current decreases drastically as compared to gapless graphene G-FET. The shifting of dirac point in case of gapless graphene FET on SiO2 is more which corresponds to a significant amount of band to band tunneling as
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compared to gapped graphene as shown in Fig.9. In Fig.10 transfer characteristics of G-FET on silicon substrate is symmetric; p-branch and n-branch are showing symmetry behavior for
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positive and negative gate voltage. In the case of gapped graphene on SiC, p-branch and nbranch are not symmetry which corresponds to high contact resistance [25]. From Fig.10 we find that for a small value of gate voltage conductivity is very less, it shows most of the current is thermionic current and it is important for field effect transistor application. Drain current slope is very high in G-FET on the silicon substrate as compared to SiC G-FET; it means transconductance is greater in G-FET on a silicon substrate.
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Vds=0.4V(SiO2-Sub.)
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Vds=0.4V(SiC-Sub.) Vds=0.5V(SiO2-Sub.) Vds=0.5V(SiC-Sub.) Vds=0.6V(SiO2-Sub.) Vds=0.6V(SiC-Sub.)
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Fig. 9 Transfer characteristics of G-FET for 10 nm channel on SiC with gapped graphene and the SiO2 substrate with gapless graphene. Vds=0.4V(SiC-Sub.)
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Fig.10. Comparison of the transfer characteristics of gapped graphene (Eg=0.26ev) on SiC substrate with gapless graphene on a silicon substrate.
C. Effect of Silicon substrate on electric field near drain region In this section we studied and compared the hot electron problem on silicon and the SiO2 substrate [26]. Hot electron effect is due to the high electric field near the drain region. The proper study of a high electric field near drain region is possible for minimum gate voltage; therefore, we used zero gate voltage [27]. Simulation has been carried out for different VDS values 0.6V, 0.8V and 1.0V respectively. Fig.11 shows that electric field across drain and
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channel junction region, in case of SiO2 substrate G-FET the electric field is high as compared to silicon substrate based G-FET device. This electric field has the direct impact on leakage current and breakdown voltage of the device. In the case of a high electric field near the drain region, electron gets tunnel through oxide and increase of gate leakage current [28]. With the rapid raise
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of drain voltage, electric field gets reduced in drain region in case of silicon substrate G-FET, the difference is quite large in the case of VDS is equal to 1V. Gate tunneling current is one of the biggest problems for short channel graphene device, and it can be solved by using silicon
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substrate.
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Fig.11 (b)
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Silicon Vds=1V
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Fig 11- Electric field versus distance along the channel of G-FET device in drain region for different drain voltage ranging from 0.6 to 1.0 volt.
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Fig.12. Transconductance vs Gate voltage for gapless G-FET on silicon and the SiO2 substrate and gapped graphene-FET on SiC substrate.
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Silicon SiO2
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gd(S)
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Fig.13. Drain conductance vs drain voltage of gapless graphene FET on silicon and the SiO2 substrate and gapped graphene FET on SiC.
D. Transconductance and drain conductance of G-FET device In this section we have analyzed the analog and radio frequency performance of G-FET. We found that transconductance (gm) is higher in the case of G-FET on a silicon substrate as
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compared to G-FET on SiO2 and gapped graphene on SiC substrate G-FET. Another important parameter is fmax which is highly influenced by gd, can achieve maximum value by minimizing gd
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or in other words by improving drain current saturation [29, 30]. The gd plot is shown in Fig.13 and 14 where different substrate are compared along with gapped and gapless graphene FET. Our simulation result clearly demonstrates the importance of gapped graphene as a channel material along with silicon substrate for radiofrequency application in G-FET. From simulation result as shown in Fig.13, it is found that gd increases in case of SiO2 substrate G-FET, though gd for gapless graphene FET is slightly higher for a higher value of drain voltage as compare to gapped graphene on SiC substrate G-FET. This is the quite improved performance of gapless graphene-FET on a silicon substrate. In the case of Fig.14, we compared the drain conductance for gapped graphene FET on silicon and SiC substrate for higher drain voltage up to 0.65 volts.
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We found out gapped graphene with the silicon substrate is the best combination of G-FET device for radio frequency application.
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Gapped Graphene on Silicon Sub. Gapless Graphene on Silicon Sub. Gapped Graphene on SiC Sub.
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Conclusion:
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Fig. 14. Drain conductance vs Drain voltage of gapless and gapped graphene G-FET on a silicon substrate and gapped graphene G-FET on SiC substrate.
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Based on our simulation study we conclude that for better current saturation in G-FET we need gapped graphene as a channel material and silicon as substrate. The role of gapped graphene is to
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suppress the band to band tunneling, and the silicon substrate is to prevent the carrier generation in the drain region. The simulation results show the importance of silicon substrate over SiO2 and SiC substrate for G-FET device. The problem of gate leakage current for short channel length device can be solved by using silicon substrate because it is minimizing the electric field near the drain region. By using silicon substrate, large area fabrication problem can be solved for G-FET device with existing technology. It is evident from the simulation that the silicon substrate will be the promising material for graphene electronics because it improves drain current saturation.
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Reference:
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[1] I. Meric, M.Y. Han, A.F. Young, B. Ozyilmaz, P. Kim, K.L. Shepard, Current saturation in zero-bandgap top-gated graphene field effect transistors, Nat.Nanotechnol. 3 (2008) 654. [2] Salim Berrada, Viet Hung Nguyen, Damien Querlioz, Jérôme Saint-Martin, Alfonso Alarcón, Christophe Chassat, Arnaud Bournel, and Philippe Dollfus, Graphene nanomesh transistor with high on/off ratio and good saturation behavior, Applied Physics Letters 103,(2013), 183509. [3] Kartik Ganapathi, Youngki Yoon, Mark Lundstrom, and Sayeef Salahuddin, Ballistic I–V Characteristics of Short-Channel Graphene Field-Effect Transistors: Analysis and Optimization for Analog and RF Applications IEEE Transactions on electron devices, Vol. 60, 2013, 958. [4] Seul Ki Hong, Joong Gun Oh, Wan Sik Hwang, and Byung Jin Cho, Enhanced performance in graphene RF transistors via advanced process integration, Semiconductor Science, and technology, IOP, 32 (2017),1361. [5] Seung Min Song, Jae Hoon Bong, Wan Sik Hwang & Byung Jin Cho, Improved Drain Current Saturation and Voltage Gain in Graphene on Silicon Field Effect Transistors, Naturescientific-report Vol.6,2016,25392. [6] Liao, L. et al. Sub-100 nm channel length graphene transistors. Nano Lett.Vol 10, (2010) 3952. [7] Juan M.Marmolejo-Tejada n, Jaime Velasco-Medina, Review on graphene nanoribbon devices for logic applications, Elsevier-microelectronics Vol.48,(2016),18. [8] ATLAS, User's Manual, Silvaco International, 2012. [9] Yun Wu, Xuming Zou, Menglong Sun, Zhengyi Cao, Xinran Wang, Shuai Huo, Jianjun Zhou,Yang Yang, Xinxin Yu, Yuechan Kong, Guanghui Yu, Lei Liao, and Tangsheng Chen , 200 GHz Maximum Oscillation Frequency in CVD Graphene Radio Frequency Transistors, ACS, Applied Materials & interfaces ,Vol.8 ,(2016), 25645. [10] Joseph Scott Bunch, Mechanical and Electrical Properties of Graphene Sheets, Ph.D. diss., Cornell University, 2008. [11] M. Paolo, M. Cheli, G. Iannaccone, Model of tunneling transistors based on graphene on SiC, Appl. Phys. Lett. 96 (13) (2010) 133508. [12] Christos Dimitrakopoulos, Yu-Ming Lin, Alfred Grill, Damon B. Farmer, Marcus Freitag, Yanning Sun, Shu-Jen Han, Zhihong Chen, Keith A. Jenkins, Yu Zhu, Zihong Liu, Timothy J. McArdle, John A. Ott, Robert Wisnieff, and Phaedon Avouris , Wafer-scale epitaxial graphene growth on the Si-face of hexagonal SiC (0001) for high frequency transistors American Vacuum Society 7 September 2010. [13] Jian-Hao Chen, Chaun Jang, Shudong Xiao, Masa Ishigami, Michael S. Fuhrer, Intrinsic and extrinsic performance limits of graphene devices on SiO2,Nat. Nanotechnol. 3 (4) (2008) 206e209. [14] Joshua A. Robinson, MaxwellWetherington, Joseph L. Tedesco, Paul M. Campbell, Xiaoyu Weng, Joseph Stitt, Mark A. Fanton, et al., Correlating Raman spectral signatures with carrier mobility in epitaxial graphene: a guide to achieving high mobility on the wafer scale, Nano Lett. 9 (8) (2009) 2873e2876. [15] Yang Yanfei, Lung-I. Huang, Yasuhiro Fukuyama, Fan-Hung Liu, Mariano A. Real, Paola Barbara, Chi-Te Liang, David B. Newell, Randolph E. Elmquist, Low carrier density epitaxial graphene devices on SiC, Small 11 (1) (2015) 90e95.
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[16] Alina Cismaru, Mircea Dragoman, Adrian Dinescu, Daniela Dragoman, G. Stavrinidis, G. Konstantinidis, Microwave and Millimeterwave Electrical Permittivity of Graphene Monolayer, ar xiv preprint ar xiv:1309.0990, 2013. [17] Bart N. Szafranek, et al., Current saturation and voltage gain in bilayer graphene field effect transistors, Nano Lett. 12 (3) (2012) 1324e1328. [18] Mojtaba Saeidi Mobarakeh, Negin Moezi, Mehran Vali, Daryoosh Dideban, A novel graphene tunneling field effect transistor (GTFET) using bandgap engineering, Vol. 100 (2016) 1221. [19] S. Datta, Electron transport in mesoscopic system, Cambridge University press, 1995. [20] R. Venugopal, Z. Ren, S. Datta, and M. S. Lundstrom, Simulating quantum transport in nanoscale transistors: Real versus mode-space approaches, Journal of Applied Physics, Vol.92 (2002).8979. [21] Hojjatollah Sarvari, Amir Hossein Ghayour, Zhi Chen, Rahim Ghayour, Analyses of Short Channel Effects of Single-Gate and Double-Gate Graphene Nanoribbon Field Effect Transistors, Hindawi, journal of material vol.2016, 25 July 2016,8242469. [22] Cedric Nanmeni Bondja, Zhansong Geng, Ralf Granzner, Jörg Pezoldt and Frank Schwierz, Simulation of 50-nm Gate GrapheneNanoribbon Transistors, MDPI, electronics, Vol.5,(2016),17. [23] Kinam Kim, Jae-Young Choi, Taek Kim, Seong-Ho Cho & Hyun-Jong Chung, A role for graphene in silicon-based semiconductor devices, Nature, Vol.479,(2011),338. [24] F. Tseng, D. Unluer, K. Holcomb, M. R. Stan, and A. W. Ghosh, Diluted chirality dependence in edge rough graphene nanoribbon field effect transistors, APPLIED PHYSICS LETTERS, Vol.94,(2009), 223112. [25] Xiaomu Wang, Haitao Xu, Jie Min, Lian-Mao Peng and Jian-Bin Xu, Carrier sheet density constrained anomalous current saturation of graphene field effect transistors: kinks and negative differential resistances, RSC Nanoscale, Vol.5,(2013),2811. [26] Ali Naderi, Double gate graphene nanoribbon field effect transistor with electrically induced junctions for source and drain regions, J Comput. ElectronVol.15,(2016),347. [27] Hongming Lyu, Qi Lu, Jinbiao Liu, Xiaoming Wu, Jinyu Zhang, Junfeng Li, Jiebin Niu, Zhiping Yu, Huaqiang Wu & He Qian, Deep-submicron Graphene Field-Effect Transistors with State-of-Art fmax, Nature scientific report , Vol.6,(2016),35717. [28] Vincent E. Dorgan, Myung-Ho Bae, and Eric Pop, Mobility and saturation velocity in graphene on SiO2, Applied Physics Letters, Vol.97, (2010) 082112. [29] B. Huard, N. Stander, J.A. Sulpizio, and D. Goldhaber-Gordon, https://arxiv.org › cond-mat (2013). [30] G. Fiori, A. Betti, S. Bruzzone, P. D'Amico, G. Iannaccone, Nanodevices in flatland: twodimensional graphene-based transistors with high Ion/Ioff ratio, in: Electron Devices Meeting (IEDM), IEEE International, 2011, pp. 5e7.
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Highlights of the paper 1. The Improved Drain Current Saturation has been observed on a silicon substrate as
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compared to SiO2 and SiC substrates for G-FET device. 2. For better drain current saturation, we need to suppress generation of the carrier in the drain region, which is possible by using silicon substrate. 3. For better drain current saturation, two things must be considered: 1-Gapped graphene channel to suppress band to band tunneling and 2- Silicon substrate to stop the generation of the carrier near the drain region. 4. The hot electron problem can be solved by using silicon substrate for small length scale G-FET device because it minimizes the electric field near the drain region.
S0749-6036(17)32258-9
DOI:
10.1016/j.spmi.2017.11.004
Reference:
YSPMI 5339
To appear in:
Superlattices and Microstructures
Received Date: 22 September 2017 Revised Date:
2 November 2017
Accepted Date: 2 November 2017
Please cite this article as: D.L. Tiwari, K. Sivasankaran, Impact of substrate on performance of band gap engineered graphene field effect transistor, Superlattices and Microstructures (2017), doi: 10.1016/ j.spmi.2017.11.004. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
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Impact of Substrate on Performance of Band Gap engineered Graphene Field Effect Transistor Durgesh Laxman Tiwari and K. Sivasankaran*
Vellore, Tamilnadu, India
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Department of Micro and Nanoelectronics, School of Electronics Engineering VIT University Corresponding Author: [email protected]*
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Abstract:
In this paper, we investigate the graphene field effect transistor (G-FET) to enhance the drain
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current saturation and to minimize the drain conductance (gd) using numerical simulation. This work focus on suppressing the drain conductance using silicon substrate. We studied the impact of different substrate on the performance of band gap engineered G-FET device. We used a nonequilibrium green function with mode space (NEGF_MS) to model the transport behavior of carriers for 10 nm channel length G-FET device. We compared the drain current saturation of GFET at higher drain voltage regime on silicon, SiC, and the SiO2 substrate. This paper clearly
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demonstrates the effect of substrate on an electric field near drain region of G-FET device. It is shown that the substrate of G-FET is not only creating a band gap in graphene, which is important for current saturation and gd minimization, but also selection of suitable substrate can suppress generation of carrier concentration near drain region is also important.
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Introduction:
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Keyword: Graphene, Drain conductance, NEGF_MS, carrier concentration, current saturation.
Graphene is one atomic thick two-dimensional material consists of two atoms per unit cell. The px and py orbital of carbon atom make sp2 hybridization with the neighboring carbon atom in graphene, which is responsible for the high mechanical strength of graphene material. The pz orbital electron in graphene participates in electrical conductivity. Due to linear dispersion relation, the effective mass of electron in graphene become negligible, and it shows higher carrier mobility. The high carrier mobility and large saturation velocity make it most prominent material for radio frequency (RF) and analog application. Graphene materials have an enormous potential towards electronics application, but due to poor current saturation, it’s hard to use as
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field effect transistor for RF application. Great experiment and theoretical work have been done to improve the current saturation in high voltage region for G-FET device [1, 2]. Due to the zero band-gap in graphene band to band tunneling is high and current saturation becomes difficult. G-FET Operation in a thermionic region is possible when VGS
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to band tunneling, get start and saturation become weak [3]. By creating a band gap in graphene, we can improve the drain current saturation up to some extent. Unfortunately, large area graphene is zero band gap material and creating a band gap we need to cut the graphene in ribbon form which is quite difficult for large area fabrication. There is another way to improve
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the drain current saturation in graphene field effect transistor by keeping constant carrier concentration in the drain region. Therefore for more improvement and stable performance drain
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carrier concentrations should be constant throughout drain region and it is possible by selecting a suitable substrate which improves drain current saturation. The effect of nonpolar substrate on graphene electronics for radio frequency application is more promising as compared to the polar substrate [4]. A latest experimental paper has been demonstrated that silicon is the best substrate for graphene electronics for suppression of drain conductance as well as large area fabrication [5].
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Experimentally fT has been achieved up to 1.42 THz for 56 nm gate lengths [6], but the large difference between fT and fmax is the biggest problem for graphene transistor. In this paper, we simulated top gate graphene field effect transistor and analyzed its performance on silicon, SiC and the SiO2 substrate. We compare the gapped graphene performance on SiC substrate with
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gapless and gapped graphene on a silicon substrate. The minimization of drain conductance has a direct impact on current saturation therefore by creating a band-gap in graphene people are
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trying to achieve good current saturation [7]. This work demonstrates that creating a band-gap is the not only solution to achieve a current saturation but using a suitable substrate for graphene electronics is also important which can minimize the carrier generation near the drain region. The device simulation performed using SILVACO ATLAS device simulator [8].
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Device Structure and Simulation Setup:
Fig.1 Schematic view of top gate graphene field effect transistor.
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Figure 1 shows the schematic view of G-FET considered for the study. The various device and material parameters considered for the simulation are listed in Table 1 and 2. Table: 1 Device parameter for simulation of G-FET
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Channel Length (LCh) Oxide thickness (tox) Channel Thickness (Graphene) Source, Drain and Gate Contact Source Length (LS) Drain Length (LD)
10 nm 3 nm 0.35 nm Palladium 10 nm 10 nm
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Table: 2 Material parameter for graphene on different substrate. on SiO2 substrate
on SiC substrate
on Si Substrate
Band-gap Electron Mobility Carrier density Permittivity Affinity
0.0 eV [9] 40,000 cm2v-1s-1 [12] 1012 cm-2 [12] 3.3 [15] 4.248 [17]
0.26 eV [10] 18,1000 cm2v-1s-1[13] 3x1011 cm-2 [14] 3.3 [16] 4.248 [17]
0.0 eV [11] 2,000 cm2v-1s-1 [11] 1.1x1011 cm-2 [11] 3.3 [16] 4.248 [17]
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Electrical Properties
Graphene is not an inbuilt material in SILVACO ATLAS tool. Therefore, we used user defined function to define graphene material [18]. To incorporate the 2-D nature of electron transport in G-FET device, we used 1DY geometry method for Schrödinger solution. The 1DY geometry is used to activate the confinement of electron motion in the Y direction. In this paper, we used NEGF_MS model to simulate device for 10nm channel length. We assumed ballistic transport in
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graphene for 10nm length scale, and used Von-Neumann boundary condition near the source and drain contact region. A self-consistent solution of Schrödinger-Poisson equation in NEGF method with effective mass approximation is most accurate for graphene device simulation. In NEGF_MS method self-energy term is the most important which takes care of graphene-metal
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contact up to atomic scale limit [19]. The atomistic approach of NEGF method helps to find the hidden behavior of graphene transistor for sub 10 nm length scale which is not possible by any other transport method. Self-consistent solution of Schrödinger-Poisson equation is used to find the charge and potential distribution along the channel. The potential values are used to find the
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Green’s function, retarded Green’s function and advanced Green function along the channel of the device and all these values are used to find transmission, current and carrier concentration of
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the device along the channel in most accurate form. We have activated Schrödinger-Poisson method for a self-consistent solution in ATLAS device simulator. The equation 1 and 2 are in the matrix form, and the size of the matrix depends on the number of basis element and nodal points in a given meshing condition. We used 3C-SiC as a user define material for graphene of 0.35 nm thick channel and set the relevant parameters as given in Table 1 and 2 to simulate the G-FET device.
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The Green’s function formalism can be expressed as [20] G[( E + i 0 + ) I − H + IUg − ∑ S − ∑ D ] = I ⋅
(1)
where H represents the Hamiltonian matrix in mode space with diagonal and off diagonal
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elements, and off diagonal elements corresponds to the hopping energy of electron from one lattice site to another lattice site. E corresponds to electron or hole energy and I, Ug represent the
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identity matrix and potential energy of channel respectively. ∑S and ∑D stand for self-energy term for source and drain contact which is important for an incoming and outgoing electron from source and drain region.
[
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T = Trace Γ s G R Γ D G R† ⋅
(2)
Equation 2 represents the transmission matrix of the device which consists of broadening of energy level, Γ S and Γ D . Broadening term near the source and drain contact with retarded and advanced Green's function explains the motion of electron from source to drain through the channel region. The current equation can be obtained by using Landauer formalism which
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consists of transmission and Fermi function difference between the source and drain contact as shown in Equation 3. 2q h
∞
∫ T (E )[( f (E ) − L
f R (E ))]dE ⋅
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0
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I =
Carrier density in the device is taken care by equation 4, where L is channel length, G 〈 mn represent the less than Green's function for m and n state, Ψ m and Ψn represent the mth and nth wave function. In general G 〈 mn is the correlation function between two state m and n and the
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diagonal term of correlation function gives the information of carrier density as a function of energy in the system. n( x, y) = −i / L∑ ∫ G〈 mn ( E)Ψm ( y)Ψn ( y)dE / 2π ⋅
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Reference (Vds=0.5V)
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Fig.2 ID-VG characteristics of graphene FET device for SiO2 substrate
Fig.2 shows the simulation comparison of published result for G-FET device on SiO2 substrate. We used NEGF_MS electron transport model to match reference result [21]. Our simulated result based on effective mass Hamiltonian and the reference result is based on nearestneighbour tight binding Hamiltonian. For the modeling of the device with transverse confinement, it is more important to use Von-Neumann boundary condition near contact region. By assuming the ballistic transport of electron for 10 nm channel length we used Von-Neumann
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boundary condition near the source and drain contact region. In ATLAS, we specified REFLECT statement to activate Von-Neumann boundary condition.
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Result and Discussion:
A. Effect of drain carrier density on current saturation Fig.3 shows the comparison of drain current saturation on silicon and SiO2 substrate for 10 nm channel length. We can see that for VGS
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based graphene FET but in the case of Silicon substrate based G-FET current saturation is excellent. By creating a band gap in a graphene, we can solve the problem of poor current
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saturation up to some extent by suppressing the band to band tunneling in zero band-gap G-FET. But for better result and stable performance, we have to choose a silicon substrate for graphene electronics. In the case of the silicon substrate, the same polarity charge ion as like channel generates at the drain-substrate interface due to applied drain voltage. This charge carrier increases with the increase of drain bias and prevents the generation of drain carrier concentrations. Below Fig.4 explains the mechanism behind the better performance of silicon
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substrate over SiO2 for G-FET. Due to applied negative drain voltage positive ion gets induce from the silicon substrate to prevent the shifting of Fermi level in conduction band as shown by upward pulling arrow. This pulling of bands near drain region is responsible for maintaining constant carrier concentration in drain region to improve the current saturation. Region I, II, III
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corresponds to linear, saturation and hole inversion or electron inversion region for dc output characteristics of G-FET. A drain voltage increases the saturation area is large in the case of
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silicon substrate G-FET as compared to SiO2 substrate G-FET. In a case of SiO2 substrate based G-FET, there is no induced charge ion from the substrate to suppress the drain carrier concentration. Therefore, saturation area (region II) is less in SiO2 substrate G-FET.
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Fig.3 ID-VDS characteristics for 10nm channel length on Si and SiO2 substrate for different gate voltages (0.45V, 0.50V, 0.55V). Suppression of drain carrier generation on the drain is a very important aspect for graphene field effect transistor, in particular for analog and radio frequency applications. Therefore for more elaboration, we plotted the drain carrier concentrations vs. drain region of G-FET device on
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different drain bias as shown in Fig.5. Analysis of carrier density by using mode space approach is most accurate and efficient way because computational time is very less as compare to real space approach [22]. The solution of Schrödinger equation for Eigen function and Eigen energy in decoupled mode space for each subband on every nodal point is the important part of transport
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method to capture a variation of carrier concentration in the drain region. The Fig.5 graph indicates that in the case of the SiO2 substrate carrier density increased linearly throughout drain region for higher drain voltage which corresponds to weak current saturation as shown in Fig.3
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near higher drain voltages (0.5, 0.4). Simulation result indicates the poor saturation is more dominating for small positive gate voltages (0.45, 0.50). In the case of n-channel for higher drain voltage region, the lateral carrier density modulation effect on G-FET current saturation is more in SiO2 based G-FET [23]. In the event of the silicon substrate, the carrier concentration is constant throughout drain even in a case of higher drain voltages (0.5, 0.4) because lateral carrier density modulation gets suppressed due to induced positive charge from silicon substrate near the drain region.
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Fig.4 Silicon and SiO2 substrate based top gate G-FET with output characteristics I, II and III corresponds to linear, saturation and hole inversion region respectively.
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Fig.5 Charge concentration versus Distance along the channel in drain region for 10 nm channel length for SiO2 and Silicon for different VDS. B. Effect of band-gap on current saturation We also studied the effect of the band gap of graphene on the current saturation and compared with zero band gap graphene G-FET on a silicon substrate. DC output characteristics show that in the case of zero band gap current saturation is poor on the silicon substrate as compared to
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non-zero band gap G-FET for high drain voltage region as shown in Fig. 6a. There is minuscule non-saturation of the drain current in case of G-FET with a silicon substrate as shown in Fig6.a, however, this can be eliminated by introducing a band gap in graphene. Fig.6b shows that the problem of current saturation is not solved completely after introducing a band gap in graphene
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on SiC substrate G-FET in higher drain voltage region. From Fig.7 we can observe that at 0.8V Vds supply, charge carrier concentration is linearly increasing in case of gapped graphene G-FET on SiC substrate which is not observed in case of zero band gap G-FET on a silicon substrate. Therefore we can say that silicon substrate suppresses the carrier generation in G-FET near the
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drain region.
However, for gapless G-FET on a silicon substrate, the drain current is increased with increasing
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drain voltage. The drain current increment in gapless G-FET on a silicon substrate is not very sharp as like in a case of gapped graphene on SiC substrate. The non-saturation of current on a silicon substrate gapless G-FET is due to the zero band gap of graphene channel in which electron band to band tunneling phenomena dominates [24], therefore after introducing a band gap of 0.26 eV in graphene channel drain current saturation becomes better in case of silicon. 50
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Fig.6(a) Comparison of ID vs VDS of gapped and gapless graphene on silicon substrate (b) ID vs VDS graph of gapped graphene with band gap of 0.26 eV on SiC substrate.
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The energy band diagram of gapless and gapped graphene channel on silicon substrate G-FET
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device for 0.45V and 0.60V gate and drain voltage respectively shown in Fig. 8. The energy gap between conduction band and valence band reduces the band to band tunneling possibility near the source and drain region. Therefore current saturation becomes better as shown in Fig.6a for gapped graphene channel FET as compared to gapless graphene channel FET on silicon
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substrate. Therefore for proper saturation, we need to use gapped graphene on silicon substrate because gapped graphene suppresses band to band tunneling and silicon substrate prevent the
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generation of a carrier in the drain region of G-FET device.
Fig8.(a)
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Fig8.(b)
Fig8. (a) Energy band diagram of gapless graphene G-FET on a silicon substrate, (b) Energy band diagram of gapped graphene G-FET on a silicon substrate. Figure 9 shows the transfer characteristics of G-FET on different substrate with 10 nm channel length by using NEGF_MS method. We compared the transfer characteristics for
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gapless graphene on the SiO2 substrate with gapped graphene on SiC substrate. Fig.9 demonstrates that in the case of gapped graphene device, the off current decreases drastically as compared to gapless graphene G-FET. The shifting of dirac point in case of gapless graphene FET on SiO2 is more which corresponds to a significant amount of band to band tunneling as
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compared to gapped graphene as shown in Fig.9. In Fig.10 transfer characteristics of G-FET on silicon substrate is symmetric; p-branch and n-branch are showing symmetry behavior for
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positive and negative gate voltage. In the case of gapped graphene on SiC, p-branch and nbranch are not symmetry which corresponds to high contact resistance [25]. From Fig.10 we find that for a small value of gate voltage conductivity is very less, it shows most of the current is thermionic current and it is important for field effect transistor application. Drain current slope is very high in G-FET on the silicon substrate as compared to SiC G-FET; it means transconductance is greater in G-FET on a silicon substrate.
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Fig. 9 Transfer characteristics of G-FET for 10 nm channel on SiC with gapped graphene and the SiO2 substrate with gapless graphene. Vds=0.4V(SiC-Sub.)
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Fig.10. Comparison of the transfer characteristics of gapped graphene (Eg=0.26ev) on SiC substrate with gapless graphene on a silicon substrate.
C. Effect of Silicon substrate on electric field near drain region In this section we studied and compared the hot electron problem on silicon and the SiO2 substrate [26]. Hot electron effect is due to the high electric field near the drain region. The proper study of a high electric field near drain region is possible for minimum gate voltage; therefore, we used zero gate voltage [27]. Simulation has been carried out for different VDS values 0.6V, 0.8V and 1.0V respectively. Fig.11 shows that electric field across drain and
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channel junction region, in case of SiO2 substrate G-FET the electric field is high as compared to silicon substrate based G-FET device. This electric field has the direct impact on leakage current and breakdown voltage of the device. In the case of a high electric field near the drain region, electron gets tunnel through oxide and increase of gate leakage current [28]. With the rapid raise
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of drain voltage, electric field gets reduced in drain region in case of silicon substrate G-FET, the difference is quite large in the case of VDS is equal to 1V. Gate tunneling current is one of the biggest problems for short channel graphene device, and it can be solved by using silicon
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Silicon Vds=1V
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Fig 11- Electric field versus distance along the channel of G-FET device in drain region for different drain voltage ranging from 0.6 to 1.0 volt.
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Fig.13. Drain conductance vs drain voltage of gapless graphene FET on silicon and the SiO2 substrate and gapped graphene FET on SiC.
D. Transconductance and drain conductance of G-FET device In this section we have analyzed the analog and radio frequency performance of G-FET. We found that transconductance (gm) is higher in the case of G-FET on a silicon substrate as
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compared to G-FET on SiO2 and gapped graphene on SiC substrate G-FET. Another important parameter is fmax which is highly influenced by gd, can achieve maximum value by minimizing gd
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or in other words by improving drain current saturation [29, 30]. The gd plot is shown in Fig.13 and 14 where different substrate are compared along with gapped and gapless graphene FET. Our simulation result clearly demonstrates the importance of gapped graphene as a channel material along with silicon substrate for radiofrequency application in G-FET. From simulation result as shown in Fig.13, it is found that gd increases in case of SiO2 substrate G-FET, though gd for gapless graphene FET is slightly higher for a higher value of drain voltage as compare to gapped graphene on SiC substrate G-FET. This is the quite improved performance of gapless graphene-FET on a silicon substrate. In the case of Fig.14, we compared the drain conductance for gapped graphene FET on silicon and SiC substrate for higher drain voltage up to 0.65 volts.
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We found out gapped graphene with the silicon substrate is the best combination of G-FET device for radio frequency application.
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Gapped Graphene on Silicon Sub. Gapless Graphene on Silicon Sub. Gapped Graphene on SiC Sub.
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Conclusion:
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Fig. 14. Drain conductance vs Drain voltage of gapless and gapped graphene G-FET on a silicon substrate and gapped graphene G-FET on SiC substrate.
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Based on our simulation study we conclude that for better current saturation in G-FET we need gapped graphene as a channel material and silicon as substrate. The role of gapped graphene is to
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suppress the band to band tunneling, and the silicon substrate is to prevent the carrier generation in the drain region. The simulation results show the importance of silicon substrate over SiO2 and SiC substrate for G-FET device. The problem of gate leakage current for short channel length device can be solved by using silicon substrate because it is minimizing the electric field near the drain region. By using silicon substrate, large area fabrication problem can be solved for G-FET device with existing technology. It is evident from the simulation that the silicon substrate will be the promising material for graphene electronics because it improves drain current saturation.
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Reference:
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Highlights of the paper 1. The Improved Drain Current Saturation has been observed on a silicon substrate as
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compared to SiO2 and SiC substrates for G-FET device. 2. For better drain current saturation, we need to suppress generation of the carrier in the drain region, which is possible by using silicon substrate. 3. For better drain current saturation, two things must be considered: 1-Gapped graphene channel to suppress band to band tunneling and 2- Silicon substrate to stop the generation of the carrier near the drain region. 4. The hot electron problem can be solved by using silicon substrate for small length scale G-FET device because it minimizes the electric field near the drain region.