- Email: [email protected]
Effect of ITC's on linearity and distortion performance of Junctionless tunnel field effect transistor
Accepted Manuscript Effect of ITC's on linearity and distortion performance of Junctionless tunnel field effect transistor Bhaskar Awadhiya, Sunil Pandey, Kaushal Nigam, Pravin N. Kondekar PII:
S0749-6036(17)30961-8
DOI:
10.1016/j.spmi.2017.06.036
Reference:
YSPMI 5085
To appear in:
Superlattices and Microstructures
Received Date: 18 April 2017 Revised Date:
8 June 2017
Accepted Date: 8 June 2017
Please cite this article as: B. Awadhiya, S. Pandey, K. Nigam, P.N. Kondekar, Effect of ITC's on linearity and distortion performance of Junctionless tunnel field effect transistor, Superlattices and Microstructures (2017), doi: 10.1016/j.spmi.2017.06.036. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
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Effect of ITC’s on Linearity and Distortion Performance of Junctionless Tunnel Field Effect Transistor Bhaskar Awadhiya, Sunil Pandey, Kaushal Nigam, Pravin N. Kondekar
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Nanoelectronics and VLSI Laboratory, Electronics and Communication Engineering Discipline PDPM Indian Institute of Information Technology, Jabalpur, 482005, India.
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This paper presents an extensive survey on impact of interface trap charges on JLTFET. Objective of our work is to analyze degradation in performance of our device due to presence of interface trap charge present between Si-SiO2 interface. Effect of interface trap charges on drain current, transconductance, higher order transconductance, linearity and distortion parameter (VIP2, VIP3, IIP3, IMD3, Zero crossover point, 1-dB compression point) has been studied. High linearity and low distortion demands high value of VIP2, VIP3, IIP3, 1-dB compression point and low value of IMD3, Zero crossover point, higher order transconductance parameter. Through our simulations we have found that presence of interface trap charges leads to curtailment in reliability and life time of device.
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Keywords: Third order intercept point (IIP3), Third order intermodulation distortion (IMD3), Junction less tunnel field effect transistor (JLTFET), Interface trap charges (ITC), Zero crossover point (ZCP).
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1. Introduction
Tremendous growth in modern communication systems has increased the demand for the devices possessing good RF characteristics. However majority of RF studies gives their main emphasis on understanding certain analog
Email addresses: [email protected] (Bhaskar Awadhiya), [email protected] (Sunil Pandey), [email protected] (Kaushal Nigam), [email protected] (Pravin N. Kondekar)
Preprint submitted to Elsevier
June 9, 2017
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Figure 1: Cross sectinal view of Junction less tunnel field effect transistor
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parameters such as transconductance, transconductance generation factor, cut off frequency, maximum oscillation frequency which are important figure of merits in analog design but still certain figure of merits like linearity and distortion is still left untouched. Linearity is an extremely important parameter for ensuring low intermodulation distortion at the output of amplifier. Variation in linearity parameter with interface trap charges is extremely important issues as these trap charges shift the bias point and these charges are always present in real devices. There are several papers which show the effect of interface trap charge on linearity of TFET (Tunnel field effect transistor) [1], MOSFET (Metal oxide field effect transistor) [2], JLFET (Junction less field effect transistor) [3]. However the effect on interface trap charge on linearity of JLTFET (Junction less tunnel field effect transistor) is still left unstudied. Rapid scaling in CMOS technology has increased second order effects and leakage in CMOS devices which leads to high power dissipation. TFET has drawn the attention of researchers as it is immune to short channel effects i.e. channel length scaling has no effect on TFET characteristics. Despite all these benefits TFET suffers from problem of low ON current and high threshold voltage. Also scaling in dimension leads to large doping concentration gradient requirement and hence increases the thermal budget. For solution of this problem Junctionless transistor [4] was proposed by J.P.Colinge, in which fabrication is lot simpler as compared to conventional MOSFET. Recently JLTFET [5] was proposed by B. Ghosh which amalgamates advantages of TFET and JLFET and hence shows tremendous potential in term of high ON current and low subthreshold slope. So in this paper we have studied the effect on interface trap charge on linearity and distortion performance of JLTFET. Other than short channel immunity, device 2
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reliability has always been a matter of concern. Interface charge at Si-SiO2 interface always creates reliability issues. These charges are developed at the interface during the fabrication process itself. Interface charges may be stress induced [6], process induced [7] or may be radiation induced [8]. Genesis of interface trap charges is basically because of Si dangling bonds. These bonds are present at the interface of silicon and silicon dioxide. Now as oxidation on silicon surface is carried out oxygen reacts with silicon and satisfies plethora of dangling bonds and count of dangling bonds is minimized, but still there is a possibility that post oxidation some dangling bonds are present which are the major cause of interface trap charges. Interface charges are present all over the forbidden energy gap and depending upon the Fermi level they can be either empty or filled. So as the gate voltage is applied, bands bends up or down depending upon the type of input applied at the gate and these interface states changes their occupancy and hence their electronic activity changes and correspondingly affect the device performance. Donor interface trap acts as positive interface trap charge when it’s empty and neutral charge when it is filled with electron. Acceptor interface charges acts as negative interface trap when filled with an electron and neutral charge when it is empty. In JLTFET, high value of electric field is desirable at the tunneling junction (between source and channel) for lowering the tunnel barrier. But lowering the tunneling barrier results increase in the electric and generation of interface trap charges. These interface traps present in Si-SiO2 interface results in degradation of electric field (BTBT rate is proportional to exp (-A/Ey)6 ) and hence tunnelling current and linearity and distortion performance of the device. Other than electric field negative bias temperature instability and positive bias temperature instability also leads to generation of interface trap charges [9].
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2. Device Structure, Simulation and Operation Figure 1 shows cross sectional view of JLTFET which was implemented using Silvaco ATLAS device simulation tool. Simulated structure has a doping concentration of 1×1019 cm−3 with channel length of 50 nm, source-drain extension of 50 nm and a spacer length of 5 nm between Control gate and P-gate. Thickness of gate dielectric (SiO2 ) used is taken as 0.8 nm. BTBT non local model has been used to account current for our device. Band gap narrowing (BGN) model is used as high doping concentration is applied source channel and drain region. Shockley read hall (SRH) model has also 3
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been incorporated to account leakage current in the device. Trap assisted tunnelling (TAT) model given by Schenk has also been considered in our simulation. Thickness of silicon wafer is taken to 10 nm hence we have restricted ourselves from applying Quantum confinement (QC) model which is generally considered when thickness is below 10 nm. Silicon wafer thickness is well within debye length (L D =(Si .VT /q.N)1/2 ), which is essential for applying charge plasma concept. Here Si represents dielectric constant of silicon whereas VT , q and N represents thermal voltage, electronic charge, and doping concentration in silicon layer respectively. The basic goal over here is to transform N+ - N+ - N+ to structure N+ - I - P+ without applying any doping to the structure and to operate it as JLTEFT. For introducing the hole plasma the work function of metal must follow the mentioned limitation (φm > χSi + Eg /2 - φf n ), hence we have used platinum whose work function is 5.93 as P-gate metal to introduce hole plasma. For introducing the electron plasma the work function of metal must follow the mentioned limitation (φm < χSi + Eg /2 - φf n ), hence we have used titanium whose work function is 4.3 as control gate to introduce electron plasma. Here Si and Eg are electron affinity and band gap of silicon. φf n indicates difference in Fermi level of intrinsic and doped silicon (in eV). In order to study reliability issues, effect of interface trap charges has been transformed into positive and negative localised charges. The value of interface trap charge density is taken as 1011 -1013 cm−2 eV −1 which has been taken after considering process, radiation and hot carrier damage effects which is studied in [10] [11]. For accounting minimum change, value of positive and negative charge density is taken as 1012 and −1012 cm−2 respectively. 3. Impact of ITC on device properties
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Figure 2(a) shows effect positive and negative trap charges on nonlocal band to band tunneling. It is lucidly visible from the figure that existence of negative (positive) interface trap charges suppresses (enhances) the nonlocal band to band tunneling in the device when compared with zero interface trap charge. The increment (decrement) in band to band tunneling is because of decrement (increment) in flat band voltage and this decrement (increment) in the flat band voltage results in decrement (increment) of band bending of valence and conduction band. Figure 2(b) shows the variation of electric field variation for positive, negative and zero interface trap charge. Electric field is enhanced (suppressed) for positive (negative) interface traps 4
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Figure 2: (a) Nonlocal band to band tunneling rate, and (b) Electric field near source to channel junction for positive, negative and zero interface trap charges
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Figure 3: (a) Transfer characteristics and (b) Transconductance (gm1 ) characteristics of JLTEFT for positive, negative and zero interface trap charges.
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because of higher (lower) band bending when compared with zero interface trap charges. Figure 3(a) shows the variation of transfer characteristics with different ITCs along gate bias. As mentioned in above statements, positive (negative) interface trap charges increases(decreases) band to band tunneling rate, and thus resulting an increase (decrease) in ON current with different ITCs. Variation in transconductance with gate voltage in presence of trap charges is shown in Figure 3(b). It is clearly visible from this figure that the presence of interface trap charges leads to a shift in transconductance characteristics. For positive (negative) interface trap charges, transconductance is higher (lower) as compared to zero interface trap charge.
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4. Performance metrics for linearity and intermodulation parameter
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Linearity and intermodulation distortion performance of device can be analysed by certain figure of merits which are VIP2, VIP3, IIP3, IMD3, 1-dB compression point, zero crossover point and higher order transconductance parameter (which includes gm2 , gm3 ) which are defined as: δ n Ids gm1 , gmn = (1) V IP 2 = 4 × gm2 δVgsn s gm1 (2) V IP 3 = 24 × gm3 2 gm1 IIP 3 = × (3) 3 gm3 × Rs 2 9 3 × (V IP 3) × (gm3 ) × Rs (4) IM D3 = 2
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where, Rs = 50 Ω is generally chosen for RF application. Second order transconductance (gm2 ) is defined as second derivative of drain current with respect to gate voltage. Third order transconductance (gm3 ) is defined as third derivative of drain current with respect to gate voltage. Higher order transconductance governs limit on distortion [12], hence both (gm2 and gm3 ) should be low in amplitude for achieving low distortion. Zero crossover point (ZCP) is that point in Vgs axis where the third order transconductance (gm3 ) is zero. ZCP decides DC bias point for device operation [13] and it should be close to threshold voltage (Vth ) for obtaining high gain. Also low value of zero crossover point ensures that we are getting high linearity at low value of Vgs . Getting high linearity and low voltage bias is good for portable RF application [14]. 1-dB compression point is defined as power level at which output power is decreased by 1-dB when compared with ideal linear characteristics; this point is considered as on-set on distortion [1] and also tells largest input signal that can be handled by the device without distortion [15]. Hence it is desirable to have high value of 1-dB compression point because it tells maximum power, amplifier can handle by supplying fixed gain and if the power increases after this point, gain starts falling. VIP2 is the extrapolated input voltage at which first order harmonic voltage term (ω 1 ) is equal to second order harmonic voltage term (ω 2 ). It is the extrapolated input voltage at 7
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Figure 4: (a) Second order transconductance (gm2 ) coefficient and (b) Third order transconductance (gm3 ) coefficient along gate bias for positive, negative and zero interface trap charges.
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Figure 5: (a) Zero crossover point and (b) Transconductance as a function of drain current of JLTFET for positive, negative and zero interface trap charges.
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which first order harmonic voltage term (ω 1 ) is equal to third order harmonic voltage term (ω 3 ). VIP3 is heavily dependent on gate voltage and drain current [16]. Peak in VIP3 should occur at lower value of gate voltage, shifting of peak of VIP3 towards higher value of Vgs indicates poor control of gate over the channel and high value of gate voltage is required to attain linearity. Third order intercept point [17] (IIP3) represents extrapolated input power at which third order intermodulation voltage term (2ω 2 - ω 1 ) is equal to first order harmonic voltage (ω 1 ). High value of third order intercept point is desirable for high linearity. Third order intermodulation distortion (IMD3) represents extrapolated intermodulation power at which first order harmonic power is equivalent to third order intermodulation harmonic power. Low 9
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5. Impact of ITC on linearity performance
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value of IMD3 is requires for low distortion [18]. Other than all these parameters transconductance versus drain current characteristics is also one of the parameter to judge the linearity. Wide and flat transconductance versus drain current curve ensures suppression of gm3 amplitude and high linearity of device [19]. Although flattening of curve will reduce the gm1 slightly.
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Linearity performance of devices in high frequency range can be estimated by experimental process which needs device to be fabricated. This process is time killing and extravagant. Hence linearity here is estimated using performance metrics. Linearity is one of the important parameter which ensures no intermodulation components at the output. For a system to be linear transconductance must be remain constant over the entire range of the input voltage, but transconductance of neither MOSFET nor TFET is independent of input voltage, which shows the nonlinear behavior of device. Transconductance and higher order transconductance put constraints on lower limits of distortion hence amplitude of higher order transconductance should be minimal. Figure 4(a) shows variation of gm2 with respect to gate voltage, at higher value of Vgs , gm2 is lesser (higher) for positive (negative) interface charge when compared with zero interface charge. Similarly in Figure 4(b) at higher value of Vgs , amplitude of gm3 is lesser (higher) for positive (negative) interface trap charge than zero interface charge. Also from Figure 4(b) it is clearly evident that interface charges leads to shifting of zero crossover point. For positive (negative) interface charges the zero cross over point is at lower (higher) value of Vgs than zero interface charge which is separately shown in Figure 5(a). Transconductance versus drain current characteristics is shown in Figure 5(b), flatter transconductance versus drain current curve indicate higher linearity, for positive (negative) interface charge the transconductance versus drain current is more (less) flatter than zero interface charge. For better linearity VIP2, VIP3 and IIP3 should be high, from Figure 6(a), 6(b) and 7(a) it is clearly evident that for positive (negative) interface trap charges peak value of VIP2, VIP3 and IIP3 increases (decreases) as compared to zero interface charge. Figure 7(b) shows the impact of interface trap charge on 1-dB compression point. Positive (negative) interface trap charge exhibits higher (lower) value of 1-dB compression point as compared to zero trap charge.
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Figure 6: (a) VIP2 and (b) VIP3 as function of gate to source voltage for positive, negative and zero interface trap charges.
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Figure 7: (a) IIP3 and (b) 1-dB compression point for positive, negative and zero interface trap charges.
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Figure 8: IMD3 as function of gate to source voltage for positive, negative and zero interface trap charges.
6. Impact of ITC on distortion performance
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Intermodulation distortion arises because of non-linearity present in the device. When a two tone input signal is applied to system exhibiting non linearity then output contains harmonics, higher order harmonics of input frequency and intermodulation components which are sum or difference of input frequencies. These harmonics and intermodulation components lead to distortion if these frequency components fall into band of interest at the output. Figure 8 shows impact of interface charge IMD3. Positive (negative) interface trap charge has lower (higher) value of IMD3 when compared to zero interface trap charge.
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7. Conclusion
Effect of localised interface trap charges has been studied on linearity, distortion and device parameters of JLTFET. Conclusions that can be taken out from these extensive simulations are the presence of interface trap charges leads to shift in flat band voltage, and thus band bending which in turn modifies tunneling barrier and hence transfer characteristics, linearity and distortion parameters. Simulations clearly indicate that presence of localised charges degrades the parameters in subthreshold, linear and saturation region. However in most of the amplifiers, FET operates in either saturation
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or linear region hence performance degradation of amplifier will be there because of presence of interface trap charges. Also the presence of localised charges leads to alteration in the bias point which is unfavorable of circuit reliability. Since these interface trap charges are present in the device, so study impact of these charges on device performance is necessary so that the device can optimised accordingly.
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References
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[1] J. Madan and R. Chaujar, “Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability,”IEEE Transactions on Device and Materials Reliability, vol. 16, no. 2, pp. 227-234, June. 2016. [2] R. Gautam, M. Saxena, R. S. Gupta, and M. Gupta, “Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: Analog performance and linearity analysis,”Microelectron. Reliab., vol. 25, no. 6, pp. 989-994, Jun. 2012.
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[3] Y. Pratap, S. Haldar, R.S. Gupta and M. Gupta, “Performance evaluation and reliability issues of Junctionless CSG MOSFET for RFIC design, ”IEEE Transactions on Device and Materials Reliability., vol. 14, no. 1, pp. 418-425, Mar. 2014.
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[4] J.-P. Colinge, C.W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, et al. “Nanowire transistors without junctions,”Nat. Nanotechnol., vol. 5, no. 3, pp. 225-229, Mar. 2010. [5] B. Ghosh, M.W. Akram,“Junction Less Tunnel Field Effect Transistor”IEEE Electron Device Lett., vol. 34, no. 5, pp. 584-586, May 2014.
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[6] L. Trabzon and O. Awadelkarim, “Damage to n-MOSFETs from electrical stress relationship to processing damage and impact on device reliability,”Microelectron Reliab., vol. 38, no. 4, pp. 651-657, Apr. 1989. [7] E. H. Poindexter, “MOS interface states: Overview and physicochemical perspective,”Semicond. Sci. Technol., vol. 4, no. 12, pp. 961-969, Dec. 1989. [8] Y. H. Lho and K. Y. Kim, “Radiation effects on the power MOSFET for space applications,”ETRI J., vol. 27, no. 4, pp. 449-452, Aug. 2005. 14
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[9] Y. Qiu, R. Wang, Q. Huang and R. Huang, “A comparative study on the impacts of interface traps on tunneling FET and MOSFET, ”IEEE Trans. Electron Devices, vol. 61, no. 5, pp. 1289-1291, May 2014. [10] T. Chiang, “A compact model for threshold voltage of surrounding gate MOSFETs with localized interface trapped charges,”IEEE Trans.Electron Devices, vol. 58, no. 2, pp. 567-571, Jan. 2011.
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[11] S. Shabde, A. Bhattacharyya, R. S. Kao, and R. S. Muller, “Analysis of MOSFET degradation due to hot-electron stress in terms of interface state and fixed-charge generation,”Solid State Electron., vol. 31, no. 11, pp. 1603-1610, Nov. 1988. [12] P. Ghosh, S. Haldar, R. S. Gupta, and M. Gupta, “An investigation of linearity performance and intermodulation distortion of GME CGTMOSFET for RFIC designs,”IEEE Trans. Electron Dev., vol. 59, no. 12, pp. 3263-3268, Dec. 2012.
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[13] N. Gupta, R. Chaujar, “Optimization of high-k and gate metal workfunction for improved analog and intermodulation performance of Gate Stack (GS)-GEWE-SiNW MOSFET,”Superlattices and Microstructures., vol. 97, no. 12, pp. 630-641, Sep. 2016.
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[14] Yi Song, Chen Zhang, R. Dowdy, K. Chabak, P. K. Mohseni, Wonsik Choi, and Xiuling Li “III-V Junctionless Gate-All-Around Nanowire MOSFETs for High Linearity Low Power Applications,”IEEE Electron Device Letters, vol. 5, no. 3, pp. 324-326, Mar. 2014.
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[15] S.P.Kumar, A.Agrawal, R.Chaujar, R.S.Gupta, “Device linearity and intermodulation distortion comparision of dual material gate and conventional AlGaN/GaN high electron mobility transistor, ”Microelectronics Reliability,, vol. 3, no. 10, pp. 587-596, March. 2011. [16] Woerlee PH, Knitel MJ, Langevelde RL, Klaassen DBM, Tiemeijer LF, Scholten AJ, “RF-CMOS performance trends, ”IEEE Trans. Electron Dev., vol. 48, no. 8, pp. 1776-1781, Aug. 2001. [17] B. Razavi, ”RF Microelectronics., EnglewoodCliffs , NJ: Prentice-Hall 1998.
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[18] G. Niu, Q. Liang, J. D. Cressler, C. S. Webster, and D. L. Harame, “RF linearity characteristics of SiGe HBTs,”IEEE Trans. Microw. Theory Tech., vol. 49, no. 9, pp. 1558-1565, Sep. 2001.
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[19] Y.-J. Chan and M.-T.Yang, “Device linearity improvement by Al Ga As/In Ga As heterostructure doped-channel FETs,”IEEE Electron Device Lett., vol. 16, no. 11, pp. 33-35, Jan. 1995.
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Dear Editor, In this manuscript, the basic highlight are:
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Effect of interface trap charges on drain current, transconductance, and higher order transconductance and linearity and distortion parameter (VIP2, VIP3, IIP3, IMD3, zero crossover point, 1-dB compression point).
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High linearity and low distortion demands high value of VIP2, VIP3, IIP3, 1-dB compression point and low value of IMD3, zero crossover point and higher order transconductance parameter.
S0749-6036(17)30961-8
DOI:
10.1016/j.spmi.2017.06.036
Reference:
YSPMI 5085
To appear in:
Superlattices and Microstructures
Received Date: 18 April 2017 Revised Date:
8 June 2017
Accepted Date: 8 June 2017
Please cite this article as: B. Awadhiya, S. Pandey, K. Nigam, P.N. Kondekar, Effect of ITC's on linearity and distortion performance of Junctionless tunnel field effect transistor, Superlattices and Microstructures (2017), doi: 10.1016/j.spmi.2017.06.036. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
ACCEPTED MANUSCRIPT
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Effect of ITC’s on Linearity and Distortion Performance of Junctionless Tunnel Field Effect Transistor Bhaskar Awadhiya, Sunil Pandey, Kaushal Nigam, Pravin N. Kondekar
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Nanoelectronics and VLSI Laboratory, Electronics and Communication Engineering Discipline PDPM Indian Institute of Information Technology, Jabalpur, 482005, India.
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Abstract
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This paper presents an extensive survey on impact of interface trap charges on JLTFET. Objective of our work is to analyze degradation in performance of our device due to presence of interface trap charge present between Si-SiO2 interface. Effect of interface trap charges on drain current, transconductance, higher order transconductance, linearity and distortion parameter (VIP2, VIP3, IIP3, IMD3, Zero crossover point, 1-dB compression point) has been studied. High linearity and low distortion demands high value of VIP2, VIP3, IIP3, 1-dB compression point and low value of IMD3, Zero crossover point, higher order transconductance parameter. Through our simulations we have found that presence of interface trap charges leads to curtailment in reliability and life time of device.
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Keywords: Third order intercept point (IIP3), Third order intermodulation distortion (IMD3), Junction less tunnel field effect transistor (JLTFET), Interface trap charges (ITC), Zero crossover point (ZCP).
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1. Introduction
Tremendous growth in modern communication systems has increased the demand for the devices possessing good RF characteristics. However majority of RF studies gives their main emphasis on understanding certain analog
Email addresses: [email protected] (Bhaskar Awadhiya), [email protected] (Sunil Pandey), [email protected] (Kaushal Nigam), [email protected] (Pravin N. Kondekar)
Preprint submitted to Elsevier
June 9, 2017
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ACCEPTED MANUSCRIPT
Figure 1: Cross sectinal view of Junction less tunnel field effect transistor
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parameters such as transconductance, transconductance generation factor, cut off frequency, maximum oscillation frequency which are important figure of merits in analog design but still certain figure of merits like linearity and distortion is still left untouched. Linearity is an extremely important parameter for ensuring low intermodulation distortion at the output of amplifier. Variation in linearity parameter with interface trap charges is extremely important issues as these trap charges shift the bias point and these charges are always present in real devices. There are several papers which show the effect of interface trap charge on linearity of TFET (Tunnel field effect transistor) [1], MOSFET (Metal oxide field effect transistor) [2], JLFET (Junction less field effect transistor) [3]. However the effect on interface trap charge on linearity of JLTFET (Junction less tunnel field effect transistor) is still left unstudied. Rapid scaling in CMOS technology has increased second order effects and leakage in CMOS devices which leads to high power dissipation. TFET has drawn the attention of researchers as it is immune to short channel effects i.e. channel length scaling has no effect on TFET characteristics. Despite all these benefits TFET suffers from problem of low ON current and high threshold voltage. Also scaling in dimension leads to large doping concentration gradient requirement and hence increases the thermal budget. For solution of this problem Junctionless transistor [4] was proposed by J.P.Colinge, in which fabrication is lot simpler as compared to conventional MOSFET. Recently JLTFET [5] was proposed by B. Ghosh which amalgamates advantages of TFET and JLFET and hence shows tremendous potential in term of high ON current and low subthreshold slope. So in this paper we have studied the effect on interface trap charge on linearity and distortion performance of JLTFET. Other than short channel immunity, device 2
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reliability has always been a matter of concern. Interface charge at Si-SiO2 interface always creates reliability issues. These charges are developed at the interface during the fabrication process itself. Interface charges may be stress induced [6], process induced [7] or may be radiation induced [8]. Genesis of interface trap charges is basically because of Si dangling bonds. These bonds are present at the interface of silicon and silicon dioxide. Now as oxidation on silicon surface is carried out oxygen reacts with silicon and satisfies plethora of dangling bonds and count of dangling bonds is minimized, but still there is a possibility that post oxidation some dangling bonds are present which are the major cause of interface trap charges. Interface charges are present all over the forbidden energy gap and depending upon the Fermi level they can be either empty or filled. So as the gate voltage is applied, bands bends up or down depending upon the type of input applied at the gate and these interface states changes their occupancy and hence their electronic activity changes and correspondingly affect the device performance. Donor interface trap acts as positive interface trap charge when it’s empty and neutral charge when it is filled with electron. Acceptor interface charges acts as negative interface trap when filled with an electron and neutral charge when it is empty. In JLTFET, high value of electric field is desirable at the tunneling junction (between source and channel) for lowering the tunnel barrier. But lowering the tunneling barrier results increase in the electric and generation of interface trap charges. These interface traps present in Si-SiO2 interface results in degradation of electric field (BTBT rate is proportional to exp (-A/Ey)6 ) and hence tunnelling current and linearity and distortion performance of the device. Other than electric field negative bias temperature instability and positive bias temperature instability also leads to generation of interface trap charges [9].
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2. Device Structure, Simulation and Operation Figure 1 shows cross sectional view of JLTFET which was implemented using Silvaco ATLAS device simulation tool. Simulated structure has a doping concentration of 1×1019 cm−3 with channel length of 50 nm, source-drain extension of 50 nm and a spacer length of 5 nm between Control gate and P-gate. Thickness of gate dielectric (SiO2 ) used is taken as 0.8 nm. BTBT non local model has been used to account current for our device. Band gap narrowing (BGN) model is used as high doping concentration is applied source channel and drain region. Shockley read hall (SRH) model has also 3
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been incorporated to account leakage current in the device. Trap assisted tunnelling (TAT) model given by Schenk has also been considered in our simulation. Thickness of silicon wafer is taken to 10 nm hence we have restricted ourselves from applying Quantum confinement (QC) model which is generally considered when thickness is below 10 nm. Silicon wafer thickness is well within debye length (L D =(Si .VT /q.N)1/2 ), which is essential for applying charge plasma concept. Here Si represents dielectric constant of silicon whereas VT , q and N represents thermal voltage, electronic charge, and doping concentration in silicon layer respectively. The basic goal over here is to transform N+ - N+ - N+ to structure N+ - I - P+ without applying any doping to the structure and to operate it as JLTEFT. For introducing the hole plasma the work function of metal must follow the mentioned limitation (φm > χSi + Eg /2 - φf n ), hence we have used platinum whose work function is 5.93 as P-gate metal to introduce hole plasma. For introducing the electron plasma the work function of metal must follow the mentioned limitation (φm < χSi + Eg /2 - φf n ), hence we have used titanium whose work function is 4.3 as control gate to introduce electron plasma. Here Si and Eg are electron affinity and band gap of silicon. φf n indicates difference in Fermi level of intrinsic and doped silicon (in eV). In order to study reliability issues, effect of interface trap charges has been transformed into positive and negative localised charges. The value of interface trap charge density is taken as 1011 -1013 cm−2 eV −1 which has been taken after considering process, radiation and hot carrier damage effects which is studied in [10] [11]. For accounting minimum change, value of positive and negative charge density is taken as 1012 and −1012 cm−2 respectively. 3. Impact of ITC on device properties
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Figure 2(a) shows effect positive and negative trap charges on nonlocal band to band tunneling. It is lucidly visible from the figure that existence of negative (positive) interface trap charges suppresses (enhances) the nonlocal band to band tunneling in the device when compared with zero interface trap charge. The increment (decrement) in band to band tunneling is because of decrement (increment) in flat band voltage and this decrement (increment) in the flat band voltage results in decrement (increment) of band bending of valence and conduction band. Figure 2(b) shows the variation of electric field variation for positive, negative and zero interface trap charge. Electric field is enhanced (suppressed) for positive (negative) interface traps 4
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Figure 2: (a) Nonlocal band to band tunneling rate, and (b) Electric field near source to channel junction for positive, negative and zero interface trap charges
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Figure 3: (a) Transfer characteristics and (b) Transconductance (gm1 ) characteristics of JLTEFT for positive, negative and zero interface trap charges.
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because of higher (lower) band bending when compared with zero interface trap charges. Figure 3(a) shows the variation of transfer characteristics with different ITCs along gate bias. As mentioned in above statements, positive (negative) interface trap charges increases(decreases) band to band tunneling rate, and thus resulting an increase (decrease) in ON current with different ITCs. Variation in transconductance with gate voltage in presence of trap charges is shown in Figure 3(b). It is clearly visible from this figure that the presence of interface trap charges leads to a shift in transconductance characteristics. For positive (negative) interface trap charges, transconductance is higher (lower) as compared to zero interface trap charge.
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4. Performance metrics for linearity and intermodulation parameter
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Linearity and intermodulation distortion performance of device can be analysed by certain figure of merits which are VIP2, VIP3, IIP3, IMD3, 1-dB compression point, zero crossover point and higher order transconductance parameter (which includes gm2 , gm3 ) which are defined as: δ n Ids gm1 , gmn = (1) V IP 2 = 4 × gm2 δVgsn s gm1 (2) V IP 3 = 24 × gm3 2 gm1 IIP 3 = × (3) 3 gm3 × Rs 2 9 3 × (V IP 3) × (gm3 ) × Rs (4) IM D3 = 2
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where, Rs = 50 Ω is generally chosen for RF application. Second order transconductance (gm2 ) is defined as second derivative of drain current with respect to gate voltage. Third order transconductance (gm3 ) is defined as third derivative of drain current with respect to gate voltage. Higher order transconductance governs limit on distortion [12], hence both (gm2 and gm3 ) should be low in amplitude for achieving low distortion. Zero crossover point (ZCP) is that point in Vgs axis where the third order transconductance (gm3 ) is zero. ZCP decides DC bias point for device operation [13] and it should be close to threshold voltage (Vth ) for obtaining high gain. Also low value of zero crossover point ensures that we are getting high linearity at low value of Vgs . Getting high linearity and low voltage bias is good for portable RF application [14]. 1-dB compression point is defined as power level at which output power is decreased by 1-dB when compared with ideal linear characteristics; this point is considered as on-set on distortion [1] and also tells largest input signal that can be handled by the device without distortion [15]. Hence it is desirable to have high value of 1-dB compression point because it tells maximum power, amplifier can handle by supplying fixed gain and if the power increases after this point, gain starts falling. VIP2 is the extrapolated input voltage at which first order harmonic voltage term (ω 1 ) is equal to second order harmonic voltage term (ω 2 ). It is the extrapolated input voltage at 7
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Figure 4: (a) Second order transconductance (gm2 ) coefficient and (b) Third order transconductance (gm3 ) coefficient along gate bias for positive, negative and zero interface trap charges.
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Figure 5: (a) Zero crossover point and (b) Transconductance as a function of drain current of JLTFET for positive, negative and zero interface trap charges.
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which first order harmonic voltage term (ω 1 ) is equal to third order harmonic voltage term (ω 3 ). VIP3 is heavily dependent on gate voltage and drain current [16]. Peak in VIP3 should occur at lower value of gate voltage, shifting of peak of VIP3 towards higher value of Vgs indicates poor control of gate over the channel and high value of gate voltage is required to attain linearity. Third order intercept point [17] (IIP3) represents extrapolated input power at which third order intermodulation voltage term (2ω 2 - ω 1 ) is equal to first order harmonic voltage (ω 1 ). High value of third order intercept point is desirable for high linearity. Third order intermodulation distortion (IMD3) represents extrapolated intermodulation power at which first order harmonic power is equivalent to third order intermodulation harmonic power. Low 9
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5. Impact of ITC on linearity performance
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value of IMD3 is requires for low distortion [18]. Other than all these parameters transconductance versus drain current characteristics is also one of the parameter to judge the linearity. Wide and flat transconductance versus drain current curve ensures suppression of gm3 amplitude and high linearity of device [19]. Although flattening of curve will reduce the gm1 slightly.
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Linearity performance of devices in high frequency range can be estimated by experimental process which needs device to be fabricated. This process is time killing and extravagant. Hence linearity here is estimated using performance metrics. Linearity is one of the important parameter which ensures no intermodulation components at the output. For a system to be linear transconductance must be remain constant over the entire range of the input voltage, but transconductance of neither MOSFET nor TFET is independent of input voltage, which shows the nonlinear behavior of device. Transconductance and higher order transconductance put constraints on lower limits of distortion hence amplitude of higher order transconductance should be minimal. Figure 4(a) shows variation of gm2 with respect to gate voltage, at higher value of Vgs , gm2 is lesser (higher) for positive (negative) interface charge when compared with zero interface charge. Similarly in Figure 4(b) at higher value of Vgs , amplitude of gm3 is lesser (higher) for positive (negative) interface trap charge than zero interface charge. Also from Figure 4(b) it is clearly evident that interface charges leads to shifting of zero crossover point. For positive (negative) interface charges the zero cross over point is at lower (higher) value of Vgs than zero interface charge which is separately shown in Figure 5(a). Transconductance versus drain current characteristics is shown in Figure 5(b), flatter transconductance versus drain current curve indicate higher linearity, for positive (negative) interface charge the transconductance versus drain current is more (less) flatter than zero interface charge. For better linearity VIP2, VIP3 and IIP3 should be high, from Figure 6(a), 6(b) and 7(a) it is clearly evident that for positive (negative) interface trap charges peak value of VIP2, VIP3 and IIP3 increases (decreases) as compared to zero interface charge. Figure 7(b) shows the impact of interface trap charge on 1-dB compression point. Positive (negative) interface trap charge exhibits higher (lower) value of 1-dB compression point as compared to zero trap charge.
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Figure 6: (a) VIP2 and (b) VIP3 as function of gate to source voltage for positive, negative and zero interface trap charges.
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Figure 7: (a) IIP3 and (b) 1-dB compression point for positive, negative and zero interface trap charges.
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Figure 8: IMD3 as function of gate to source voltage for positive, negative and zero interface trap charges.
6. Impact of ITC on distortion performance
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Intermodulation distortion arises because of non-linearity present in the device. When a two tone input signal is applied to system exhibiting non linearity then output contains harmonics, higher order harmonics of input frequency and intermodulation components which are sum or difference of input frequencies. These harmonics and intermodulation components lead to distortion if these frequency components fall into band of interest at the output. Figure 8 shows impact of interface charge IMD3. Positive (negative) interface trap charge has lower (higher) value of IMD3 when compared to zero interface trap charge.
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7. Conclusion
Effect of localised interface trap charges has been studied on linearity, distortion and device parameters of JLTFET. Conclusions that can be taken out from these extensive simulations are the presence of interface trap charges leads to shift in flat band voltage, and thus band bending which in turn modifies tunneling barrier and hence transfer characteristics, linearity and distortion parameters. Simulations clearly indicate that presence of localised charges degrades the parameters in subthreshold, linear and saturation region. However in most of the amplifiers, FET operates in either saturation
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or linear region hence performance degradation of amplifier will be there because of presence of interface trap charges. Also the presence of localised charges leads to alteration in the bias point which is unfavorable of circuit reliability. Since these interface trap charges are present in the device, so study impact of these charges on device performance is necessary so that the device can optimised accordingly.
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[9] Y. Qiu, R. Wang, Q. Huang and R. Huang, “A comparative study on the impacts of interface traps on tunneling FET and MOSFET, ”IEEE Trans. Electron Devices, vol. 61, no. 5, pp. 1289-1291, May 2014. [10] T. Chiang, “A compact model for threshold voltage of surrounding gate MOSFETs with localized interface trapped charges,”IEEE Trans.Electron Devices, vol. 58, no. 2, pp. 567-571, Jan. 2011.
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[13] N. Gupta, R. Chaujar, “Optimization of high-k and gate metal workfunction for improved analog and intermodulation performance of Gate Stack (GS)-GEWE-SiNW MOSFET,”Superlattices and Microstructures., vol. 97, no. 12, pp. 630-641, Sep. 2016.
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[14] Yi Song, Chen Zhang, R. Dowdy, K. Chabak, P. K. Mohseni, Wonsik Choi, and Xiuling Li “III-V Junctionless Gate-All-Around Nanowire MOSFETs for High Linearity Low Power Applications,”IEEE Electron Device Letters, vol. 5, no. 3, pp. 324-326, Mar. 2014.
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[15] S.P.Kumar, A.Agrawal, R.Chaujar, R.S.Gupta, “Device linearity and intermodulation distortion comparision of dual material gate and conventional AlGaN/GaN high electron mobility transistor, ”Microelectronics Reliability,, vol. 3, no. 10, pp. 587-596, March. 2011. [16] Woerlee PH, Knitel MJ, Langevelde RL, Klaassen DBM, Tiemeijer LF, Scholten AJ, “RF-CMOS performance trends, ”IEEE Trans. Electron Dev., vol. 48, no. 8, pp. 1776-1781, Aug. 2001. [17] B. Razavi, ”RF Microelectronics., EnglewoodCliffs , NJ: Prentice-Hall 1998.
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Dear Editor, In this manuscript, the basic highlight are:
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Effect of interface trap charges on drain current, transconductance, and higher order transconductance and linearity and distortion parameter (VIP2, VIP3, IIP3, IMD3, zero crossover point, 1-dB compression point).
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High linearity and low distortion demands high value of VIP2, VIP3, IIP3, 1-dB compression point and low value of IMD3, zero crossover point and higher order transconductance parameter.