- Email: [email protected]
Improving the performance of a junctionless carbon nanotube field-effect transistor using a split-gate
Journal Pre-proofs Regular paper Improving the performance of a junctionless carbon nanotube field-effect transistor using a split-gate Khalil Tamersit PII: DOI: Reference:
S1434-8411(19)32513-0 https://doi.org/10.1016/j.aeue.2019.153035 AEUE 153035
To appear in:
International Journal of Electronics and Communications
Received Date: Revised Date: Accepted Date:
2 October 2019 31 October 2019 11 December 2019
Please cite this article as: K. Tamersit, Improving the performance of a junctionless carbon nanotube field-effect transistor using a split-gate, International Journal of Electronics and Communications (2019), doi: https:// doi.org/10.1016/j.aeue.2019.153035
This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
© 2019 Published by Elsevier GmbH.
Improving the performance of a junctionless carbon nanotube field-effect transistor using a split-gate
Khalil Tamersit Department of Electronics and Telecommunications, Université 8 Mai 1945 Guelma, Guelma 24000, Algeria. Email: [email protected], [email protected]. Tel.: +213777684646.
Abstract In this paper, a novel junctionless carbon nanotube field-effect transistor (JL-CNTFET) endowed with a split coaxial gate (SCG) is proposed through a rigorous self-consistent simulation. This latter is based on solving self-consistently the Schrödinger and Poisson equations using the non-equilibrium Green's function (NEGF) formalism and the finite difference method (FDM), respectively. It has been found that the suggested SCG JLCNTFET can exhibit significantly improved switching performance including the off-current, current ratio, intrinsic delay and power-delay product, due to the decreasing of band-to-band tunneling via the split-gate strategy. The obtained results indicate that the proposed SCG JLCNTFET can be considered as a promising device for the futuristic high-performance integrated circuits intended for low-power and high-speed applications.
Keywords: Junctionless (JL), carbon nanotube field-effect transistor (CNTFET), split-gate, quantum simulation, band-to-band tunneling (BTBT), switching.
1
1. Introduction Electronics based on carbon nanotube (CNT) has made considerable progress [1], among the most prominent is the construction of CNT-based field-effect transistor (FET) with 1-nm gate length [2] and the fabrication of modernistic microprocessor using complementary CNT transistors [3]. These substantial advancements give free rein to the paths toward beyond-silicon technologies [3]. For this reason, a huge number of pertinent theoretical and experimental works has been recorded in literature, while the carbon- and CNT-based electronics continues to increasingly attract the researchers' interest [1], [4]-[14]. In the last two decades, the coaxial-gate carbon nanotube field-effect transistor (CG CNTFET) has been extensively investigated due to its excellence in terms of electrical performance and scaling capability [15]-[17]. The CG CNTFET device can be further optimized in terms of electrical performance and fabrication process using the junctionless paradigm [18]-[20], which is considered as a simple and efficient solution to the intractability of realizing abrupt junction at nanoscale domain [21]-[24]. Several techniques have been proposed to improve the promising junctionless (JL) CG CNTFET, among other we cite approaches based on the strain [25] and work function engineering [19]. These techniques are promising for the near future, however, they are still difficult to achieve experimentally at the nanoscale regime with the existing techniques. Therefore, new experimentally feasible strategies and approaches should be proposed in order to boost the performance of junctionless CG JL-CNTFET. In this context, this paper proposes a new device called split coaxial-gate junctionless carbon nanotube field-effect transistor (SCG JL-CNTFET). The used simulation approach is based on solving the Schrödinger equation using the mode space non-equilibrium Green’s function (NEGF) formalism coupled self-consistently with the Poisson equation in the ballistic limit [26]. The NEGF simulation is considered as a sound basis to simulate and
2
evaluate the emerging nanoscale FET while considering all electrostatic and transport features including the quantum effects that significantly affect the nanodevice performance [27]. The suggested nanoscale CNT-based field-effect transistor is endowed with a split-gate in order to mitigate the band-to-band tunneling aiming an enhancement in terms of switching performance. The simulation investigation includes potential distribution, charge density, current spectrum, band diagrams, transfer characteristics, off-current, on-current, current ratio, switching speed, and power-delay product. It has been found that the proposed simple approach can lead to a significant enhancement in terms of switching behavior. The rest of this paper is organized as follow, Section 2 presents the structure of the novel JL-CNTFET. Section 3 summarizes the used simulation method. Section 4 presents and discusses the computational results. Section 5 concludes the present paper.
2. Device structure Fig. 1(a) shows the perspective of the conventional CG JL-CNTFET, which is endowed with a conventional coaxial-gate (CCG) to ensure a good electrostatic control [28], [29]. As shown, the carbon nanotube is surrounded by a coaxial layer of hafnium dioxide (HfO2) along the device with a dielectric constant OX. Note that the zigzag CNT is the type considered in the present study due to its appropriateness for FET applications in terms of gap energy (EG) [30]. Inspecting the Fig. 1(b) that shows the longitudinal cross-section of the conventional CG JL-CNTFET, we can see that the whole zigzag CNT is uniformly n-type doped with a concentration NCNT, while avoiding the junctions, which are difficult to achieve accurately at the nanoscale regime [20]-[25]. It is to note that LS(D), LG, dCNT, and tOX denote the length of source (drain) region, the gate length, the CNT diameter, and the oxide thickness, respectively. Fig. 1(c) shows the 3D view of the proposed SCG JL-CNTFET, which is endowed with split coaxial gate whereby the switching performance will be improved. As 3
VG
VS
VD
(a) Gate
r
tOX
HfO2 (ox=16) X
0
S
n-CNT
n-CNT
n-CNT
D
dCNT
Gate LG
LS
LD
(b) VG
VS
VD
(c) Gate
r
Gate tOX
HfO2 (ox=16) 0
X
S
n-CNT
n-CNT
Gate LG1 LS
n-CNT
D
dCNT
Gate LSP LG-EFF
LG2 LD
(d) Fig. 1. Three-dimensional structure (a) and the lengthwise cut view (b) of the conventional CG JL-CNTFET. 3D structure (c) and the longitudinal cross-section (d) of the proposed SCG JL-CNTFET.
shown in Fig. 1(c) and (d), the proposed SCG JL-CNTFET is similar to the conventional one except the gate type. The parameters LG1(2), LSP, and LG-EFF=LG1+LSP+LG2 denote the length of gate at source (drain) side, the spacing between the two gates, and the effective gate, respectively. Note that the effective gate length of the proposed device is taken to be equal to the gate length of the conventional JL-CNTFET for a fair comparison. 4
Parameter
Value
Z-CNT (n,0) EG dCNT NCNT LG LG-EFF LS(D) LG1(G2) LSP tOX OX VDS
(16,0) 0.667 eV 1.25 nm 2 nm-1 30 nm 30 nm 10 nm 12 nm 6 nm 2 nm 16 0.5 V
Table 1. Parameters of JL CNTFETs under investigation used through this work.
Table 1 shows the nominal physical and geometrical parameters of the JL CNTFETs under study. Note that in case one parameter is intentionally changed for sake of analysis, it is indicated in the text or figure.
3. Simulation approach In the simulation of nanoscale FETs, the non-equilibrium Green’s function (NEGF) formalism is known as a sound and accurate computational approach [26]. In the last decade, with the implication of emerging nanomaterials in FETs to extend the lifetime of Moore's law, the use of this simulation method is increasing remarkably due to its capability to consider the atomistic features, quantum effects, and complex geometries [31]. Basically, the simulation of nanoscale FET using the NEGF method is based primarily on the numerical calculation of the well known retarded Green’s function, which can be given in matrix form by [27]
G ( E ) [( E i 0 ) I H S D ]1
(1)
where I, 0+, E, H, ΣS and ΣD are the identity matrix, infinitesimal positive number, energy, Hamiltonian matrix, left (source) self-energy, and right (drain) self-energy, respectively. Note that the self-energies can be computed analytically as in [30]. As shown in Fig. 2(a), the CNT device is linked to the source and drain contacts via the self-energies. It is easily seen that the
5
Gate Source EFS
[ΣS]
Drain EFD
... [H]+[U]
[ΣD]
(a)
Initial Potential
NEGF
ΦCNT
ρCNT
Poisson Equation Convergence Ne, CNT, Gn(x), Tr(x), IDS, ...etc.
(b) Fig. 2. (a) The generic nanoscale transistor with a CNT channel connected to the two contacts. (b) The flowchart of the used simulation approach.
channel current is modulated by a gate that governs the device electrostatics. Note that the main NEGF quantities are also shown in the same figure. It is worth noting that the mode space (MS) fashion has been used to save the computational cost, which is the main drawback of the real space (RS) NEGF method [30-32]. In addition, the ballistic transport limit has been assumed while neglecting any scattering function. It is also to indicate that the used computational Hamiltonian considers only the couplings of pZ orbital of CNT material, and thus it is based on the atomistic nearest neighbor pZ-orbital tight-binding approximation [33]. Considering the MS approach, the Hamiltonian matrix for the qth mode is given by [30], [33] U1 b 2q H
b2 q 0 U2 t t U 3 b2 q 0 t U N 1 b2 q b2 q U N NN
(2)
6
where U, t, b2q= 2tcos(πq/n), and N are the CNT's on-site electrostatic potential, the C–C nearest neighbor binding parameter, coupling parameter, and the number of rings along the ZCNT (n,0) on which the on-site electrostatic potential is distributed, respectively [33]. Based on the computed retarded Green’s function and self-energies, the local-density-of-states (LDOS) can be computed by [30]
DS ( D ) GS ( D )G †
(3)
where S ( D ) i ( S ( D ) †S ( D ) ) is the energy level broadening. The CNT charge density is now calculable using the above NEGF quantities via following expression [25], [30] Q( x) (q ) dE sgnE E N ( x)
DS ( E , x) f (sgnE E N ( x)( E EFS ))
DD ( E , x) f (sgnE E N ( x)( E EFD ))
(4)
where q, sgn, EN, f(sgn[E−EN].(E−EFS(FD))) are the electron charge, sign function, charge neutrality level, and source (drain) Fermi function corresponding to the Fermi level EFS(FD). As shown in Fig. 2(b), the NEGF simulation is a self-consistent approach, where the NEGF solver feeds the Poisson solver and vice versa, until a convergence [34], [35]. The device electrostatics have been approximated accurately using the finite difference method while solving the Poisson equation for cylindrical transistor geometry given by [33]
2U ( x, r )
( x, r )
(5)
where U, , and are the electrostatic potential distribution, the charge density distribution, and the dielectric constant, respectively. It is worth noting that the developed FDM solver employs an uniform dense meshing equal to 1 Å [29], [36]. In summary, the numerical modeling is based on solving self-consistently the computational couple described above (MS
7
0.0 10-6
0.1
0.2
VDS [V]
0.3
0.4
0.5 30
Lines: Our simulations Experiment [37] NEGF [33]
IDS [A]
IDS [A]
20 10-8 VGS= 0.5 V 10
10-10 VGS=0.4 V 10-12
-0.4
-0.2
0.0
0.2
0.4
0.6
0 0.8
VGS [V]
Fig. 3. Comparison of the IDS-VGS transfer characteristic issued from the NEGF simulation with that measured experimentally [37] at VDS= 0.5 V (Bottom X left Y). Comparison of our simulated output characteristics with those reported in [33] (Top X right Y).
NEGF-Poisson) until a convergence [33]-[36]. After the achievement of this latter, the CNT channel can be calculated by [25], [30]
4e I dE T ( E )[ f ( E EFS ) f ( E EFD )]
(6)
where ħ is the Planck’s constant and Tr(E)=Trace[ΓSGΓDG†] is and the transmission coefficient. From computer programming point of view, the simulator's source code consists of approximately 2000 lines. It is to note that the simulations are performed on Matlab Software considering the room temperature (300 K). More details about the NEGF-based quantum simulation can be found in [26], [27].
4. Results and discussion In Fig. 3, we can see a comparison between the NEGF simulation and experimental data in terms of IDS-VGS transfer characteristics. It is easily seen that the numerical results are in reasonable agreement with the experimental data [37]. Note that the NEGF simulation approach has been found able to reproduce the experimental data for several FETs based on different channel materials such as graphene [38], carbon nanotube [39], graphene nanoribbon [40], transition metal dichalcogenide [41], etc. For this reason, the NEGF simulation is 8
e [eV] 5.25
-1.5 -1.2
r-direction [nm]
HfO2 3.25
-0.83
r
dCNT
0
2.00
x
-0.49 -0.16
HfO2
0.17
0.00 0
Source 10
0.50
Drain
Gate
x-direction [nm]
40
50
(a) r [nm] 2.625
0.625 0.000 0.625
2.625
(b) Fig. 4. Two-dimensional potential distribution of the conventional CG JL-CNTFET for (a) the longitudinal cross section and (b) for the cross section perpendicular to the x-direction at the middle of channel (x= 25 nm).
considered as an accurate, reliable, and flexible tool to simulate not only the nanoscale FETs, but also other ultrascaled devices [42]. Inspecting the same figure, we can see the excellent agreement between our simulated IDS-VDS output characteristics and those simulated in [33], considering the same simulation approach. After having checked the accuracy of the simulator, thereafter we present an exhaustive simulation and analysis of the proposed junctionless CNT-based FET. Fig. 4(a) shows the two-dimensional electrostatic potential of the conventional CG JLCNTFET drawn from the FDM nodes of the longitudinal cross section considering VGS=-0.5 V and VDS=0.5 V. We can clearly see the electrostatic gating aspect whereby the channel current is controlled in the conventional device. Fig. 4(b) shows the corresponding potential distribution at the level of the cross section perpendicular to the x-direction at the middle of device. It is important to note that the coaxial electrostatic gating is considered as a promising 9
e [eV]
5.25
-1.5
-1.2
r-direction [nm]
HfO2 3.25
-0.83
r
dCNT
0
2.00
x
-0.49 -0.16
HfO2
0.17
0.00
Source 0
10
Gate
Gate
Ungated
22
28
x-direction [nm]
0.50
Drain 40
50
(a) r [nm] 2.625
0.625 0.000 0.625
2.625
(b) Fig. 5. Two-dimensional potential distribution of the proposed SCG JL-CNTFET for (a) the longitudinal cross section and (b) for the cross section perpendicular to the x-direction at the middle of channel (x= 25 nm).
technique for futuristic high-performance CNTFET-based integrated circuits [43]-[45], due to its great ability in coaxially controlling the atomic-thick sheet of carbon. Fig. 5(a) shows the 2D potential distribution of the proposed device biased with VGS= 0.5 V and VDS=0.5 V. We can see that the potential aspect at the source and drain side are almost the same regarding the conventional CG JL-CNTFET. However, we can see the impact of the ungated region between the two coaxial gates on the electrostatics. As clearly seen, the whole electrostatic gating recorded in conventional case (Fig. 4(a)) is now divided by the ungated region (6 nm), while making the electrostatic impact of the CNT charge density more influential. Fig. 5(b) shows the potential distribution of the cross section perpendicular to the transport direction at the middle of the proposed SCG JL-CNTFET. By comparing the Fig. 4(b) and Fig. 5(b) we can clearly see the impact of the CNT charge density on the electrostatics of the ungated region. Thereafter, we will show and analyze the 10
102
VDS= 0.5 V CCG-JL CNTFET SCG-JL CNTFET LSP=3 nm LSP=4 nm LSP=5 nm LSP=6 nm
101
IDS [A]
100
LSP increasing
10-1
CNT(16,0); EG= 0.667 eV
10-2
OX=16; tOX=2 nm; 10-3
dCNT=1.25 nm; NCNT=2/nm LS(D)=10 nm; LG-EFF=30 nm.
10-4
-0.4
0.0
-0.2
0.2
0.4
VGS [V]
Fig. 6. The IDS-VGS transfer characteristics for conventional CG JL-CNTFET and the proposed SCG JLCNTFET.
improvements in electrical performance attributed to the employed ungated region that splits the conventional single gate into two coaxial gates. Fig. 6 shows the IDS-VGS properties of the conventional and proposed JL-CNTFETs. Note that the effective gate length with and without the consideration of ungated region is still equal to 30 nm. We can see that the increase in ungated distance, LSP, improves the minimal leakage current and decreases the band-to-band tunneling current. It is to indicate that the increase in LSP comes on the expense of LG1 and LG2, or equivalently, the increase in LSP decreases LG1 and LG2 equally while maintaining an effective gate length equal to 30 nm. Inspecting the same figure, it is clearly seen that the thermionic currents including the possible on-current are not influenced by the employed split gate design, and thus a significant improvement in terms of current ratio is expected. In order to have a deep view on the recorded results, we plot the electron density per unit energy and current spectrum versus x-position for both JL-CNTFETs under different gate bias conditions, as shown in Fig. 7. In Fig. 7, the top (bottom) line is the conduction (valence) edge band, and the region between the two horizontal white lines denotes the gap energy of the considered zigzag CNT. Inspecting the two contact regions in the figures of electron density spectrum, we can see that the electrons are filled up to the concerned Fermi levels, where the interference pattern are 11
(a)
(c)
(b)
(d)
Fig. 7. Electron density spectrum (dN/dE) versus x-position for (a) the conventional CG JL-CNTFET and (c) the proposed SCG JL-CNTFET. Energy-position-resolved current spectrum (Log10 I(x,E)) for (b) the conventional CG JL-CNTFET and (d) the proposed SCG JL-CNTFET. The basing condition is: VDS= 0.5 V and VGS=-0.5 V.
also apparent. Fig. 7(a) shows that the conventional CG JL-CNTFET exhibits a band-to-band tunneling (BTBT) from conduction band of the source to the conduction band of the drain through the valence band underneath the gate. Note that the ambipolar property and the relatively high minimum leakage current recorded in the transfer characteristic of the conventional CG JL-CNTFET (Fig. 6) is mainly attributed to this BTBT mechanism, which is known with its detrimental effects on subthreshold characteristics [19], [46]-[48]. Fig. 7(b) shows clearly the corresponding current spectrum in the conventional device. We can easily see that the BTBT current is the dominant component due to its high intensity while reflecting the recorded ambipolar property and the high leakage current. Considering the same biasing conditions (VGS=-0.5 V) for the proposed SCG JLCNTFET, we can see in Fig. 7(c) that the proposed SCG JL-CNTFET alleviates the BTBT mechanism via the drop in potential (indicated by dashed circle) induced by the ungated region. As shown in Fig. 7(d), the BTBT current is decreased in comparison to that of conventional device due to the recorded curvature that opposes the BTBT components. This 12
explains the improvement in terms of leakage current and ambipolar behavior recorded in Fig. 6 using the split gate technique. Note that the decrease in LSP alleviates the recorded drop in potential that opposes the BTBT, and thus the BTBT increases. In this context, we emphasize that the BTBT can be further mitigated using the graded doping technique while dilating the left and right BTBT widths [49]. Inspection of Fig. 7(d) also reveals a kind of direct sourceto-drain tunneling (DSDT), which is attributed to the short length of the two coaxial gates in the proposed design while supporting the appearance of DSDT current. It is worth noting that the DSDT mechanism becomes more influential for ultra-scaled devices [48]. For this reason, the minimum (maximum) gate length (ungated spacing) considered in split gate design is chosen equal to 12 nm (6 nm) in order to avoid the detrimental effects of DSDT increasing. In the Fig. 8, the on-currents and off-currents are extracted from the Fig. 6 considering a power supply voltage (VDD) equal to 0.5 V. Note that each (ION,IOFF) point corresponds to 102 1
10
CCG-JL CNTFET SCG-JL CNTFET
LSP= 6 nm
IOFF [A]
100 10-1 10-2 10-3 10-4 10
VDD=0.5 V 20
(a) 30
40
50
60
70
80
ION [A]
105 CCG-JL CNTFET SCG-JL CNTFET LSP= 6 nm
104
ION/IOFF
103 102 101 100 10-1 10
VDD=0.5 V 20
(b) 30
40
50
60
70
80
ION [A]
Fig. 8. (a) IOFF versus ION and (b) ION/IOFF current ratio versus ION for both JL-CNTFETs.
13
(VGS-ON, VGS-OFF=VGS-ON-VDD), and thus the curves are within reach by sweeping a range of VGS. This technique, which is extensively used in literature [37], [49]-[51], allows to give a clearer picture concerning the off- and on-currents on one hand, and to reveal the maximum reachable current ratios on the other hand [49]-[51]. Fig. 8(a) shows the off-currents versus the on-currents for the two CNT-based devices under study. As shown, the proposed SCG JLCNTFET can provide lower off-current in comparison to its conventional counterpart, while the two devices share the same order of magnitude in terms of the on-currents. Therefore, higher current ratios can be obtained using the proposed design. Indeed, Fig. 8(b) shows that the maximum reachable ION-IOFF ratio of the proposed split gate JL-CNTFET is higher by about one order of magnitude than that of the conventional design. The intrinsic delay () is an important parameter that indicates how fast the JL-CNTFET can switch [52]. It can be numerically simulated using the following relation [51] =(QON-QOFF)/ION
(7)
where QON (QOFF) is the total charge in the whole CNT channel including the source and drain extension at on-state (off-state). Fig. 9(a) shows the intrinsic delay as a function of on-current for the proposed and conventional JL-CNTFET considering a power supply voltage equal to 0.5 V. The curves are plotted with a manner similar to that used to draw Fig. 8, where a VDD window is used to extract QOFF, QON and ION required for intrinsic delay estimation (12). Note that after each extraction, the window is shifted to extract the other switching cases while plotting the curve. It is easily seen that the proposed design exhibits shorter intrinsic delay regarding the conventional device over the shared range of on-currents. The recorded improvement in terms of intrinsic delay indicates that the suggested design can be a valuable option for high-speed applications. 14
1200 CCG-JL CNTFET SCG-JL CNTFET LSP= 6 nm
1000
[fs]
800 600 400
VDD=0.5 V
200 0
(a) 10
20
30
40
ION [A]
11.24 CCG-JL CNTFET SCG-JL CNTFET LSP= 6 nm
PDP [eV]
9.99
Maximum ION/IOFF
8.74
Maximum ION/IOFF
7.49
6.24
VDD=0.5 V
(b) 10
20
30
40
ION [A]
Fig. 9. (a) Intrinsic delay versus ION current of both JL-CNTFETs. (b) PDP versus ION for the conventional and proposed JL-CNTFET.
The power-delay product (PDP) is also an important switching parameter that indicates the energy required for a transition from on-state to off-state. The PDP can be numerically computed as [51] PDP=(QON-QOFF)VDD
(8)
Fig. 9(b) shows the power-delay product in function of on-current for the proposed design and its conventional counterpart considering VDD=0.5 V. It is clearly seen that the JLCNTFET endowed with split gate provides lower power-delay product than the conventional device over the shared range of on-currents. Inspecting the same figure, we can also see that the PDP that corresponds the maximum reachable current ratio of the proposed design is lower than that of the conventional design, indicating that the suggested design can be considered as a promising candidate for futuristic low-power applications. In addition to the 15
performance enhancement, the proposed SCG-based strategy can be considered as a promising alternative to the similar approaches based on strain, dielectric, doping, and work function engineering, which are still difficult to achieve accurately at nanoscale domain [914]. Note that the synergy of the proposed strategy with the aforementioned similar techniques including the dielectric engineering can further boost the performance of JL CNTFETs.
5. Conclusion In this paper, the switching performance of the JL-CNTFET has been improved using a new strategy based on the employment of a split surrounding gate. This latter has been used in order to alleviate the band-to-band tunneling mechanism that degrades the switching characteristics. The simulation results have revealed that the proposed SCG JL-CNTFET design is efficient in improving the ambipolar behavior, minimum leakage current, current ratio, intrinsic delay, and power-delay product. The findings obtained in this study empower the proposed SCG JL-CNTFET to be a favorable device for modern digital circuits.
16
References [1] J. Si, L. Xu, M. Zhu, Z. Zhang, and L. Peng, “Advances in High‐Performance Carbon‐Nanotube Thin‐Film Electronics,” Advanced Electronic Materials, vol. 5, no. 8, p. 1900122, Jun. 2019. [2] S. B. Desai, S. R. Madhvapathy, A. B. Sachid, J. P. Llinas, Q. Wang, G. H. Ahn, G. Pitner, M. J. Kim, J. Bokor, C. Hu, H.-S. P. Wong, and A. Javey, “MoS2 transistors with 1-nanometer gate lengths,” Science, vol. 354, no. 6308, pp. 99–102, Oct. 2016. [3] G. Hills, C. Lau, A. Wright, S. Fuller, M. D. Bishop, T. Srimani, P. Kanhaiya, R. Ho, A. Amer, Y. Stein, D. Murphy, Arvind, A. Chandrakasan, and M. M. Shulaker, “Modern microprocessor built from complementary carbon nanotube transistors,” Nature, vol. 572, no. 7771, pp. 595–602, Aug. 2019. [4] P. Avouris, J. Appenzeller, R. Martel, and S. J. Wind, “Carbon nanotube electronics,” Proceedings of the IEEE, vol. 9, no. 11, pp. 1772–1784, Nov. 2003. [5] F. Salimian and D. Dideban, “Comparative study of nanoribbon field effect transistors based on silicene and graphene,” Materials Science in Semiconductor Processing, vol. 93, pp. 92–98, Apr. 2019. [6] V. Khademhosseini, D. Dideban, M. Ahmadi, R. Ismail, and H. Heidari, “Single Electron Transistor Scheme Based on Multiple Quantum Dot Islands: Carbon Nanotube and Fullerene,” ECS Journal of Solid State Science and Technology, vol. 7, no. 10, pp. M145–M152, 2018. [7] V. KhademHosseini, D. Dideban, M. T. Ahmadi, and R. Ismail, “An analytical approach to model capacitance and resistance of capped carbon nanotube single electron transistor,” AEU - International Journal of Electronics and Communications, vol. 90, pp. 97–102, Jun. 2018. [8] A. H. Bayani, D. Dideban, M. Akbarzadeh, and N. Moezi, “Benchmarking Performance of a Gate-AllAround Germanium Nanotube Field Effect Transistor (GAA-GeNTFET) against GAA-CNTFET,” ECS Journal of Solid State Science and Technology, vol. 6, no. 4, pp. M24–M28, 2017. [9] A. Naderi and S. A. Ahmadmiri, “Attributes in the Performance and Design Considerations of Asymmetric Drain and Source Regions in Carbon Nanotube Field Effect Transistors: Quantum Simulation Study,” ECS Journal of Solid State Science and Technology, vol. 5, no. 7, pp. M63–M68, 2016. [10] B. A. Tahne and A. Naderi, “SLD-MOSCNT: A new MOSCNT with step–linear doping profile in the source and drain regions,” International Journal of Modern Physics B, vol. 31, no. 01, p. 1650242, Jan. 2017. [11] A. Naderi and M. Ghodrati, “Improving band-to-band tunneling in a tunneling carbon nanotube field effect transistor by multi-level development of impurities in the drain region,” The European Physical Journal Plus, vol. 132, no. 12, Dec. 2017. [12] A. Naderi and P. Keshavarzi, “The effects of source/drain and gate overlap on the performance of carbon nanotube field effect transistors,” Superlattices and Microstructures, vol. 52, no. 5, pp. 962–976, Nov. 2012.
17
[13] A. Naderi and P. Keshavarzi, “Novel carbon nanotube field effect transistor with graded double halo channel,” Superlattices and Microstructures, vol. 51, no. 5, pp. 668–679, May 2012. [14] A. Naderi, S. M. Noorbakhsh, and H. Elahipanah, “Temperature Dependence of Electrical Characteristics of Carbon Nanotube Field-Effect Transistors: A Quantum Simulation Study,” Journal of Nanomaterials, vol. 2012, pp. 1–7, 2012. [15] A. D. Franklin, “The road to carbon nanotube transistors,” Nature, vol. 498, no. 7455, pp. 443-444, Jun.2013. [16] A. D. Franklin et al., “Carbon nanotube complementary wrap-gate transistors,” Nano Lett., vol. 13, no. 6, 2013. [17] A. Naderi and B. A. Tahne, “Review—Methods in Improving the Performance of Carbon Nanotube Field Effect Transistors,” ECS Journal of Solid State Science and Technology, vol. 5, no. 12, pp. M131–M140, 2016. [18] L. Ansari et al., “First Principle-Based Analysis of Single-Walled Carbon Nanotube and Silicon Nanowire Junctionless Transistors,” IEEE Transactions on Nanotechnology, vol. 12, no. 6, pp. 1075–1081, 2013. [19] K. Tamersit, “Quantum simulation of a junctionless carbon nanotube field-effect transistor with binary metal alloy gate electrode,” Superlattices and Microstructures, vol. 128, pp. 252–259, Apr. 2019. [20] M. A. Barik, R. Deka, and J. C. Dutta, “Carbon nanotube-based dual-gated junctionless field-effect transistor for acetylcholine detection,” IEEE Sensors J., vol. 16, no. 2, pp. 280–286, Jan. 2016. [21] C.-W. Lee et al., “Junctionless multigate field-effect transistor,” Appl. Phys. Lett., vol. 94, no. 5, 2009. [22] J.-P. Colinge et al., “Nanowire transistors without junctions,” Nature Nanotech., vol. 5, no. 3, p. 225, 2010. [23] C.-W. Lee et al., “Performance estimation of junctionless multigate transistors,” Solid-State Electronics, vol. 54, no. 2, pp. 97–103, Feb. 2010. [24] J. P. Colinge et al., “Junctionless Nanowire Transistor (JNT): Properties and design guidelines,” Solid-State Electronics, vol. 65–66, pp. 33–37, Nov. 2011. [25] P. Pourian, R. Yousefi, and S. S. Ghoreishi, “Effect of uniaxial strain on electrical properties of CNT-based junctionless field-effect transistor: Numerical study,” Superlattices Microstruct., vol. 93, pp. 92–100, May 2016. [26] M. P. Anantram et al., “Modeling of Nanoscale Devices,” Proceedings of the IEEE, vol. 96, no. 9, 2008. [27] S. Datta, “Nanoscale device modeling: The Green’s function method,” Superlattices Microstruct., vol. 28, no. 4, pp. 253–278, Oct. 2000. [28] J. Guo, S. Datta, and M. Lundstrom, “A Numerical Study of Scaling Issues for Schottky-Barrier Carbon Nanotube Transistors,” IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 172–177, 2004.
18
[29] K. Tamersit and F. Djeffal, “Carbon Nanotube Field-Effect Transistor With Vacuum Gate Dielectric for Label-Free Detection of DNA Molecules: A Computational Investigation,” IEEE Sensors Journal, vol. 19, no. 20, pp. 9263–9270, Oct. 2019. [30] J. Guo, S. Datta, M. Lundstrom, and M. P. Anantam, “Toward Multiscale Modeling of Carbon Nanotube Transistors,” Int. J. Multiscale Comput. Eng., vol. 2, no. 2, pp. 257–276, 2004. [31] K. Tamersit and F. Djeffal, “A computationally efficient hybrid approach based on artificial neural networks and the wavelet transform for quantum simulations of graphene nanoribbon FETs,” Journal of Computational Electronics, vol. 18, no. 3, pp. 813–825, May 2019. [32] N. B. Bousari, M. K. Anvarifard, and S. Haji-Nasiri, “Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering,” AEU - International Journal of Electronics and Communications, vol. 108, pp. 226–234, Aug. 2019. [33] S. O. Koswatta et al., “Nonequilibrium Green’s function treatment of phonon scattering in carbon-nanotube transistors,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2339–2351, Sep. 2007. [34] K. Tamersit and F. Djeffal, “Double-Gate Graphene Nanoribbon Field-Effect Transistor for DNA and Gas Sensing Applications: Simulation Study and Sensitivity Analysis,” IEEE Sensors Journal, vol. 16, no. 11, pp. 4180–4191, Jun. 2016. [35] K. Tamersit, “Performance Assessment of a New Radiation Dosimeter Based on Carbon Nanotube FieldEffect Transistor: A Quantum Simulation Study,” IEEE Sensors Journal, vol. 19, no. 9, pp. 3314–3321, May 2019. [36] K. Tamersit and F. Djeffal, “A novel graphene field-effect transistor for radiation sensing application with improved sensitivity: Proposal and analysis,” Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 901, pp. 32–39, Sep. 2018. [37] A. Javey et al., “High performance n-type carbon nanotube field-effect transistors with chemically doped contacts,” Nano Lett., vol. 5, no. 2, pp. 345–348, Feb. 2005. [38] D. Berdebes et al., “Substrate gating of contact resistance in graphene transistors,” IEEE Trans. Electron Devices, vol. 58, no. 11, pp. 3925–3932, Nov. 2011. [39] J. Appenzeller et al., “Band-to-band tunneling in carbon nanotube field-effect transistors,” Physical review letters, vol. 93, no. 19, pp. 196805-1–196805-4, Nov. 2004. [40] J. Guo, “Modeling of graphene nanoribbon devices,” Nanoscale, vol. 4, no. 18, pp. 5538–5548, Sep. 2012. [41] B. Wei and C. Lu, “Transition metal dichalcogenide MoS2 field-effect transistors for analog circuits: A simulation study,” AEU - International Journal of Electronics and Communications, vol. 88, pp. 110–119, May 2018.
19
[42] S. Bruzzone et al., “An open-source multiscale framework for the simulation of nanoscale devices,” IEEE Trans. Electron Devices, vol. 61, no. 1, pp. 48–53, Jan. 2014. [43] M. Khaleqi Qaleh Jooq, A. Mir, S. Mirzakuchaki, and A. Farmani, “A robust and energy-efficient nearthreshold SRAM cell utilizing ballistic carbon nanotube wrap-gate transistors,” AEU - International Journal of Electronics and Communications, vol. 110, p. 152874, Oct. 2019. [44] E. Shahrom and S. A. Hosseini, “A new low power multiplexer based ternary multiplier using CNTFETs,” AEU - International Journal of Electronics and Communications, vol. 93, pp. 191–207, Sep. 2018. [45] A. Singh, M. Khosla, and B. Raj, “Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM,” AEU - International Journal of Electronics and Communications, vol. 80, pp. 67–72, Oct. 2017. [46] K. Tamersit and F. Djeffal, “Boosting the performance of a nanoscale graphene nanoribbon field-effect transistor using graded gate engineering,” Journal of Computational Electronics, vol. 17, no. 3, pp. 1276–1284, Jun. 2018. [47] G. Fiori and G. Iannaccone, “Simulation of Graphene Nanoribbon Field-Effect Transistors,” IEEE Electron Device Letters, vol. 28, no. 8, pp. 760–762, Aug. 2007. [48] J. Luo et al., “Compact model for carbon nanotube field-effect transistors including nonidealities and calibrated with experimental data down to 9-nm gate length,” IEEE Trans. Electron Devices, vol. 60, no. 6, pp. 1834–1843, Jun. 2013. [49] R. Yousefi et al., “Numerical Study of Lightly Doped Drain and Source Carbon Nanotube Field Effect Transistors,” IEEE Transactions on Electron Devices, vol. 57, no. 4, pp. 765–771, Apr. 2010. [50] Y. Yoon and Jing Guo, “Analysis of Strain Effects in Ballistic Carbon Nanotube FETs,” IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1280–1287, Jun. 2007. [51] S. O. Koswatta et al., “Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs,” IEEE Transactions on Electron Devices, vol. 56, no. 3, pp. 456–465, Mar. 2009. [52] Y. Ouyang et al., “Scaling Behaviors of Graphene Nanoribbon FETs: A Three-Dimensional Quantum Simulation Study,” IEEE Transactions on Electron Devices, vol. 54, no. 9, pp. 2223–2231, Sep. 2007.
20
Author declares that there is no conflicts of interest.
21
S1434-8411(19)32513-0 https://doi.org/10.1016/j.aeue.2019.153035 AEUE 153035
To appear in:
International Journal of Electronics and Communications
Received Date: Revised Date: Accepted Date:
2 October 2019 31 October 2019 11 December 2019
Please cite this article as: K. Tamersit, Improving the performance of a junctionless carbon nanotube field-effect transistor using a split-gate, International Journal of Electronics and Communications (2019), doi: https:// doi.org/10.1016/j.aeue.2019.153035
This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
© 2019 Published by Elsevier GmbH.
Improving the performance of a junctionless carbon nanotube field-effect transistor using a split-gate
Khalil Tamersit Department of Electronics and Telecommunications, Université 8 Mai 1945 Guelma, Guelma 24000, Algeria. Email: [email protected], [email protected]. Tel.: +213777684646.
Abstract In this paper, a novel junctionless carbon nanotube field-effect transistor (JL-CNTFET) endowed with a split coaxial gate (SCG) is proposed through a rigorous self-consistent simulation. This latter is based on solving self-consistently the Schrödinger and Poisson equations using the non-equilibrium Green's function (NEGF) formalism and the finite difference method (FDM), respectively. It has been found that the suggested SCG JLCNTFET can exhibit significantly improved switching performance including the off-current, current ratio, intrinsic delay and power-delay product, due to the decreasing of band-to-band tunneling via the split-gate strategy. The obtained results indicate that the proposed SCG JLCNTFET can be considered as a promising device for the futuristic high-performance integrated circuits intended for low-power and high-speed applications.
Keywords: Junctionless (JL), carbon nanotube field-effect transistor (CNTFET), split-gate, quantum simulation, band-to-band tunneling (BTBT), switching.
1
1. Introduction Electronics based on carbon nanotube (CNT) has made considerable progress [1], among the most prominent is the construction of CNT-based field-effect transistor (FET) with 1-nm gate length [2] and the fabrication of modernistic microprocessor using complementary CNT transistors [3]. These substantial advancements give free rein to the paths toward beyond-silicon technologies [3]. For this reason, a huge number of pertinent theoretical and experimental works has been recorded in literature, while the carbon- and CNT-based electronics continues to increasingly attract the researchers' interest [1], [4]-[14]. In the last two decades, the coaxial-gate carbon nanotube field-effect transistor (CG CNTFET) has been extensively investigated due to its excellence in terms of electrical performance and scaling capability [15]-[17]. The CG CNTFET device can be further optimized in terms of electrical performance and fabrication process using the junctionless paradigm [18]-[20], which is considered as a simple and efficient solution to the intractability of realizing abrupt junction at nanoscale domain [21]-[24]. Several techniques have been proposed to improve the promising junctionless (JL) CG CNTFET, among other we cite approaches based on the strain [25] and work function engineering [19]. These techniques are promising for the near future, however, they are still difficult to achieve experimentally at the nanoscale regime with the existing techniques. Therefore, new experimentally feasible strategies and approaches should be proposed in order to boost the performance of junctionless CG JL-CNTFET. In this context, this paper proposes a new device called split coaxial-gate junctionless carbon nanotube field-effect transistor (SCG JL-CNTFET). The used simulation approach is based on solving the Schrödinger equation using the mode space non-equilibrium Green’s function (NEGF) formalism coupled self-consistently with the Poisson equation in the ballistic limit [26]. The NEGF simulation is considered as a sound basis to simulate and
2
evaluate the emerging nanoscale FET while considering all electrostatic and transport features including the quantum effects that significantly affect the nanodevice performance [27]. The suggested nanoscale CNT-based field-effect transistor is endowed with a split-gate in order to mitigate the band-to-band tunneling aiming an enhancement in terms of switching performance. The simulation investigation includes potential distribution, charge density, current spectrum, band diagrams, transfer characteristics, off-current, on-current, current ratio, switching speed, and power-delay product. It has been found that the proposed simple approach can lead to a significant enhancement in terms of switching behavior. The rest of this paper is organized as follow, Section 2 presents the structure of the novel JL-CNTFET. Section 3 summarizes the used simulation method. Section 4 presents and discusses the computational results. Section 5 concludes the present paper.
2. Device structure Fig. 1(a) shows the perspective of the conventional CG JL-CNTFET, which is endowed with a conventional coaxial-gate (CCG) to ensure a good electrostatic control [28], [29]. As shown, the carbon nanotube is surrounded by a coaxial layer of hafnium dioxide (HfO2) along the device with a dielectric constant OX. Note that the zigzag CNT is the type considered in the present study due to its appropriateness for FET applications in terms of gap energy (EG) [30]. Inspecting the Fig. 1(b) that shows the longitudinal cross-section of the conventional CG JL-CNTFET, we can see that the whole zigzag CNT is uniformly n-type doped with a concentration NCNT, while avoiding the junctions, which are difficult to achieve accurately at the nanoscale regime [20]-[25]. It is to note that LS(D), LG, dCNT, and tOX denote the length of source (drain) region, the gate length, the CNT diameter, and the oxide thickness, respectively. Fig. 1(c) shows the 3D view of the proposed SCG JL-CNTFET, which is endowed with split coaxial gate whereby the switching performance will be improved. As 3
VG
VS
VD
(a) Gate
r
tOX
HfO2 (ox=16) X
0
S
n-CNT
n-CNT
n-CNT
D
dCNT
Gate LG
LS
LD
(b) VG
VS
VD
(c) Gate
r
Gate tOX
HfO2 (ox=16) 0
X
S
n-CNT
n-CNT
Gate LG1 LS
n-CNT
D
dCNT
Gate LSP LG-EFF
LG2 LD
(d) Fig. 1. Three-dimensional structure (a) and the lengthwise cut view (b) of the conventional CG JL-CNTFET. 3D structure (c) and the longitudinal cross-section (d) of the proposed SCG JL-CNTFET.
shown in Fig. 1(c) and (d), the proposed SCG JL-CNTFET is similar to the conventional one except the gate type. The parameters LG1(2), LSP, and LG-EFF=LG1+LSP+LG2 denote the length of gate at source (drain) side, the spacing between the two gates, and the effective gate, respectively. Note that the effective gate length of the proposed device is taken to be equal to the gate length of the conventional JL-CNTFET for a fair comparison. 4
Parameter
Value
Z-CNT (n,0) EG dCNT NCNT LG LG-EFF LS(D) LG1(G2) LSP tOX OX VDS
(16,0) 0.667 eV 1.25 nm 2 nm-1 30 nm 30 nm 10 nm 12 nm 6 nm 2 nm 16 0.5 V
Table 1. Parameters of JL CNTFETs under investigation used through this work.
Table 1 shows the nominal physical and geometrical parameters of the JL CNTFETs under study. Note that in case one parameter is intentionally changed for sake of analysis, it is indicated in the text or figure.
3. Simulation approach In the simulation of nanoscale FETs, the non-equilibrium Green’s function (NEGF) formalism is known as a sound and accurate computational approach [26]. In the last decade, with the implication of emerging nanomaterials in FETs to extend the lifetime of Moore's law, the use of this simulation method is increasing remarkably due to its capability to consider the atomistic features, quantum effects, and complex geometries [31]. Basically, the simulation of nanoscale FET using the NEGF method is based primarily on the numerical calculation of the well known retarded Green’s function, which can be given in matrix form by [27]
G ( E ) [( E i 0 ) I H S D ]1
(1)
where I, 0+, E, H, ΣS and ΣD are the identity matrix, infinitesimal positive number, energy, Hamiltonian matrix, left (source) self-energy, and right (drain) self-energy, respectively. Note that the self-energies can be computed analytically as in [30]. As shown in Fig. 2(a), the CNT device is linked to the source and drain contacts via the self-energies. It is easily seen that the
5
Gate Source EFS
[ΣS]
Drain EFD
... [H]+[U]
[ΣD]
(a)
Initial Potential
NEGF
ΦCNT
ρCNT
Poisson Equation Convergence Ne, CNT, Gn(x), Tr(x), IDS, ...etc.
(b) Fig. 2. (a) The generic nanoscale transistor with a CNT channel connected to the two contacts. (b) The flowchart of the used simulation approach.
channel current is modulated by a gate that governs the device electrostatics. Note that the main NEGF quantities are also shown in the same figure. It is worth noting that the mode space (MS) fashion has been used to save the computational cost, which is the main drawback of the real space (RS) NEGF method [30-32]. In addition, the ballistic transport limit has been assumed while neglecting any scattering function. It is also to indicate that the used computational Hamiltonian considers only the couplings of pZ orbital of CNT material, and thus it is based on the atomistic nearest neighbor pZ-orbital tight-binding approximation [33]. Considering the MS approach, the Hamiltonian matrix for the qth mode is given by [30], [33] U1 b 2q H
b2 q 0 U2 t t U 3 b2 q 0 t U N 1 b2 q b2 q U N NN
(2)
6
where U, t, b2q= 2tcos(πq/n), and N are the CNT's on-site electrostatic potential, the C–C nearest neighbor binding parameter, coupling parameter, and the number of rings along the ZCNT (n,0) on which the on-site electrostatic potential is distributed, respectively [33]. Based on the computed retarded Green’s function and self-energies, the local-density-of-states (LDOS) can be computed by [30]
DS ( D ) GS ( D )G †
(3)
where S ( D ) i ( S ( D ) †S ( D ) ) is the energy level broadening. The CNT charge density is now calculable using the above NEGF quantities via following expression [25], [30] Q( x) (q ) dE sgnE E N ( x)
DS ( E , x) f (sgnE E N ( x)( E EFS ))
DD ( E , x) f (sgnE E N ( x)( E EFD ))
(4)
where q, sgn, EN, f(sgn[E−EN].(E−EFS(FD))) are the electron charge, sign function, charge neutrality level, and source (drain) Fermi function corresponding to the Fermi level EFS(FD). As shown in Fig. 2(b), the NEGF simulation is a self-consistent approach, where the NEGF solver feeds the Poisson solver and vice versa, until a convergence [34], [35]. The device electrostatics have been approximated accurately using the finite difference method while solving the Poisson equation for cylindrical transistor geometry given by [33]
2U ( x, r )
( x, r )
(5)
where U, , and are the electrostatic potential distribution, the charge density distribution, and the dielectric constant, respectively. It is worth noting that the developed FDM solver employs an uniform dense meshing equal to 1 Å [29], [36]. In summary, the numerical modeling is based on solving self-consistently the computational couple described above (MS
7
0.0 10-6
0.1
0.2
VDS [V]
0.3
0.4
0.5 30
Lines: Our simulations Experiment [37] NEGF [33]
IDS [A]
IDS [A]
20 10-8 VGS= 0.5 V 10
10-10 VGS=0.4 V 10-12
-0.4
-0.2
0.0
0.2
0.4
0.6
0 0.8
VGS [V]
Fig. 3. Comparison of the IDS-VGS transfer characteristic issued from the NEGF simulation with that measured experimentally [37] at VDS= 0.5 V (Bottom X left Y). Comparison of our simulated output characteristics with those reported in [33] (Top X right Y).
NEGF-Poisson) until a convergence [33]-[36]. After the achievement of this latter, the CNT channel can be calculated by [25], [30]
4e I dE T ( E )[ f ( E EFS ) f ( E EFD )]
(6)
where ħ is the Planck’s constant and Tr(E)=Trace[ΓSGΓDG†] is and the transmission coefficient. From computer programming point of view, the simulator's source code consists of approximately 2000 lines. It is to note that the simulations are performed on Matlab Software considering the room temperature (300 K). More details about the NEGF-based quantum simulation can be found in [26], [27].
4. Results and discussion In Fig. 3, we can see a comparison between the NEGF simulation and experimental data in terms of IDS-VGS transfer characteristics. It is easily seen that the numerical results are in reasonable agreement with the experimental data [37]. Note that the NEGF simulation approach has been found able to reproduce the experimental data for several FETs based on different channel materials such as graphene [38], carbon nanotube [39], graphene nanoribbon [40], transition metal dichalcogenide [41], etc. For this reason, the NEGF simulation is 8
e [eV] 5.25
-1.5 -1.2
r-direction [nm]
HfO2 3.25
-0.83
r
dCNT
0
2.00
x
-0.49 -0.16
HfO2
0.17
0.00 0
Source 10
0.50
Drain
Gate
x-direction [nm]
40
50
(a) r [nm] 2.625
0.625 0.000 0.625
2.625
(b) Fig. 4. Two-dimensional potential distribution of the conventional CG JL-CNTFET for (a) the longitudinal cross section and (b) for the cross section perpendicular to the x-direction at the middle of channel (x= 25 nm).
considered as an accurate, reliable, and flexible tool to simulate not only the nanoscale FETs, but also other ultrascaled devices [42]. Inspecting the same figure, we can see the excellent agreement between our simulated IDS-VDS output characteristics and those simulated in [33], considering the same simulation approach. After having checked the accuracy of the simulator, thereafter we present an exhaustive simulation and analysis of the proposed junctionless CNT-based FET. Fig. 4(a) shows the two-dimensional electrostatic potential of the conventional CG JLCNTFET drawn from the FDM nodes of the longitudinal cross section considering VGS=-0.5 V and VDS=0.5 V. We can clearly see the electrostatic gating aspect whereby the channel current is controlled in the conventional device. Fig. 4(b) shows the corresponding potential distribution at the level of the cross section perpendicular to the x-direction at the middle of device. It is important to note that the coaxial electrostatic gating is considered as a promising 9
e [eV]
5.25
-1.5
-1.2
r-direction [nm]
HfO2 3.25
-0.83
r
dCNT
0
2.00
x
-0.49 -0.16
HfO2
0.17
0.00
Source 0
10
Gate
Gate
Ungated
22
28
x-direction [nm]
0.50
Drain 40
50
(a) r [nm] 2.625
0.625 0.000 0.625
2.625
(b) Fig. 5. Two-dimensional potential distribution of the proposed SCG JL-CNTFET for (a) the longitudinal cross section and (b) for the cross section perpendicular to the x-direction at the middle of channel (x= 25 nm).
technique for futuristic high-performance CNTFET-based integrated circuits [43]-[45], due to its great ability in coaxially controlling the atomic-thick sheet of carbon. Fig. 5(a) shows the 2D potential distribution of the proposed device biased with VGS= 0.5 V and VDS=0.5 V. We can see that the potential aspect at the source and drain side are almost the same regarding the conventional CG JL-CNTFET. However, we can see the impact of the ungated region between the two coaxial gates on the electrostatics. As clearly seen, the whole electrostatic gating recorded in conventional case (Fig. 4(a)) is now divided by the ungated region (6 nm), while making the electrostatic impact of the CNT charge density more influential. Fig. 5(b) shows the potential distribution of the cross section perpendicular to the transport direction at the middle of the proposed SCG JL-CNTFET. By comparing the Fig. 4(b) and Fig. 5(b) we can clearly see the impact of the CNT charge density on the electrostatics of the ungated region. Thereafter, we will show and analyze the 10
102
VDS= 0.5 V CCG-JL CNTFET SCG-JL CNTFET LSP=3 nm LSP=4 nm LSP=5 nm LSP=6 nm
101
IDS [A]
100
LSP increasing
10-1
CNT(16,0); EG= 0.667 eV
10-2
OX=16; tOX=2 nm; 10-3
dCNT=1.25 nm; NCNT=2/nm LS(D)=10 nm; LG-EFF=30 nm.
10-4
-0.4
0.0
-0.2
0.2
0.4
VGS [V]
Fig. 6. The IDS-VGS transfer characteristics for conventional CG JL-CNTFET and the proposed SCG JLCNTFET.
improvements in electrical performance attributed to the employed ungated region that splits the conventional single gate into two coaxial gates. Fig. 6 shows the IDS-VGS properties of the conventional and proposed JL-CNTFETs. Note that the effective gate length with and without the consideration of ungated region is still equal to 30 nm. We can see that the increase in ungated distance, LSP, improves the minimal leakage current and decreases the band-to-band tunneling current. It is to indicate that the increase in LSP comes on the expense of LG1 and LG2, or equivalently, the increase in LSP decreases LG1 and LG2 equally while maintaining an effective gate length equal to 30 nm. Inspecting the same figure, it is clearly seen that the thermionic currents including the possible on-current are not influenced by the employed split gate design, and thus a significant improvement in terms of current ratio is expected. In order to have a deep view on the recorded results, we plot the electron density per unit energy and current spectrum versus x-position for both JL-CNTFETs under different gate bias conditions, as shown in Fig. 7. In Fig. 7, the top (bottom) line is the conduction (valence) edge band, and the region between the two horizontal white lines denotes the gap energy of the considered zigzag CNT. Inspecting the two contact regions in the figures of electron density spectrum, we can see that the electrons are filled up to the concerned Fermi levels, where the interference pattern are 11
(a)
(c)
(b)
(d)
Fig. 7. Electron density spectrum (dN/dE) versus x-position for (a) the conventional CG JL-CNTFET and (c) the proposed SCG JL-CNTFET. Energy-position-resolved current spectrum (Log10 I(x,E)) for (b) the conventional CG JL-CNTFET and (d) the proposed SCG JL-CNTFET. The basing condition is: VDS= 0.5 V and VGS=-0.5 V.
also apparent. Fig. 7(a) shows that the conventional CG JL-CNTFET exhibits a band-to-band tunneling (BTBT) from conduction band of the source to the conduction band of the drain through the valence band underneath the gate. Note that the ambipolar property and the relatively high minimum leakage current recorded in the transfer characteristic of the conventional CG JL-CNTFET (Fig. 6) is mainly attributed to this BTBT mechanism, which is known with its detrimental effects on subthreshold characteristics [19], [46]-[48]. Fig. 7(b) shows clearly the corresponding current spectrum in the conventional device. We can easily see that the BTBT current is the dominant component due to its high intensity while reflecting the recorded ambipolar property and the high leakage current. Considering the same biasing conditions (VGS=-0.5 V) for the proposed SCG JLCNTFET, we can see in Fig. 7(c) that the proposed SCG JL-CNTFET alleviates the BTBT mechanism via the drop in potential (indicated by dashed circle) induced by the ungated region. As shown in Fig. 7(d), the BTBT current is decreased in comparison to that of conventional device due to the recorded curvature that opposes the BTBT components. This 12
explains the improvement in terms of leakage current and ambipolar behavior recorded in Fig. 6 using the split gate technique. Note that the decrease in LSP alleviates the recorded drop in potential that opposes the BTBT, and thus the BTBT increases. In this context, we emphasize that the BTBT can be further mitigated using the graded doping technique while dilating the left and right BTBT widths [49]. Inspection of Fig. 7(d) also reveals a kind of direct sourceto-drain tunneling (DSDT), which is attributed to the short length of the two coaxial gates in the proposed design while supporting the appearance of DSDT current. It is worth noting that the DSDT mechanism becomes more influential for ultra-scaled devices [48]. For this reason, the minimum (maximum) gate length (ungated spacing) considered in split gate design is chosen equal to 12 nm (6 nm) in order to avoid the detrimental effects of DSDT increasing. In the Fig. 8, the on-currents and off-currents are extracted from the Fig. 6 considering a power supply voltage (VDD) equal to 0.5 V. Note that each (ION,IOFF) point corresponds to 102 1
10
CCG-JL CNTFET SCG-JL CNTFET
LSP= 6 nm
IOFF [A]
100 10-1 10-2 10-3 10-4 10
VDD=0.5 V 20
(a) 30
40
50
60
70
80
ION [A]
105 CCG-JL CNTFET SCG-JL CNTFET LSP= 6 nm
104
ION/IOFF
103 102 101 100 10-1 10
VDD=0.5 V 20
(b) 30
40
50
60
70
80
ION [A]
Fig. 8. (a) IOFF versus ION and (b) ION/IOFF current ratio versus ION for both JL-CNTFETs.
13
(VGS-ON, VGS-OFF=VGS-ON-VDD), and thus the curves are within reach by sweeping a range of VGS. This technique, which is extensively used in literature [37], [49]-[51], allows to give a clearer picture concerning the off- and on-currents on one hand, and to reveal the maximum reachable current ratios on the other hand [49]-[51]. Fig. 8(a) shows the off-currents versus the on-currents for the two CNT-based devices under study. As shown, the proposed SCG JLCNTFET can provide lower off-current in comparison to its conventional counterpart, while the two devices share the same order of magnitude in terms of the on-currents. Therefore, higher current ratios can be obtained using the proposed design. Indeed, Fig. 8(b) shows that the maximum reachable ION-IOFF ratio of the proposed split gate JL-CNTFET is higher by about one order of magnitude than that of the conventional design. The intrinsic delay () is an important parameter that indicates how fast the JL-CNTFET can switch [52]. It can be numerically simulated using the following relation [51] =(QON-QOFF)/ION
(7)
where QON (QOFF) is the total charge in the whole CNT channel including the source and drain extension at on-state (off-state). Fig. 9(a) shows the intrinsic delay as a function of on-current for the proposed and conventional JL-CNTFET considering a power supply voltage equal to 0.5 V. The curves are plotted with a manner similar to that used to draw Fig. 8, where a VDD window is used to extract QOFF, QON and ION required for intrinsic delay estimation (12). Note that after each extraction, the window is shifted to extract the other switching cases while plotting the curve. It is easily seen that the proposed design exhibits shorter intrinsic delay regarding the conventional device over the shared range of on-currents. The recorded improvement in terms of intrinsic delay indicates that the suggested design can be a valuable option for high-speed applications. 14
1200 CCG-JL CNTFET SCG-JL CNTFET LSP= 6 nm
1000
[fs]
800 600 400
VDD=0.5 V
200 0
(a) 10
20
30
40
ION [A]
11.24 CCG-JL CNTFET SCG-JL CNTFET LSP= 6 nm
PDP [eV]
9.99
Maximum ION/IOFF
8.74
Maximum ION/IOFF
7.49
6.24
VDD=0.5 V
(b) 10
20
30
40
ION [A]
Fig. 9. (a) Intrinsic delay versus ION current of both JL-CNTFETs. (b) PDP versus ION for the conventional and proposed JL-CNTFET.
The power-delay product (PDP) is also an important switching parameter that indicates the energy required for a transition from on-state to off-state. The PDP can be numerically computed as [51] PDP=(QON-QOFF)VDD
(8)
Fig. 9(b) shows the power-delay product in function of on-current for the proposed design and its conventional counterpart considering VDD=0.5 V. It is clearly seen that the JLCNTFET endowed with split gate provides lower power-delay product than the conventional device over the shared range of on-currents. Inspecting the same figure, we can also see that the PDP that corresponds the maximum reachable current ratio of the proposed design is lower than that of the conventional design, indicating that the suggested design can be considered as a promising candidate for futuristic low-power applications. In addition to the 15
performance enhancement, the proposed SCG-based strategy can be considered as a promising alternative to the similar approaches based on strain, dielectric, doping, and work function engineering, which are still difficult to achieve accurately at nanoscale domain [914]. Note that the synergy of the proposed strategy with the aforementioned similar techniques including the dielectric engineering can further boost the performance of JL CNTFETs.
5. Conclusion In this paper, the switching performance of the JL-CNTFET has been improved using a new strategy based on the employment of a split surrounding gate. This latter has been used in order to alleviate the band-to-band tunneling mechanism that degrades the switching characteristics. The simulation results have revealed that the proposed SCG JL-CNTFET design is efficient in improving the ambipolar behavior, minimum leakage current, current ratio, intrinsic delay, and power-delay product. The findings obtained in this study empower the proposed SCG JL-CNTFET to be a favorable device for modern digital circuits.
16
References [1] J. Si, L. Xu, M. Zhu, Z. Zhang, and L. Peng, “Advances in High‐Performance Carbon‐Nanotube Thin‐Film Electronics,” Advanced Electronic Materials, vol. 5, no. 8, p. 1900122, Jun. 2019. [2] S. B. Desai, S. R. Madhvapathy, A. B. Sachid, J. P. Llinas, Q. Wang, G. H. Ahn, G. Pitner, M. J. Kim, J. Bokor, C. Hu, H.-S. P. Wong, and A. Javey, “MoS2 transistors with 1-nanometer gate lengths,” Science, vol. 354, no. 6308, pp. 99–102, Oct. 2016. [3] G. Hills, C. Lau, A. Wright, S. Fuller, M. D. Bishop, T. Srimani, P. Kanhaiya, R. Ho, A. Amer, Y. Stein, D. Murphy, Arvind, A. Chandrakasan, and M. M. Shulaker, “Modern microprocessor built from complementary carbon nanotube transistors,” Nature, vol. 572, no. 7771, pp. 595–602, Aug. 2019. [4] P. Avouris, J. Appenzeller, R. Martel, and S. J. Wind, “Carbon nanotube electronics,” Proceedings of the IEEE, vol. 9, no. 11, pp. 1772–1784, Nov. 2003. [5] F. Salimian and D. Dideban, “Comparative study of nanoribbon field effect transistors based on silicene and graphene,” Materials Science in Semiconductor Processing, vol. 93, pp. 92–98, Apr. 2019. [6] V. Khademhosseini, D. Dideban, M. Ahmadi, R. Ismail, and H. Heidari, “Single Electron Transistor Scheme Based on Multiple Quantum Dot Islands: Carbon Nanotube and Fullerene,” ECS Journal of Solid State Science and Technology, vol. 7, no. 10, pp. M145–M152, 2018. [7] V. KhademHosseini, D. Dideban, M. T. Ahmadi, and R. Ismail, “An analytical approach to model capacitance and resistance of capped carbon nanotube single electron transistor,” AEU - International Journal of Electronics and Communications, vol. 90, pp. 97–102, Jun. 2018. [8] A. H. Bayani, D. Dideban, M. Akbarzadeh, and N. Moezi, “Benchmarking Performance of a Gate-AllAround Germanium Nanotube Field Effect Transistor (GAA-GeNTFET) against GAA-CNTFET,” ECS Journal of Solid State Science and Technology, vol. 6, no. 4, pp. M24–M28, 2017. [9] A. Naderi and S. A. Ahmadmiri, “Attributes in the Performance and Design Considerations of Asymmetric Drain and Source Regions in Carbon Nanotube Field Effect Transistors: Quantum Simulation Study,” ECS Journal of Solid State Science and Technology, vol. 5, no. 7, pp. M63–M68, 2016. [10] B. A. Tahne and A. Naderi, “SLD-MOSCNT: A new MOSCNT with step–linear doping profile in the source and drain regions,” International Journal of Modern Physics B, vol. 31, no. 01, p. 1650242, Jan. 2017. [11] A. Naderi and M. Ghodrati, “Improving band-to-band tunneling in a tunneling carbon nanotube field effect transistor by multi-level development of impurities in the drain region,” The European Physical Journal Plus, vol. 132, no. 12, Dec. 2017. [12] A. Naderi and P. Keshavarzi, “The effects of source/drain and gate overlap on the performance of carbon nanotube field effect transistors,” Superlattices and Microstructures, vol. 52, no. 5, pp. 962–976, Nov. 2012.
17
[13] A. Naderi and P. Keshavarzi, “Novel carbon nanotube field effect transistor with graded double halo channel,” Superlattices and Microstructures, vol. 51, no. 5, pp. 668–679, May 2012. [14] A. Naderi, S. M. Noorbakhsh, and H. Elahipanah, “Temperature Dependence of Electrical Characteristics of Carbon Nanotube Field-Effect Transistors: A Quantum Simulation Study,” Journal of Nanomaterials, vol. 2012, pp. 1–7, 2012. [15] A. D. Franklin, “The road to carbon nanotube transistors,” Nature, vol. 498, no. 7455, pp. 443-444, Jun.2013. [16] A. D. Franklin et al., “Carbon nanotube complementary wrap-gate transistors,” Nano Lett., vol. 13, no. 6, 2013. [17] A. Naderi and B. A. Tahne, “Review—Methods in Improving the Performance of Carbon Nanotube Field Effect Transistors,” ECS Journal of Solid State Science and Technology, vol. 5, no. 12, pp. M131–M140, 2016. [18] L. Ansari et al., “First Principle-Based Analysis of Single-Walled Carbon Nanotube and Silicon Nanowire Junctionless Transistors,” IEEE Transactions on Nanotechnology, vol. 12, no. 6, pp. 1075–1081, 2013. [19] K. Tamersit, “Quantum simulation of a junctionless carbon nanotube field-effect transistor with binary metal alloy gate electrode,” Superlattices and Microstructures, vol. 128, pp. 252–259, Apr. 2019. [20] M. A. Barik, R. Deka, and J. C. Dutta, “Carbon nanotube-based dual-gated junctionless field-effect transistor for acetylcholine detection,” IEEE Sensors J., vol. 16, no. 2, pp. 280–286, Jan. 2016. [21] C.-W. Lee et al., “Junctionless multigate field-effect transistor,” Appl. Phys. Lett., vol. 94, no. 5, 2009. [22] J.-P. Colinge et al., “Nanowire transistors without junctions,” Nature Nanotech., vol. 5, no. 3, p. 225, 2010. [23] C.-W. Lee et al., “Performance estimation of junctionless multigate transistors,” Solid-State Electronics, vol. 54, no. 2, pp. 97–103, Feb. 2010. [24] J. P. Colinge et al., “Junctionless Nanowire Transistor (JNT): Properties and design guidelines,” Solid-State Electronics, vol. 65–66, pp. 33–37, Nov. 2011. [25] P. Pourian, R. Yousefi, and S. S. Ghoreishi, “Effect of uniaxial strain on electrical properties of CNT-based junctionless field-effect transistor: Numerical study,” Superlattices Microstruct., vol. 93, pp. 92–100, May 2016. [26] M. P. Anantram et al., “Modeling of Nanoscale Devices,” Proceedings of the IEEE, vol. 96, no. 9, 2008. [27] S. Datta, “Nanoscale device modeling: The Green’s function method,” Superlattices Microstruct., vol. 28, no. 4, pp. 253–278, Oct. 2000. [28] J. Guo, S. Datta, and M. Lundstrom, “A Numerical Study of Scaling Issues for Schottky-Barrier Carbon Nanotube Transistors,” IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 172–177, 2004.
18
[29] K. Tamersit and F. Djeffal, “Carbon Nanotube Field-Effect Transistor With Vacuum Gate Dielectric for Label-Free Detection of DNA Molecules: A Computational Investigation,” IEEE Sensors Journal, vol. 19, no. 20, pp. 9263–9270, Oct. 2019. [30] J. Guo, S. Datta, M. Lundstrom, and M. P. Anantam, “Toward Multiscale Modeling of Carbon Nanotube Transistors,” Int. J. Multiscale Comput. Eng., vol. 2, no. 2, pp. 257–276, 2004. [31] K. Tamersit and F. Djeffal, “A computationally efficient hybrid approach based on artificial neural networks and the wavelet transform for quantum simulations of graphene nanoribbon FETs,” Journal of Computational Electronics, vol. 18, no. 3, pp. 813–825, May 2019. [32] N. B. Bousari, M. K. Anvarifard, and S. Haji-Nasiri, “Improving the electrical characteristics of nanoscale triple-gate junctionless FinFET using gate oxide engineering,” AEU - International Journal of Electronics and Communications, vol. 108, pp. 226–234, Aug. 2019. [33] S. O. Koswatta et al., “Nonequilibrium Green’s function treatment of phonon scattering in carbon-nanotube transistors,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2339–2351, Sep. 2007. [34] K. Tamersit and F. Djeffal, “Double-Gate Graphene Nanoribbon Field-Effect Transistor for DNA and Gas Sensing Applications: Simulation Study and Sensitivity Analysis,” IEEE Sensors Journal, vol. 16, no. 11, pp. 4180–4191, Jun. 2016. [35] K. Tamersit, “Performance Assessment of a New Radiation Dosimeter Based on Carbon Nanotube FieldEffect Transistor: A Quantum Simulation Study,” IEEE Sensors Journal, vol. 19, no. 9, pp. 3314–3321, May 2019. [36] K. Tamersit and F. Djeffal, “A novel graphene field-effect transistor for radiation sensing application with improved sensitivity: Proposal and analysis,” Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, vol. 901, pp. 32–39, Sep. 2018. [37] A. Javey et al., “High performance n-type carbon nanotube field-effect transistors with chemically doped contacts,” Nano Lett., vol. 5, no. 2, pp. 345–348, Feb. 2005. [38] D. Berdebes et al., “Substrate gating of contact resistance in graphene transistors,” IEEE Trans. Electron Devices, vol. 58, no. 11, pp. 3925–3932, Nov. 2011. [39] J. Appenzeller et al., “Band-to-band tunneling in carbon nanotube field-effect transistors,” Physical review letters, vol. 93, no. 19, pp. 196805-1–196805-4, Nov. 2004. [40] J. Guo, “Modeling of graphene nanoribbon devices,” Nanoscale, vol. 4, no. 18, pp. 5538–5548, Sep. 2012. [41] B. Wei and C. Lu, “Transition metal dichalcogenide MoS2 field-effect transistors for analog circuits: A simulation study,” AEU - International Journal of Electronics and Communications, vol. 88, pp. 110–119, May 2018.
19
[42] S. Bruzzone et al., “An open-source multiscale framework for the simulation of nanoscale devices,” IEEE Trans. Electron Devices, vol. 61, no. 1, pp. 48–53, Jan. 2014. [43] M. Khaleqi Qaleh Jooq, A. Mir, S. Mirzakuchaki, and A. Farmani, “A robust and energy-efficient nearthreshold SRAM cell utilizing ballistic carbon nanotube wrap-gate transistors,” AEU - International Journal of Electronics and Communications, vol. 110, p. 152874, Oct. 2019. [44] E. Shahrom and S. A. Hosseini, “A new low power multiplexer based ternary multiplier using CNTFETs,” AEU - International Journal of Electronics and Communications, vol. 93, pp. 191–207, Sep. 2018. [45] A. Singh, M. Khosla, and B. Raj, “Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM,” AEU - International Journal of Electronics and Communications, vol. 80, pp. 67–72, Oct. 2017. [46] K. Tamersit and F. Djeffal, “Boosting the performance of a nanoscale graphene nanoribbon field-effect transistor using graded gate engineering,” Journal of Computational Electronics, vol. 17, no. 3, pp. 1276–1284, Jun. 2018. [47] G. Fiori and G. Iannaccone, “Simulation of Graphene Nanoribbon Field-Effect Transistors,” IEEE Electron Device Letters, vol. 28, no. 8, pp. 760–762, Aug. 2007. [48] J. Luo et al., “Compact model for carbon nanotube field-effect transistors including nonidealities and calibrated with experimental data down to 9-nm gate length,” IEEE Trans. Electron Devices, vol. 60, no. 6, pp. 1834–1843, Jun. 2013. [49] R. Yousefi et al., “Numerical Study of Lightly Doped Drain and Source Carbon Nanotube Field Effect Transistors,” IEEE Transactions on Electron Devices, vol. 57, no. 4, pp. 765–771, Apr. 2010. [50] Y. Yoon and Jing Guo, “Analysis of Strain Effects in Ballistic Carbon Nanotube FETs,” IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1280–1287, Jun. 2007. [51] S. O. Koswatta et al., “Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs,” IEEE Transactions on Electron Devices, vol. 56, no. 3, pp. 456–465, Mar. 2009. [52] Y. Ouyang et al., “Scaling Behaviors of Graphene Nanoribbon FETs: A Three-Dimensional Quantum Simulation Study,” IEEE Transactions on Electron Devices, vol. 54, no. 9, pp. 2223–2231, Sep. 2007.
20
Author declares that there is no conflicts of interest.
21