Impact of the H2 bake temperature on the structural properties of tensily strained Si layers on SiGe

ARTICLE IN PRESS

Journal of Crystal Growth 310 (2008) 2493–2502 www.elsevier.com/locate/jcrysgro

Impact of the H2 bake temperature on the structural properties of tensily strained Si layers on SiGe J.M. Hartmann, Y. Bogumilowciz, A. Abbadie, F. Fillot, T. Billon CEA-LETI, MINATEC, 17, Rue des Martyrs, 38054 Grenoble Cedex 9, France Received 5 October 2007; received in revised form 7 January 2008; accepted 13 January 2008 Communicated by D.W. Shaw Available online 30 January 2008

Abstract We have studied the impact of various H2 bakes (in-between 750 and 850 1C, this for durations in-between 15 and 120 s) on the structural properties of 16 nm thick sSi layers grown on top of polished Si0.7Ge0.3 and Si0.6Ge0.4 virtual substrates (VSs) after an ‘‘HF-last’’ wet cleaning. Those stacks have been characterized afterwards thanks to tapping mode—atomic force microscopy (AFM), surface light scattering (haze measurements), secondary ions mass spectrometry and Secco defect revelation. A definite oxygen contamination peak at the sSi/SiGe interface was associated to 750 1C, 120 s H2 bakes. The resulting sSi layers were heavily defected and rough. By contrast, temperatures superior or equal to 800 1C yielded contamination-free interfaces. No clear impact of the H2 bake temperature (X800 1C) and/or duration on the threading dislocation density and the ‘‘line’’ defect linear density was evidenced. Higher temperatures and longer bakes yielded rougher surfaces, however. The best compromise seemed to be {850 1C, 15 s} H2 bakes. For such bakes, the surface root mean square surface roughness was in-between 0.1 and 0.2 nm only (10 mm  10 mm AFM images). r 2008 Elsevier B.V. All rights reserved. PACS: 81.15.Gh; 61.72.Hf; 68.37.Ps; 68.55.Jk Keywords: A1. Surface structure; A1. Defects; A1. Interfaces; A3. Chemical vapour deposition processes; B1. Germanium silicon alloys

1. Introduction Biaxial tensile strained Si layers epitaxially grown on top of high Ge content SiGe virtual substrates (VSs) [1] are of great interest for complementary metal-oxide-semiconductor (CMOS) devices. Increased transistor performances indeed occur as a direct result of increased electron and hole mobilities caused by the tensile strain. For electrons, the six-fold degeneracy of the conduction band minima in the D/0 0 1S directions is split, such that the two out-of plane D2 valleys are at a lower energy than the four in-plane D4 valleys, resulting in reduced intervalley carrier scattering. An increase of the electron mobility in tensile-strained Si (sSi) by a factor of up to 1.8 (compared to bulk Si) has been evidenced for Ge concentrations of the underlying SiGe VS superior or equal to 20% [2]. For holes, the degeneracy of Corresponding author. Tel.: +33 4 38 78 95 24; fax: +33 4 38 78 30 34.

E-mail address: [email protected] (J.M. Hartmann). 0022-0248/$ - see front matter r 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.jcrysgro.2008.01.033

the valence band at the G point is lifted and the light-hole band is preferentially populated, again resulting in reduced intervally carrier scattering and also reduced effective mass. The hole mobility enhancement in sSi can reach a factor of 2.2, albeit for Ge concentrations superior or equal to 40% [3]. The tensile-strained Si layers on top of those SiGe VSs can be transferred onto an oxidized Si wafer through the TM SmartCut process for strained silicon-on-insulator (sSOI) fabrication [4]. Such sSOI substrates, presenting the advantage of having a tensile-strained thin Si layer on top of a buried insulating layer, yield high performance fully depleted field effect transistors (FETs) [5,6]. We have quite recently investigated the structural properties of sSi layers grown on top of polished Si1xGex VSs (with x equal either to 0.2, 0.3, 0.4 or 0.5) as a function of (i) their thickness and (ii) the growth chemistry and temperature adopted to deposit the sSi layers (either SiH2Cl2 at 700 1C or SiH4 at 600 1C) [7–9]. The surface preparation adopted in all cases was the following

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one: (i) a ‘‘HF-last’’ wet cleaning that yielded SiGe surfaces mostly free of native oxide and carbon contamination followed by (ii) a 850 1C, 120 s H2 bake at 20 Torr in order to get rid of the remaining C and O atoms on the surface prior to sSi re-growth [10]. We have studied here the impact of various H2 bakes (in-between 750 and 850 1C, this for durations in-between 15 and 120 s) on the structural properties of sSi layers grown at 700 1C on top of polished Si0.7Ge0.3 and Si0.6Ge0.4 VSs. The target is to determine the process parameters yielding the smoothest and lowest defect density sSi films without any sSi/SiGe interfacial contamination. 2. Experimental details We have used an Epi Centura reduced pressure-chemical vapor deposition (RP-CVD) tool from Applied Materials to perform all the epitaxial growths of this study. Hydrogen at a flow of a few tens of standard liters per minute was used as the carrier gas. The growth pressure was fixed at 20 Torr at all times. Pure dichlorosilane was used as the Si gaseous precursor. Germane diluted at 2% in hydrogen was used as the germanium gaseous precursor. The F(SiH2Cl2)/F(H2) mass-flow ratios and the growth temperature used to grow the 16 nm thick sSi layers were 0.01 and 700 1C. Prior to the growth of sSi, the polished SiGe VSs were subjected to an ‘‘HF-last’’ wet cleaning followed by various thermal budget H2 bakes inside the RP-CVD chamber in order to start ideally from smooth, contamination free surfaces. The following H2 bake temperatures and durations were studied: {750 1C, 120 s}, {800 1C, 120 s}, {850 1C, 15 s}, {850 1C, 30 s} and finally {850 1C, 120 s}. The bake pressure and the H2 flows were the same than those used for the growth of SiGe and sSi: 20 Torr and a few tens of standard litres per minute. Omega–2theta (o–2y) scans around the (0 0 4) and (2 2 4) diffraction orders were acquired thanks to a MRD Panalytical high-resolution X-ray diffractometer. The Cu Ka1 wavelength (l ¼ 1.5406 A˚) was selected by a fourcrystal Ge (2 2 0) monochromator. The X-ray reflectivity curves were acquired on a Jordan–Valley tool with a copper anti-cathode. Tapping mode atomic force microscopy (AFM) measurements were carried out on a Digital Instrument Dimension 3100 system. Surface light scattering measurements were performed on a SP2UV tool from KLA Tencor. The secondary ion mass spectrometry (SIMS) measurements were carried out on a Cameca IMS 5f spectrometer. Cs+ primary ions were used for silicon and germanium depth profiling, with a low-impact energy of 2 keV at 501 to obtain a high depth resolution. The atomic masses monitored were those of Cs2C+ (133  2+12 ¼ 285 atomic mass units or amu), Cs2O+ (133  2+16 ¼ 282 amu), Cs2F+ (133  2+19 ¼ 285 amu), Cs2Si+ (133  2+28 ¼ 294 amu) and Cs2Ge+ (133  2+ 70 ¼ 336 amu). Defects revelation was carried out thanks to the selective wet etching solution pioneered by F. Secco d’Arragona [11], i.e. (K2Cr2O7+H2O)/HF, 2/1. A diluted

0.02 M Secco solution (etch rate 10 A˚/s) was used to delineate defects in the sSi layers. The whole sSi layers and a few nanometers of the SiGe layers underneath were etched for all samples. 3. The starting SiGe VSs The Si0.7Ge0.3 and the Si0.6Ge0.4 VSs were grown at 850–900 1C (using Ref. [12] data points) on 200 mm slightly p-type doped Si(0 0 1) substrates. These SiGe VSs consist in (i) a graded germanium concentration layer with a grading rate of 8% Ge mm1 in our case, starting from a few % of Ge and increasing gradually to the final Ge concentration, followed by (ii) a 1 mm thick constant Ge composition SiGe layer [1]. The grading rate is low enough to ensure a good final constant composition layer, while being still high enough so that the entire structure thickness is still reasonable (i.e. less than 10 mm). With this growth sequence, the top layer is expected to be almost totally relaxed, with threading dislocations densities (TDDs) of the order of 105 cm2 [7–9]. After the use of several chemical mechanical polishing (CMP) steps to get rid of the surface cross-hatch, the surfaces of those SiGe VSs were cleaned in an automated wet bench [13]. Conventional o–2y scans around the (0 0 4) and the (2 2 4) X-ray diffraction (XRD) orders allowed us to determine precisely the germanium concentration and the macroscopic degree of strain relaxation of the constant composition SiGe layers sitting on top of some of our samples. More details about the protocol used to deal with the experimental data can be found in Ref. [1]. We have found for the Si0.6Ge0.4 VSs a mean Ge concentration and a mean macroscopic degree of strain relaxation R equal to 36.9% and 99.6%, respectively. For the Si0.7Ge0.3 VSs, these parameters are equal to 27.2% and 99.5%, respectively. 4. sSi surface morphology 4.1. Specular X-ray reflectivity: sSi film thickness and surface roughness determination We have used specular X-ray reflectivity (SXR) to determine the sSi layer thickness in our samples. As an example, we have plotted in Fig. 1 the SXR curves associated with {sSi layer/Si0.63Ge0.37 or Si0.73Ge0.27 VS} stacks with a sSi layer thickness around 16 nm. As soon as the critical angle for total external reflection (o0.251) is exceeded, we are faced (as X-rays penetrate into the stack) with a sharp drop of the reflected intensity, whose decrease is a function of the surface roughness. Superimposed to this decay slope, we have for sSi-capped SiGe VSs some welldefined interference fringes whose angular spacing is inversely proportional to the sSi layer thickness. We have used the optical electromagnetic wave solution of the Fresnel equation on each interface to solve the problem of the propagation of X-rays in our sSi/SiGe stacks at grazing

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10-2 10-3

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Fig. 1. Specular X-ray reflectivity curves associated to the sSi/Si0.73Ge0.27 and sSi/Si0.63Ge0.37 stacks after H2 bakes at 850 1C for 120 s. The sSi/ Si0.63Ge0.37 curve was shifted vertically for clarity purposes (normalized intensity (to that for total external reflection) multiplied by 10). Please note the better-defined thickness fringes for sSi/Si0.63Ge0.37 than for sSi/ Si0.73Ge0.27, which is due to a larger material density difference (and thus optical index difference) for higher Ge content VS.

incidence angles and thus fit our experimental SXR profiles. With this formalism, the sSi layers and the SiGe VSs underneath are defined by a single transfer matrix taking into account their refractive index n ¼ 1dib (d and b depend on the material density r), their thickness t (taken as infinite for the SiGe VSs), the surface or interface root mean square roughness s and the angle of incidence o [14–16]. A mean thickness of 15.670.2 nm is associated to sSi layers grown on top of Si0.73Ge0.27. This value is slightly higher for sSi layers grown with exactly the same process parameters on top of Si0.63Ge0.37: 16.170.2 nm. The associated sSi growth rates, 2.17 nm min1 on Si0.73Ge0.27 and 2.23 nm min1 on Si0.63Ge0.37, are quite close to the ones found for the same process conditions on (i) Si0.52Ge0.48 and Si0.60Ge0.40 (2.37 nm min1) [7] and (ii) Si0.71Ge0.29 and Si0.79Ge0.21 (2.30 nm min1) [9]. Let us now focus on the surface roughness parameter ssurf. that is linked to the decay of the SXR curves as the angle of incidence gets higher (see Fig. 2). For sSi on Si0.73Ge0.27, it is more or less constant at 2.1 A˚ for all save the highest H2 bake thermal budget probed, (i.e. {850 1C, 120 s}) for which it is equal to 2.5 A˚. For sSi on Si0.63Ge0.37, the trend is somewhat different. It decreases from 3.25 A˚ for {750 1C, 120 s} down to 2.05 A˚ for {800 1C, 120 s}, {850 1C, 15 s} and {850 1C, 30 s}. This is likely due to the change seen in AFM from rough to smooth surfaces as the H2 bake temperature increases from 750 1C up to 800 1C (see Section 4.2 and the bottom part of Fig. 3). Then, the surface roughness increases up to 2.75 A˚ for

0 750°C, 120s

800°C, 850°C, 850°C, 120s 15s 30s H2 bake conditions

850°C, 120s

Fig. 2. Surface roughness parameter ssurf. extracted from the SXR curves acquired on our sSi/SiGe stacks as a function of the various H2 bakes probed in this study.

{850 1C, 120 s}. The overall conclusion is thus that, at least from the SXR point of view, {850 1C, 120 s} yields rougher surfaces than lower thermal budget H2 bakes (with the exclusion of the {750 1C, 120 s} H2 bake for sSi on Si0.63Ge0.37). 4.2. AFM: small scale surface morphology We have imaged the surface of all our samples in tapping-mode AFM. 10 mm  10 mm images can be found in Fig. 3. CMP has enabled us to get rid of the surface cross-hatch along the /1 1 0S directions (spatial wavelength of the order of 1–2 mm) inherent to as-grown SiGe VSs [1]. It slightly re-appeared after the {‘‘HF-last’’ wet cleaning/850 1C, 120 s in-situ H2 bake} surface preparation and the sSi layer growth that followed (as an illustration, please have a look at the images associated to the 850 1C, 30 s H2 bakes). Numerous small mounds (on top of the resurgent surface cross-hatch) can be found in most of the images of the samples with H2 thermal budgets superior or equal to 800 1C, 120 s. What is most interesting is that: (i) Their diameter seems to increase from roughly one hundred to several hundreds of nm as the H2 bake temperature and duration increase. (ii) The height of those mounds is larger for sSi on Si0.73Ge0.27 than for sSi on Si0.63Ge0.37. This trend is quite marked for higher thermal budget H2 bakes. For {850 1C, 120 s}, mounds are indeed barely visible on the surface of the sSi on Si0.63Ge0.37 stack.

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10 800°C, 120s

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5

7.5

10 0

2.5

5 μm

7.5

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2.5 nm 5

0 nm 16 nm sSi on Si0.6Ge0.4 VS

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Fig. 3. The 10 mm  10 mm AFM images of the surface of 16 nm thick sSi layers grown on top of polished Si0.73Ge0.27 and Si0.63Ge0.37 VS after an ‘‘HFlast’’ wet cleaning followed by various thermal budget H2 bakes (see the figure’s insets for details). Image sides are more or less along the /1 0 0S crystallographic directions.

Other features have been found on the AFM images. For a 750 1C, 120 s H2 bake on Si0.73Ge0.27 and for a 800 1C, 120 s H2 bake on Si0.63Ge0.37, there is the presence of numerous lines running along the /1 1 0S directions together with spots. More quantitatively, the ‘‘line’’ linear densities are around 83 000 and 14 000 cm1, respectively. Meanwhile, the ‘‘spots’’ area densities are around 6  108 and 3  107 cm2, respectively. Lines are most likely due to the formation of a large number of dislocations because of an imperfect surface preparation. Those dislocation would

have (because of the tensile strain) glided on /1 1 1S planes during the growth of the sSi layers, leaving in their wake stacking faults (SFs) and ‘‘ploughing’’ lines on the surface. The spots are thought to be due to locally poly-crystalline Si, once again because of an imperfect surface preparation. One should notice that the density of lines and spots is much higher for a 750 1C, 120 s H2 bake on Si0.73Ge0.27 than for a 800 1C, 120 s H2 bake on Si0.63Ge0.37, however. In order to compare things which are comparable, let us now focus on the 750 1C, 120 s H2 bake on Si0.63Ge0.37. In

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this case, the density of spots is huge, the surface has a morphology more akin to that of a poly-crystalline layer. From Fig. 3 images, it would thus seem that {800 1C, 120 s} and higher thermal budget H2 bakes yield good surface morphologies for sSi on Si0.73Ge0.27. By contrast, {850 1C, 15 s} and higher thermal budget H2 bakes seem mandatory to obtain acceptable surface morphologies for sSi on Si0.73Ge0.27. Indeed, {750 1C, 120 s} and {800 1C, 120 s} H2 bakes generate heavily defected sSi layers when grown on top of Si0.73Ge0.27 and Si0.63Ge0.37, respectively. Meanwhile, {750 1C, 120 s} H2 bakes lead apparently to the formation of a poly-crystalline Si layer when grown on top of Si0.63Ge0.37. The root mean square (rms) roughness and the Z ranges ( ¼ ZmaxZmin) extracted from the 10 mm  10 mm images of Fig. 3 are plotted in Fig. 4 as a function of the H2 bake conditions. For sSi on Si0.73Ge0.27, the rms roughness decreases from 2.1 down to 1.5 A˚ as we move from a {750 1C, 120 s} to a {800 1C, 120 s} H2 bake. It then increases monotonously back up to 2.5 A˚ as the H2 bake reaches {850 1C, 120 s}. For sSi on Si0.63Ge0.37, the trend is somewhat different. The rms roughness indeed decreases from 4.8 down to 1.3 A˚ as the H2 bake goes from {750 1C, 120 s} up to {800 1C, 120 s}. It then stays more or less constant for higher thermal budget H2 bakes. Z ranges follow the same trends as the rms roughness, be it for sSi on Si0.63Ge0.37 or sSi on Si0.73Ge0.27. It thus seems that the surfaces of sSi layers grown on top of Si0.63Ge0.37 are smoother than the ones grown on top of Si0.73Ge0.27. Such

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a trend might be due to the higher tensile strain accumulated in sSi layers deposited on higher Ge content layers that leads to a gradual surface smoothening as growth proceeds. We have indeed recently noticed that the surfaces of sSOI substrates were smoother than the ones of conventional SOI substrates [17]. This reduction of surface roughness (which may be due to the increased step energy due to tensile strain [18]) might partially explain the increased electron mobility in strained Si [19]. 4.3. Surface light scattering: large scale surface morphology In a Surfscan SP2UV surface inspection system, the light coming out of a 360 nm wavelength laser is scanned over the surface of a wafer under normal or oblique incidence [20]. Both light point defects and haze can be extracted from the scattered light which is captured thanks to narrow or wide collection channels. We have plotted in Figs. 5 and 6 the normal incidence wide (DW) and narrow (DN) hazes (in parts per million or ppm) obtained on our samples prior to the ‘‘HF-last’’ wet cleaning and just after the epitaxy of sSi, this for different H2 bake conditions. A DW configuration will be most sensitive to surface roughness with spatial wavelengths in the 0.3–1 mm range, i.e. to the small surface mounds of Fig. 3. By contrast, a DN setup will give us information about the surface crosshatch, as its sensitivity range is in-between slightly more than 1 and 3 mm [21].

10 Z range - sSi on Si0.6 Ge 0.4

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Z range - sSi on Si0.7 Ge 0.3

sSi on Si0.6 Ge0.4 sSi on Si0.7 Ge0.3 Si0.6 Ge0.4 - after CMP Si0.7 Ge0.3 - after CMP 1

0.3 μm < λ < 1 μm

0.1 750°C, 120s

800°C, 850°C, 850°C, 120s 15s 30s H2 bake conditions

850°C, 120s

Fig. 4. Surface root mean square (rms) roughness and Z ranges after the epitaxy of 16 nm of sSi on top of polished Si0.73Ge0.27 and Si0.63Ge0.37 VS, this after an ‘‘HF-last’’ wet cleaning followed by various thermal budget H2 bakes (values coming from Fig. 3 images).

0.1 750°C, 120s

800°C, 850°C, 850°C, 120s 15s 30s H2 bake conditions

850°C, 120s

Fig. 5. DW haze values prior to or just after the epitaxy of 16 nm of sSi on top of polished Si0.73Ge0.27 and Si0.63Ge0.37 VS, this after an ‘‘HF-last’’ wet cleaning followed by various thermal budget H2 bakes.

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sSi on Si0.6 Ge0.4 sSi on Si0.7 Ge0.3

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1 μm < λ < 3 μm

1 Si 0.6 Ge0.4 - after CMP Si 0.7 Ge0.3 - after CMP

0.1

750°C, 120s

800°C, 850°C, 850°C, 120s 15s 30s H2 bake conditions

850°C, 120s

Fig. 6. DN haze values prior to or just after the epitaxy of 16 nm of sSi on top of polished Si0.73Ge0.27 and Si0.63Ge0.37 VS, this after an ‘‘HF-last’’ wet cleaning followed by various thermal budget H2 bakes.

Let us first talk about the haze values associated to the polished SiGe VSs prior to the HF-last wet cleaning. Values were fairly uniform in-between same Ge concentration wafers. A haze increase was, however, noticed when moving from Si0.73Ge0.27 to Si0.63Ge0.37 VSs. This was likely due to a slightly imperfect chemical mechanical polishing for higher Ge content VSs, most probably because of a much rougher growth surface [1]. A huge increase of the DW and DN hazes occurred for sSi-capped layers. Let us first deal with the DW values (see Fig. 5). A monotonic increase of the haze occurred for sSi on Si0.73Ge0.27 as the H2 bake thermal budget increased from {750 1C, 120 s} up to {850 1C, 120 s}. The behavior for sSi on Si0.63Ge0.37 is somewhat different: the DW haze increases when moving from {750 1C, 120 s} up to {850 1C, 15 s}. It then decreases as the H2 bake time at 850 1C increases. Such DW evolutions are quite in-line with Fig. 3 AFM images and Fig. 4 roughness data. For H2 bake temperatures superior or equal to 800 1C, numerous small mounds were indeed present for sSi on Si0.73Ge0.27. Their characteristic dimensions were found to increase as the H2 thermal budget increases, explaining the monotonous DW increase. By contrast, the small mounds present on the surface of sSi on Si0.63Ge0.37 decreased in height as the H2 bake time at 850 1C increased, partly explaining the belllike evolution of DW for sSi on Si0.63Ge0.37. We are now going to focus on the DN haze, which should be most sensitive to any surface cross-hatch resurgence (see Fig. 6). One has indeed to keep in mind that although the surface of SiGe VS is flat and featureless

after CMP, a periodic strain field (with a spatial wavelength along the /1 1 0S directions of the order of 1–2 mm) is still present inside the constant composition layer (see Ref. [8] and references therein). For polished SiGe VS capped by several hundreds of nm of same Ge content SiGe, this strain field would lead to the reappearance of a definite surface cross-hatch. In other words, a polished, flat surface is metastable while a crosshatched one is closer to equilibrium. The DN haze increased more or less monotonously as the thermal budget of the H2 bake increased. The higher DN haze values for sSi on Si0.63Ge0.37 than for sSi on Si0.73Ge0.27 might partly be due to the surface roughness after CMP which is higher on Si0.63Ge0.37 than on Si0.73Ge0.27. Those larger haze values might also be due to the Ge concentration itself. Higher Ge content SiGe VS have just after growth (i.e. closer to equilibrium) a much more pronounced surface cross-hatch than lower Ge content VS. A 12 nm rms roughness is indeed associated to Si0.5Ge0.5 VS, versus 2–3 nm for Si0.8Ge0.2 VS, for example [1]. The slight reappearance of the surface cross-hatch would thus be favoured for 37% of Ge, hence the higher DN haze values. 5. SIMS: interfacial contamination We have profiled in SIMS the Si, the Ge, the C, the O and the F atoms concentration in all the sSi/SiGe stacks. The relative sensitivity factors (RSFs) of C, O and F in Si [22] were used to convert the Cs2C+, Cs2O+ and Cs2F+ secondary ions [23] detected by the magnetic sector mass spectrometer of the SIMS apparatus into C, O and F atomic concentrations. The Cs2Ge+ signal conversion into a Ge atomic concentration was such that a perfect matching between SIMS and XRD data occurred away from the sSi layer. As an example, we have plotted in Fig. 7 the profiles that have been obtained after a {850 1C, 120 s} H2 bake prior to the growth of roughly 16 nm of sSi on top of Si0.63Ge0.37. No C, O or F contamination peaks are present at the sSi/SiGe interface. No C and F interfacial contamination peaks were observed for lower thermal budget H2 bakes, this whatever the Ge content. By contrast, a definite O interfacial contamination peak was noticed for {750 1C, 120 s} H2 bakes. This peak disappeared for {800 1C, 120 s} and higher thermal budget H2 bakes, as illustrated in Fig. 8 for sSi on Si0.63Ge0.37 (the same phenomenon occurred for sSi on Si0.73Ge0.27). Let us define the {750 1C, 120 s} interfacial contamination by the O peak concentration (in at. cm3) multiplied by its full width at half maximum (in cm). Very similar O doses, 3.15  1014 and 3.35  1014 at. cm3, are associated to sSi on Si0.73Ge0.27 and to sSi on Si0.63Ge0.37. Those values can quite instructively be compared to the surface atoms concentration, 6.64  1014 at. cm3 for Si0.73Ge0.27 and 6.59  1014 at. cm3 for Si0.63Ge0.37. This would mean that roughly half of the surface sites are occupied by O atoms after {750 1C, 120 s} H2 bakes. One has, however, to keep in mind that the RSFs of O in Si were adopted for O atoms

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Ge, O, C and F atoms conc. (cm-3)

1022

sSi layers deposited on top of as-grown (i.e. with a definite surface cross-hatch) Si0.8Ge0.2 and Si0.67Ge0.33 VSs, the minimum H2 bake temperature was found to be 800 1C. Bake temperatures 25 1C lower (i.e. 750 1C for Si, 775 1C for SiGe) indeed yielded interfacial O contaminations peaks.

Ge

Si 0.63Ge 0.37

sSi

1021

O

1020

6. Secco defect revelation

1019 C 1018

850°C, 120s H2 bake

F

1017 0

10

20 30 Depth (nm)

40

50

Fig. 7. SIMS depth profile of the Ge, O and F atoms concentrations in a sSi/Si0.63Ge0.37 stack after a {850 1C, 120 s} H2 bake. The position of the interface is given by the vertical dashed line.

O atoms conc. (cm-3)

750°C, 120s 800°C, 120s 850°C, 15s 1021 Si0.63 Ge0.37

sSi

1020

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Fig. 8. SIMS depth profile of the O atoms concentrations in sSi/ Si0.63Ge0.37 stacks after {750 1C, 120 s}, {800 1C, 120 s} and {850 1C, 15 s} H2 bakes. The position of the interface is given by the vertical dashed line.

concentration determination, while the interfacial layer is made of SiGe, with slightly varying RSFs (explaining why the O peak is not symmetric). Such findings are quite in-line with the ones we had previously obtained for 120 s H2 bakes (also at 20 Torr) on Si and on as-grown SiGe VSs [10]. We had indeed noticed that a 775 1C bake temperature was mandatory in order to avoid the presence of an O contamination peak on Si. For

Finally, we have proceeded with Secco defect revelation of our sSi/SiGe stacks in order to quantify the evolution of both the TDD and the so-called ‘‘line’’ linear density (LLD) as a function of the H2 bake conditions. The sSi layers grown after 750 1C, 120 s H2 bakes were not revealed. Indeed, they are rough and heavily defected, with an O contamination peak at the interface with SiGe (see the previous sections). As an example, we have plotted in Fig. 9 a dark field optical microscopy image of the defects present in a 16 nm thick sSi layer grown at 700 1C with SiH2Cl2 on a Si0.73Ge0.27 VS after a {850 1C, 30 s} H2 bake. The whole sSi layer and around 5 nm of SiGe underneath were consumed during the Secco etch. The location of a threading dislocation is betrayed by a round white spot. Meanwhile, numerous elongated ‘‘lines’’ along the /1 1 0S directions can also be observed in Fig. 9. These lines are most probably the signature of SFs (i.e. {1 1 1} planes of broken or distorted bond extending through the thickness of the sSi film) or misfit dislocations (MDs) at the interface between sSi and SiGe [7–9,24–27]. It seems likely that SFs would be more deleterious to device operation than MDs [28], although the latter have been shown to act as dopant diffusion pipes in bulk nMOS transistors [29]. At least 10 such images have been acquired for each sample after Secco defect revelation in order to obtain statistically significant values for TDD and LLD. We have plotted in Fig. 10 the TDD and in Fig. 11 the LLD as a function of the H2 bake conditions, this for our 16 nm sSi layers grown at 700 1C using SiH2Cl2 on top of polished Si0.73Ge0.27 and Si0.63Ge0.37 VSs. The TDD, in-between 1.0 and 1.6  105 cm2 for sSi on Si0.73Ge0.27 and in-between 1.4 and 2.3  105 cm2 for sSi on Si0.63Ge0.37, does not seem to depend on the H2 bake thermal budget. Those values, very much in line with the ones reported in Refs. [8,9], are most likely dictated by the SiGe VSs underneath. The mean TDD associated to sSi on Si0.63Ge0.37 is slightly higher than the sSi on Si0.73Ge0.27 one (17  105 versus 1.4  105 cm2), however. This is most probably due to (i) the higher tensile strain in same thickness sSi layers in the first case than in the second one and (ii) the slight TDD increase as the Ge content in SiGe VS increases [1]. As for TDD, the LLD does not clearly depend on the H2 bake conditions. It is indeed comprised in-between 360 and 460 cm1 for sSi on Si0.73Ge0.27 and in-between 600 and 650 cm1 for sSi on Si0.63Ge0.37. The mean LLD associated to sSi on Si0.63Ge0.37 is slightly higher than the sSi on Si0.73Ge0.27 one (610 versus 405 cm1), however. Those

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Fig. 9. 130 mm  100 mm dark field optical microscopy image of the defects present in a 16 nm thick sSi layer grown at 700 1C with SiH2Cl2 on a polished Si0.73Ge0.27 VS after the Secco consumption of the whole sSi layer and around 5 nm of SiGe underneath. Lines running along the /1 1 0S directions are most probably the signature of SFs in the sSi layer (and of misfit dislocations at the interface between sSi and SiGe). Threading dislocations appear at white spots.

1000

106

sSi on Si0.6 Ge 0.4

sSi on Si0.6 Ge0.4

sSi on Si0.7 Ge 0.3

LLD (cm-1)

TDD (cm-2)

sSi on Si0.7 Ge0.3

105

Ge

100

104 800°C, 120s

850°C, 850°C, 15s 30s H2 bake conditions

850°C, 120s

800°C, 120s

850°C, 850°C, 15s 30s H2 bake conditions

850°C, 120s

Fig. 10. Threading dislocation density in 16 nm thick sSi layers grown on top of polished Si0.73Ge0.27 and Si0.63Ge0.37 VS after an ‘‘HF-last’’ wet cleaning followed by various thermal budget H2 bakes.

Fig. 11. ‘‘Lines’’ (i.e. stacking faults and misfit dislocations) linear density in 16 nm thick sSi layers grown on top of polished Si0.73Ge0.27 and Si0.63Ge0.37 VS after an ‘‘HF-last’’ wet cleaning followed by various thermal budget H2 bakes.

values are quite similar to the ones associated with sSi layers grown on various content SiGe VSs (after 850 1C, 120 s H2 bakes). We indeed showed that, for a given sSi

layer thickness, the LLD increased as the Ge content increased. For 16 nm thick sSi layers, it went from roughly 120 cm1 ([Ge] ¼ 21%) up to 460 cm1 ([Ge] ¼ 40%) [9].

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7. Comparison with literature results We have found in the literature only a few papers dealing with the properties of tensily strained Si layers grown on top of polished SiGe VSs [30–32]. The chemistries and growth temperatures called upon for sSi deposition were either SiH2Cl2 and 750 1C [31] or SiH4 and 650 1C [32]. The following conclusion was reached: in order to minimize the surface roughness of such stacks while suppressing any O and C interfacial contamination, one should adopt H2 bake temperatures as low as possible (in the 800–850 1C range). The higher the temperature, the lower the mandatory bake duration is: 800 1C, 180 s [32]3850 1C, 30 s [31]. It should however be underlined that (i) The Ge concentrations of the polished SiGe templates underneath were in-between 15% and 20% only in Refs. [30–32]. (ii) The H2 bakes were carried out at pressures higher than our 20 Torr bakes: 80 Torr in Refs. [30–31] (undisclosed in Ref. [32]). We are dealing here with higher Ge concentration SiGe VSs (either 27% or 37%), which are characterized by much rougher as-grown surfaces. This is quite important as smooth surfaces formed after CMP are metastable. They would for high thermal budget H2 bakes and thick layers grown on top come back to their rough, as-grown shapes. The other specificity of our study is that our sSi layers are much more tensily strained than those on 15–20% VS. This also impacts surface roughness. We had seen in Figs. 7 and 8 that H2 thermal budgets superior or equal to {800 1C, 120 s} yielded contaminationfree sSi/Si0.73Ge0.27 and sSi/Si0.63Ge0.37 interfaces, as on 15–20% VS. Let us now compare small-scale AFM images. The 2 mm  2 mm rms roughness associated to sSi on Si0.73Ge0.27 and to sSi on Si0.73Ge0.27 are in the 0.13–0.24 nm and in the 0.08–0.11 nm ranges, respectively (values not discussed previously). Those values are quite close to the 0.09–0.10 nm values associated to 1 mm  1 mm AFM images of 5–50 nm thick sSi layers grown on top of Si0.85Ge0.15 [31]. Values lower than 0.13–0.18 nm have been obtained by SOITEC for 20 nm thick sSi films grown on top of Si0.8Ge0.2 VS [32]. 8. Conclusion We have studied the impact of various H2 bakes (in-between 750 and 850 1C, this for durations in-between 15 and 120 s) on the structural properties of 16 nm thick sSi layers grown on top of polished Si0.7Ge0.3 and Si0.6Ge0.4 VS after an ‘‘HF-last’’ wet cleaning. SIMS has revealed the presence of a definite O contamination peak at the sSi/SiGe interface after 750 1C, 120 s H2 bakes. The resulting sSi layers were heavily defected and rough, with the presence of numerous very small hills and lines running along the /1 1 0S directions (which are most likely associated to

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emerging threading dislocations and to SFs, respectively). By contrast, temperatures superior or equal to 800 1C yielded contamination-free interfaces. No clear impact of the H2 bake temperature (X800 1C) and/or duration on the TDD and the ‘‘line’’ defect linear density (LLD) was evidenced. TDD in-between 1.0 and 2.3  105 cm2 and LLD in-between 360 and 650 cm1 were indeed associated to such stacks. Those values are most likely dictated by the SiGe VS underneath. Higher temperatures and longer bakes yielded rougher surfaces, however. The best H2 bake for the growth of sSi on polished Si0.7Ge0.3 and Si0.6Ge0.4 VSs seemed to be {850 1C, 15 s}. The sSi surfaces after such bakes are characterized by numerous very small amplitude mounds several hundreds of nm in diameter. The surface root mean square roughness was in-between 0.1 and 0.2 nm only, however (10 mm  10 mm AFM images). Light inspection was also used to characterize at the wafer scale the impact of the H2 bakes on the surface morphology (i.e. the slight re-appearance of surface cross-hatch). The normal incidence wide (DW) and narrow (DN) hazes are indeed sensitive to surface roughness with 0.3–1 and 1–3 mm spatial wavelengths, respectively. Higher values were associated to sSi layers grown on Si0.6Ge0.4 VS than on Si0.7Ge0.3 VS. This was explained in terms of a greater tendency of polished SiGe surfaces of recovering their asgrown undulating shape for higher Ge contents after high temperature, long H2 bakes. Acknowledgements This work, carried out in the NaNoTec and the Silicon Technology Platform Departments of LETI, CEA-Grenoble, was supported by the European Union MEDEA+Silonis and PullNano IST Projects. F. Gonzatti, J.-P. Colonna, L. Saidi, L. Masarotto, V. Benevent, G. Fleury, S. Rousseau, P. Roche, B. Assie and J.P. Mazzon are gratefully acknowledged for their help in operating and maintaining the Epi Centura tool. References [1] Y. Bogumilowicz, J.M. Hartmann, F. Laugier, G. Rolland, T. Billon, N. Cherkashin, A. Claverie, J. Crystal Growth 283 (2005) 346. [2] M.T. Currie, C.W. Leitz, T.A. Langdo, G. Taraschi, E.A. Fitzgerald, D.A. Antoniadis, J. Vac. Sci. Technol. B 19 (2001) 2268. [3] C.W. Leitz, M.T. Currie, M.L. Lee, Z.-Y. Cheng, D.A. Antoniadis, E.A. Fitzgerald, J. Appl. Phys. 92 (2002) 3745. [4] B. Ghyselen, J.M. Hartmann, T. Ernst, C. Aulnette, B. Osternaud, Y. Bogumilowicz, A. Abbadie, P. Besson, O. Rayssac, A. Tiberj, N. Daval, I. Cayrefourq, F. Fournel, H. Moriceau, C. Di Nardo, F. Andrieu, V. Paillard, M. Cabie´, L. Vincent, E. Snoeck, F. Cristiano, A. Rocher, A. Ponchet, A. Claverie, P. Boucaud, M.-N. Semeria, D. Bensahel, N. Kernevez, C. Mazure, Solid State Electron. 48 (2005) 1285. [5] K. Rim, K. Chan, L. Shi, J. Ott, N. Klymko, F. Cardone, L. Tai, S. Koester, M. Cobb, D. Canaperi, B. To, E. Duch, I. Babich, R. Carruthers, P. Saunders, G. Walker, Y. Zhang, M. Steen, M. Ieong, in: Proceedings of the 2003 IEDM Conference, Washington, USA, p. 49. [6] F. Andrieu, C. Dupre´, F. Rochette, O. Faynot, L. Tosti, C. Buj, E. Rouchouze, M. Casse´, B. Ghyselen, I. Cayrefourcq, L. Bre´vard, F.

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