- Email: [email protected]
SiGe-on-insulator MOSFETs
Solid-State Electronics 48 (2004) 1347–1355 www.elsevier.com/locate/sse
Simulation and modelling of transport properties in strained-Si and strained-Si/SiGe-on-insulator MOSFETs J.B. Rold an *, F. G amiz Departamento de Electronica y Tecnologıa de Computadores, Facultad de Ciencias, Universidad de Granada, Avd.Fuentenueva s/n., 18071 Granada, Spain Received 3 October 2003; received in revised form 27 November 2003; accepted 30 January 2004 Available online 13 April 2004
The review of this paper was arranged by Prof. C.K. Maiti
Abstract A comprehensive study of the transport properties of bulk and SOI strained-Si MOSFETs has been performed. The influence of the strain in the silicon layer is studied in detail, including the quantization of the inversion layer. The conductivity-effective electron mass, the inversion charge centroid and the mobility, including the most important scattering mechanisms for these devices, are simulated and modelled. Non-steady-state high-longitudinal-field transport is also dealt with from the modelling and simulation viewpoint. The main features for the performance enhancement of these devices are highlighted and design guidelines are given to take advantage of the improvements that can be achieved making use of them. 2004 Elsevier Ltd. All rights reserved. Keywords: Electron mobility; Strained-Si/SiGe MOSFETs; Inversion charge centroid; Strained-Si MOSFET mobility model; Velocity overshoot; Strained-Si/SiGe-OI MOSFETs
1. Introduction The scaling of MOSFET dimensions has pushed channel lengths to under 0.1 lm, and therefore a high doping concentration has to be used in order to limit short-channel effects. These doping profiles reduce mobility due to higher Coulomb scattering rates [1,2]. To solve these problems, the use of non-uniform doping concentrations and many other design approaches have been suggested, nevertheless the reduction of the low-field mobility is still very important. In this context, the use of strained-Si layers, where important improvements in the mobility are achieved, is very seriously considered as an alternative for conventional devices in the IC industry.
* Corresponding author. Tel.: +34-958-244071; fax: +34-958243230. E-mail addresses: [email protected] (J.B. Roldan), fgamiz@ ugr.es (F. G amiz).
The mobility improvement observed in strained-Si channel MOSFETs has been explained by means of the reduction of the carrier conductivity-effective mass and the intervalley scattering rates. This is due to the split of the sixfold degeneracy in the Si conduction band minimum, caused by the interface strain [3]. The sixfold degenerate valleys separate into two groups: two lowered valleys with a longitudinal mass axis normal to the interface and four raised valleys having a longitudinal mass axis parallel to the interface [3,4]. The mobility improvement explanation based on the split of the sixfold degeneracy of the conduction band has been done qualitatively; that is why we present here a more quantitative description of these effects in order to accurately predict the behavior of devices whose fabrication is based on strained-Si on relaxed Si1x Gex heterostructures. To achieve such a description, we have undertaken a comprehensive study on the electron transport in strained-Si channel MOSFETs in different parts: (i) The first one was the study of the inversion charge and the
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.01.016
1348
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
low-longitudinal-electric-field channel mobility (Section 3). (ii) Models of the inversion charge centroid and the mobility are developed by using the data obtained in Section 3 and some experimental data (Section 4). (iii) The difference of the relaxation times observed for different Ge mole fractions led us to study non-localtransport effects such as electron-velocity overshoot (Section 5) and the modelling of these effects (Section 6). (iv) Finally, we have simulated strained-Si/SiGe-oninsulator MOSFETs (Section 7), these devices combine the advantages of strained-Si/SiGe bulk MOSFETs and those of ultrathin fully depleted silicon-on-insulator (SOI) MOSFETs, at the same time overcoming the deficiencies they present separately [5,6]. Monte Carlo simulation was chosen because it is held to contain a more rigorous description of device physics than the models based on the solution of the fundamental balance equations [7,8].
2. Simulator description We have developed a strained-Si n-type Monte Carlo simulator by adapting a previous unstrained-Si one which includes inversion-layer quantization and a nonparabolic band model [9,10]. The electron energy for all our simulations was always under 0.5 eV, and so a nonparabolic simplified band structure can be used to accurately describe the Si band structure [8]. The quantization effects are included solving the Poisson equation coupled with the one-dimensional Schroedinger equation all along the channel. We use the procedure explained in [9] to solve the two-dimensional Poisson equation making use of the solutions of the onedimensional self-consistently solved Schroedinger and Poisson equations in different positions along the channel. In this way, we take into account short-channel effects, known to be important for submicrometer devices. The Monte Carlo simulator is coupled with the Poisson and Schroedinger equations as explained in Ref. [9]. The value of the conduction band offset for the fourfold in-plane bands over the value for the twofold out-of-plane bands was 0:67x eV, where x was the Ge mole fraction [11] and the valley shape was not modified by the strain. Phonon, surface-roughness and Coulomb scattering rates have been evaluated at each point of the channel making use of the same models, constants and band structure for our unstrained-Si MOSFET simulator as described elsewhere [9,10].
3. Inversion charge and low-field mobility simulation study In order to study the mobility, we have simulated a long-channel MOSFET for a small drain–source voltage and several gate–source voltages. The MOSFET struc-
ture was formed by a strained-silicon layer (10 nm thick) grown epitaxially on a relaxed Si1x Gex substrate. The doping profile used was reported by Iwase et al. [12] for the 0.1 lm channel length MOSFET they fabricated (oxide thickness was 4 nm). We have chosen this doping profile to ensure the results obtained in this section are coherently related to the work in later sections. The ratio between the mobility enhancement for a strained-silicon long-channel MOSFET and the mobility in an unstrained-silicon long-channel MOSFET at both T ¼ 300 and 77 K as a function of the Ge mole fraction for a EEFF ¼ 5 105 V/cm is shown in Fig. 1, where phonon and surface-roughness scattering mechanisms have been used. The mobility enhancement observed is comparable to the one obtained experimentally [13]. This improvement is noticeable at 77 and 300 K for nonzero Ge mole fractions and saturates for x ¼ 0:2 and 0.05 at room and low temperatures respectively, as can be seen in Fig. 1. This behavior can be explained by studying the evolution of the subbands population as the germanium mole fraction rises. In this respect, the population of the unprimed subbands is increased as x rises with respect to the primed subbands due to the higher separation of both subgroups of subbands produced by the strain [14]. The conductivity-effective mass of the carriers in the unprimed subbands is lower. Apart from that, the separation of both groups of subbands reduce intervalley phonon-scattering mechanisms and it is clear that the greater the separation (the strain of the silicon layer) the higher is the mobility. In order to see the reduction of the conductivity-effective mass quantitatively we show (Fig. 2) the evolution of this parameter as the germanium mole fraction rises for different temperatures and effective fields. It is important to highlight
Fig. 1. Ratio between the mobility enhancement for a strainedsilicon long-channel MOSFET and the mobility in an unstrained-silicon long-channel MOSFET at both T ¼ 300 and 77 K as a function of the Ge mole fraction for a EEFF ¼ 5 105 V/cm.
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
Fig. 2. Ratio between the average-conductivity-effective mass and the free electron mass versus Ge mole fraction x (N: T ¼ 300 K, j: T ¼ 77 K, EEFF ¼ 7:7 105 V/cm (- - -) and EEFF ¼ 5:5 105 V/cm (––)).
the saturation of the improvement which is achieved at higher germanium mole fraction at room temperature it is almost coincident to the saturation of the mobility enhancement that can be seen in Fig. 1. The high doping profiles used in short-channel MOSFETs led us to study the influence of Coulomb scattering mechanism in the low-field mobility. The MOSFET structure we have simulated in this case was formed by a strained-silicon layer (10 nm thick) grown epitaxially on a relaxed Si1x Gex substrate. The oxide thickness was considered to be 5 nm. Fig. 3 shows simulated mobility curves assuming (a) no Coulomb scattering and (b) an interface charged layer Nit ¼ 1 1011 cm2 , for strained-silicon inversion layers. We have first considered a low uniform doping concentration (NA ¼ 9 1014 cm3 ), and that the Coulomb
1349
scattering is only due to charges trapped right at the interface. As can be seen, mobility enhancement clearly decreases in the low electric field region when Coulomb scattering is taken into account. The following conclusion can be drawn from Fig. 3: For a fixed value of the transverse electric field, the greater the germanium mole fraction the greater the Coulomb limited mobility. This improvement in the Coulomb limited mobility is produced by the way the electrons are distributed in the electric subbands for different germanium mole fractions. For a fixed value of the transverse electric field, as the germanium mole fraction increases, the higher band splitting causes the ground subband population to increase, thus decreasing the number of electrons in the excited subbands. Therefore, the screening of the charged centers by the mobile carriers will be more effective, thereby reducing Coulomb scattering, and increasing the electron mobility. In the previous analysis we have considered a very low doped substrate. Nevertheless, in state-of-art technology, very high non-uniform doped substrates are used to avoid MOSFET short-channel effects. In such cases, channel impurity profiles are carefully selected to obtain higher transconductance and to prevent punchthrough. Fig. 4 shows electron mobility curves for one of these doping profiles. The simulated channel impurity profile was described in [15]. Fig. 4b shows the Coulomb mobility obtained by applying Mathiessen rule, it can be seen that Coulomb scattering is very slightly improved by the strain. Nevertheless, only at very low effective fields, where Coulomb scattering becomes the main scattering mechanism, do all the mobility curves tend to coincide, thus canceling mobility enhancement. At higher effective fields, where phonon and surfaceroughness mechanisms are more important there can be seen an improvement of the mobility curve in both cases (Figs. 3 and 4).
Fig. 3. Electron mobility (a) without Coulomb scattering and (b) including Coulomb scattering versus transverse electric field at room temperature in strained-silicon inversion layers pseudomorphically grown on Si1x Gex (––: x ¼ 0; : x ¼ 0:1; N: x ¼ 0:2; : x ¼ 0:3; j: x ¼ 0:4) (NA ¼ 9 1014 cm3 ).
1350
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
Fig. 4. Electron mobility (a) including Coulomb scattering versus transverse electric field at room temperature in strained-silicon inversion layers pseudomorphically grown on Si1x Gex for a high doped substrate. (b) Coulomb limited mobility (––: x ¼ 0; h: x ¼ 0:1; N: x ¼ 0:2; : x ¼ 0:3; j: x ¼ 0:4) (high doping profile, see [15]).
4. Modelling the low-field mobility and the inversion charge centroid
A conventional model for the surface roughness limited mobility is:
The importance of these devices in current R&D activities in the IC arena make the availability of models for device and circuit simulation essential. In this respect, we have simulated a very wide set of mobility curves changing the germanium mole fraction, doping concentrations and surface-roughness parameters in order to obtain an accurate analytical model for the mobility. The devices used in our simulations were superficial strained-Si MOSFETs, with a structure similar to the ones studied in [13,14]. In particular the ones simulated here presented the following technological features: NA ¼ 5 1017 cm3 , Tox ¼ 8 nm, TW ¼ 10 nm (strained-silicon layer thickness), and a germanium mole fraction ranging from x ¼ 0 to 0.4. The mobility model used was separated in the three main components of the mobility in MOSFETs devices as follows:
lsr ¼
1 1 1 1 ¼ þ þ lTOTAL lsr lph lC
dðxÞ1014 2 EEFF
ð5Þ
The Coulomb mobility is calculated as follows: l1 C ¼ C
NA NS
ð6Þ
For a deeper explanation of the model see [16]. Finally, we have plotted (Fig. 5) several experimental mobility curves as well as analytical curves obtained with our model. The data reported by Welser et al. [17], Rim et al. [18] and Currie et al. [19] are shown in symbols. As can be seen, our model (solid lines) fits well Rim’s curves. The parameters used were (ab ¼ 11, bb ¼ 15, aa ¼ 3, ba ¼ 25) for the phonon component and (ad ¼ 28, bd ¼ 3, Dd ¼ 5:75, d0 ¼ 5:8) for the surfaceroughness component of the mobility. As can be ob1000
ð1Þ
x=0.2
T=300K
where phonon mobility is calculated as, " 0:2aðxÞ # 1 1 EEFF 1þ ¼ E0 lph lphB ð300 KÞbðxÞ
ð2Þ
where, bðxÞ ¼ 1þ
aðxÞ ¼
ab x þ1 a x bb b1b
ð3Þ
b
800
x=0.1
x=0.29
x=0.30
Currie
x=0.2
600
x=0
x=0.1 x=0.2
400
Rim Welser
x=0 x=0
Analytical model
200
6
5
1x10
1x10
2:7
aa x þ1 a x ba b1a a 1þ 0:9
Mobility (cm2 /Vs)
x=0.15
Effective Field (V/cm)
ð4Þ
Fig. 5. Electron mobility versus effective field for strained-Si on Si1x Gex MOSFETs at room temperature. Analytical model results are shown in lines. Data reported by Welser et al. (h), Rim et al. ( ) and Currie et al. (–H–).
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
served, this group of parameters needs to be fitted for each different technology in order to describe the high effective field component of the mobility (the surfaceroughness component) dependent on the quality of the insulator interface. The C parameter of Eq. (6) used here is 45.45 · 109 V s/cm. It is very important to highlight that we have not seen lC dependencies on the germanium mole fraction. This fact is in agreement with the results obtained by MC simulations in the previous sections. For the development of the inversion charge centroid model we have used again our simulator and the structures used previously. A Nþ POLY gate was used in these cases. The model presented here can be considered as an extension of a previously introduced one [20]. The particular features of strained-Si on SiGe MOSFETs are included in this new version of the model. Taking this fact into consideration, we regard the latter model [20] as our starting point, Eq. (1). 1=2 rffiffiffiffiffiffiffi 1=3 MV QD QD 1 QI zI ¼ zI0 1 þ ð7Þ cm eSi eSi 2 eSi where eSi is the silicon permittivity, QD and QI are the depletion and inversion charges respectively and zI0 is a fitting parameter which provided a good agreement in conventional Si MOSFETs for a value of 1.2 nm and for the doping concentration range we are dealing with [20]. It is interesting to take into consideration the particular technological features of strained-Si devices in relation to the germanium mole fraction (x) and to the width of the strained-Si layer (TW , the values of this parameter used in this paper are lower than those needed for the strain to accommodate the lattice mismatch). To do so, we analytically solved the one-dimensional Poisson equation in these devices in the direction perpendicular to the Si–SiO2 interface. We obtained the electric
1351
field and the potential both in the strained-Si and the SiGe alloy layers. The width of the depletion charge layer is given by the following expression: sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi a 2 a wdep kT =q a WDPL ¼ TW þ TW TW2 þ 2 ð8Þ b b b b where a and b are constant parameters for a constant doping profile NA a eSiGe ¼1 ; b eSi
b¼
qNA eSiGe
ð9Þ
eSiGe is the SiGe permittivity (which depends on x) and wdep is defined following Ref. [20] as wdep ¼ wS
1 zI Q I eSi
ð10Þ
where wS is the surface potential. We can make use of the magnitudes described so far zI in strained-Si MOSFETs; to do so we employ Eq. (1) where a new parameter zI0 has been introduced. x ; zI0 ¼ 1:2 nm 1 b NA ðcm3 Þ b ¼ 1:5 þ 0:22 1 1017 17 10 TW ðnmÞ 5 ð11Þ þ 12:5 NA This expression accurately reproduces the simulation results for a wide range of germanium mole fractions (x ¼ 0 to 0.4, the usual experimental values of the SiGe alloys) and TW values (TW ¼ 5–30 nm). The results obtained with the simulator (solid lines) and with our model (symbols) are shown in Fig. 6, both for the inversion charge centroid and the inversion charge calculated by using the model. The reproduction
2.5 14
x=0.3 TW=5 nm
18
1.5
1.0
-3
NA=10 cm
8 6
17
NA=10
-3
cm
4
18
-3
NA=3x10 cm
2 T=300 K
0.1
(a)
10
12
z I (nm)
2.0
T=300 K x=0.3 TW=5 nm
12
-2
-3
NINV (x10 cm )
17
NA=10 cm
18
-3
NA=3x10 cm
1 12 -2 N inv (x10 cm )
18
0
N A=10
1
10
(b)
2
-3
cm
3
4
5
6
VG (V)
Fig. 6. (a) Inversion charge centroid versus inversion charge for strained-Si on Si0:7 Ge0:3 MOSFETs at room temperature. (b) Inversion charge versus gate voltage for strained-Si on Si0:7 Ge0:3 MOSFETs for different doping concentrations at room temperature. TW ¼ 5 nm. The results obtained with the simulator are shown in solid lines and the data calculated with our model in Tox ¼ 50 A, symbols.
1352
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
of the simulation results is good for the following germanium mole fractions (x ¼ 0 to 0.4), doping concentrations (NA ¼ 1017 –3 · 1018 cm3 ), and strained-Si layer widths (TW ¼ 5–30 nm). There is a maximum error of 10– 15% in all cases. 5. Velocity overshoot effects simulation study One of the most important MOSFET figures of merit when dealing with current integrated circuits is transconductance. MOSFET transconductance and drain current are both affected by electron-velocity overshoot (VO) effects in very short-channel MOSFETs. We have shown in previous papers that strained-Si devices are subject of important VO effects [14]. We have studied velocity overshoot effects by applying a sudden longitudinal-electric field of 2 · 105 V/cm to a steady-state electron distribution achieved under the influence of a longitudinal-electric field of 1 · 104 V/cm. The transverse-electric field chosen was the same one used in other simulations, 7.7 · 105 V/cm. The time evolution of the electron velocity is shown in Fig. 7. It is clear that the time taken to reach the steady-state velocity corresponding to a longitudinal-electric field of 2 · 105 V/cm increases as x rises. The electron-velocity increase caused by the high-longitudinal-field gradient found at the source of short-channel MOSFETs makes the drain current and the transconductance higher than in cases where these overshoot effects do not exist in this edge of the channel. The inversion charge and electron velocity at the source fix the drain current value, which is constant throughout the channel. The velocity increase as electrons go toward the drain is accompanied by a reduction of the inversion charge in order to keep their product constant and equal to the drain current all along the channel.
Fig. 7. Transient overshoot velocity with a sudden application of the field 2 · 105 V/cm at room and low temperature for EEFF ¼ 7:7 105 V/cm. Unstrained-silicon (––), x ¼ 0:2 (- - -), x ¼ 0:4 (– – –).
We have simulated several 0.1 lm channel length MOSFETs for x ¼ 0, 0.1, 0.2 and 0.3 using our Monte Carlo simulator. The doping profile was as reported previously, oxide thickness was 4 nm, and the source and drain junction depths were xj ¼ 100 nm. The MOSFET external bias was VDS ¼ 0:5 V, VGS ¼ 1:3 V, and VSB ¼ 0 V. The inhomogeneous steady-state velocity distribution along the channel obtained for each Ge mole fraction is plotted in Fig. 8 at room temperature. The electron velocity is higher than the saturation velocity (which has been shown to be the same for all x [14]) for strained and unstrained-Si channel MOSFETs near the drain edge. This effect is due to the highlongitudinal-electric-field gradient the carriers face as they travel toward the drain. This gradient makes the electrons overshoot the velocity they would have if they were subject to homogeneous steady-state transport (long channels). In order to estimate what the homogeneous steady-state electron velocity would be, we have plotted the velocity obtained by means of Thornber’s expression [21] using the low-longitudinal-field-mobility curve and the longitudinal-field distribution obtained along the channel for x ¼ 0 (dotted line) and x ¼ 0:1 (solid line) in our Monte Carlo simulation. It is always below the saturation velocity limit, as expected. The homogeneous steady-state electron velocity is slightly lower than the inhomogeneous steady-state electron velocity even at the source edge. This is produced by the high-longitudinal-electric-field step the electrons face as they enter the channel. It can be seen that the velocity values obtained for strained-Si devices are higher than the unstrained-Si
Fig. 8. Electron velocity versus channel position at T ¼ 300 K. Velocity distribution obtained in an 0.1 lm MOSFET with VGS ¼ 1:3 V and VDS ¼ 0:5 V for x ¼ 0 (j), x ¼ 0:1 ( ), x ¼ 0:2 (N), x ¼ 0:3 (H). Low-longitudinal-electric-field velocity corrected using Thornber’s expression and the longitudinal-field distribution obtained for the previous MOSFET with x ¼ 0 ( ) and x ¼ 0:1 (––).
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
1353
devices at the source side. The results are in agreement with the simulations performed by Bufler and Fichtner [22] and Jungemann and Meinerzhagen [23]. This fact is directly connected with the increase of drain current at high drain voltages in strained-Si devices as pointed out by [22–24].
6. Modelling velocity overshoot effects In order to model VO effects, taking into consideration their importance in these devices we have simulated several 0.1 lm channel length strained-Si MOSFETs for x ¼ 0, 0.1, 0.2, 0.3 and 0.4. The doping profile used was the one reported later [12]. The oxide thickness was 4 nm, and the source and drain junction depths were xj ¼ 100 nm. The MOSFET external bias was VDS ¼ 0:5 V, VGS ¼ 1:3 V, and VSB ¼ 0 V. The drift electron-velocity profiles along the channel for each Ge mole fraction were fitted using Eq. (12). The low-field mobility curves for each MOSFET and the longitudinalelectric field distribution were obtained using the Monte Carlo calculation for these transistors following the procedure explained in Refs. [9,25]: lðEk ; EEFF Þ ¼ 1þ
l0 ðEEFF Þ 1 oEk þk bðEk Þ bðE1k Þ E k ox l ðE ÞxE 0
EFF
k
vsat
ð12Þ l0 being the low-field mobility, Ek the longitudinalelectric field (along the channel), and EEFF the transverse-electric field (perpendicular to the silicon–SiO2 interface). vsat ¼ 1:1 107 cm/s for all x used here [14] and bðEk Þ ¼ 3 0:31 logðEk Þ [9]. We have obtained the k parameter for different x and temperatures (Fig. 9). It can be observed that parameter k increases as x rises; therefore the electron-velocity overshoot effects (contained in the second term on the right-hand side of expression (12)) show the same trend. This fact is mainly due to the reduction of the intervalley scattering (connected with the split of the sixfold degeneracy in the Si conduction band minimum) responsible for the energy relaxation in the high-longitudinal-electric-field transport regime [14]. As can be observed, the k parameter shows an almost linear dependence on x at both temperatures. We have obtained an empirical analytical expression for k as a function of temperature and x (Ge mole fraction) (Eq. (13)): kðxÞ ðbðT Þ þ 100xÞ105 cm3 =V s
ð13Þ
where bðT Þ is a constant that depends on the temperature: bð300 KÞ ¼ 4 and bð77 KÞ ¼ 6:4.
Fig. 9. Parameter k versus Ge mole fraction used in expression (12) to take into account electron-velocity overshoot effects in strained-Si on Six Ge1x channel MOSFETs at T ¼ 300 and 77 K. More details in [25].
7. Strained-Si/SiGe-on-insulator MOSFETs These new devices based on strained-Si layers and SOI structures are motivated by recent studies that have shown the feasibility of strained-Si/SiGe-on-insulator (SiGe-OI) structures. Such studies have obtained highquality crystalline relaxed SiGe layers with a thickness of less than 10 nm on SiO2 substrates by separation-byimplanted-oxygen techniques [26,27] or by solid-phase epitaxy. Using these structures as a starting point, and growing a thin strained-silicon layer on the relaxed SiGe-OI substrate, both n- and p-channel strained-Si/ SiGe-OI MOSFETs have been fabricated and successfully operated, showing high electron and hole mobilities with a germanium mole fraction as low as 0.1. These strained-Si/SiGe-OI structures combine the advantages of strained-Si/SiGe bulk MOSFETs and those of ultrathin fully depleted silicon-on-insulator. We have used our simulator to study the mobility curves of one of these structures [28] and the mobility curves obtained are shown in Fig. 10. Where we have assume that the semiconductor layer between the two oxides is TW ¼ 10 nm, and take into account different values of the strained-Si layer TSi subjected to the two following constraints: (i) TW ¼ TSiGe þ TSi , and (ii) TSi < TSiGe (where TSiGe is the SiGe layer thickness). The germanium mole fraction has been taken as x ¼ 0:3. In Fig. 10, bold circles correspond to TSi ¼ TSiGe ¼ 5 nm, and bold squares correspond to TSi ¼ 2:5 nm and TSiGe ¼ 7:5 nm. For the sake of comparison, we have also shown mobility curves corresponding to strained-Si/ SiGe bulk MOSFETs (no buried oxide) with the same
1354
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
them a serious alternative to conventional devices in the ultrahigh scale integration landscape.
Electron Mobility (cm 2/Vs)
2000
SiGe-OI Tw=10nm Bulk SiGe 1600
Acknowledgements
x=0.3 1200
This study was carried out in the framework of Research Project TIC2001-3243 supported by the Spanish Government (MCYT and FEDER).
800
400
References
TSi=2.5nm TSi=5.0nm 0
5
10
10
6
Effective Field (V/cm) Fig. 10. Electron mobility curves versus the transverse effective field for a strained-Si/SiGe-OI MOSFET at room temperature for different values of TSi (TW ¼ TSi þ TSiGe ¼ 10 nm, x ¼ 0:3).
TSi (open symbols) and mobility curves corresponding to unstrained MOSFETs: the solid line represents an unstrained bulk MOSFET (conventional MOSFET); while the dashed line represents an unstrained SOI-MOSFET (conventional SOI-MOSFET) with a silicon thickness of TW ¼ TSi ¼ 10 nm. As can be seen, in the strained case, there is an important increase in the electron mobility compared to the unstrained case, as experimentally observed, due to the reasons explained at the beginning of the paper. The mobility curves corresponding to strained-Si/SiGe-OI MOSFETs are slightly lower than those corresponding to strained-Si/SiGe bulk MOSFETs especially at low transverse effective fields. This is due to the greater phonon-scattering rate in the SiGe case, arising from the greater confinement of the carriers due to the well formed by the two oxides (TW ).
8. Conclusions A comprehensive study of the transport properties of bulk and SOI strained-Si MOSFETs has been performed. Different models for the low-field mobility, the inversion charge centroid and the velocity overshoot effects are introduced. The role that non-local effects, such as velocity overshoot, play in very short transistors is deeply analyzed. The advantages of the newly introduced strained-Si/SiGe-on-insulator (SiGe-OI) structures are described in the last section and the results are in the line of the previous sections where it is clearly stated that the advantages of strained-Si devices make
[1] Gamiz F, L opez-Villanueva JA, Banqueri J, Carceller JE, Cartujo P. IEEE Trans Electron Dev 1995;ED-42:258. [2] Takagi S, Iwase M, Toriumi A. IEEE Tech Digest 1988: 398. [3] Abstreiter G, Brugger H, Wolf T, Jorke H, Herztog HJ. Phys Rev Lett 1985;54:2441. [4] People R. IEEE J Quantum Electron 1985;22:1696. [5] Gamiz F, Fischetti MV. J Appl Phys 2001;89:5478. [6] Chau R, Kavalieros J, Roberds B, Murthy A, Doyle B, Barlage B, et al. Tech Digest––Int Electron Dev Meet 2001; 2001:621. [7] Baccarani G, Wordeman MR. Solid-State Electron 1985; 28:407. [8] Laux SE, Fischetti MV. IEEE Electron Dev Lett 1988; 9:467. [9] Roldan JB, Gamiz F, L opez-Villanueva JA, Carceller JE. Semicond Sci Technol 1997;12:321–30. [10] Gamiz F, L opez-Villanueva JA, Banqueri J, Carceller JE, Cartujo P. IEEE Trans Electron Dev 1995;ED-42:258. [11] Vogelsang T, Hofmann KR. Appl Phys Lett 1993;63(2): 186–8. [12] Iwase M, Mizuno T, Takahashi M, Niiyama H, Fukumoto M, Ishida K, et al. IEEE Electron Dev Lett 1993;14:51. [13] Welser J, Hoyt JL, Gibbons JF. Electron mobility enhancement in strained-Si n-type metal-oxide semiconductor field-effect transistors. IEEE Electron Dev Lett 1994; 15(3):100–2. [14] Roldan JB, Gamiz F, L opez-Villanueva JA, Carceller JE. J Appl Phys 1996;80:5121. [15] Gamiz F, Roldan JB, L opez-Villanueva JA, Cartujo P. Appl Phys Lett 1996;69:797–9. [16] Roldan JB, Gamiz F, Cartujo-Cassinello P, Cartujo P, Carceller JE, Roldan A. IEEE Trans Electron Dev 2003; ED-50:1408. [17] Welser J, Hoyt JL, Takagi S, Gibbons JF. IEDM 1994; 94:373–6. [18] Rim K, Koester S, Hargrove M, Chu J, Mooney PM, Ott J. In: 2001 Symposium on VLSI Technology Digest of Technical Papers, 2001. p. 59–60. [19] Currie MT, Leitz CW, Langdo TA, Taraschi G, Fitzgerad A, Antoniadis DA. J Vac Sci, Technol B 2001;19(6): 2268. [20] Lopez-Villanueva JA, Cartulo-Cassinello P, Banqueri J, Gamiz F, Rodrıquez S. IEEE Trans Electron Dev 1997; ED-44:1915. [21] Thornber KK. J Appl Phys 1980;51:2127.
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355 [22] Bufler FM, Fichtner W. IEEE Trans Electron Dev 2003; ED-50(2):278. [23] Jungemann C, Meinerzhagen B. Proc ESSDERC 2003;33:9. [24] Lundstrom M. IEEE Electron Dev Lett 2001;ED-22:293. [25] Rold an JB, G amiz F, L opez-Villanueva JA, Carceller JE. IEEE Trans Electron Dev 1998;ED-45:993.
1355
[26] Ishikawa Y, Shibata N, Fukatsu S. Appl Phys Lett 1999; 75:983. [27] Mizuno T, Sugiyama N, Tezuka T, Takagi S. IEEE Trans Electron Dev 2002;49:7. [28] Gamiz F, Roldan JB, Godoy A. Appl Phys Lett 2002; 80:4160.
Simulation and modelling of transport properties in strained-Si and strained-Si/SiGe-on-insulator MOSFETs J.B. Rold an *, F. G amiz Departamento de Electronica y Tecnologıa de Computadores, Facultad de Ciencias, Universidad de Granada, Avd.Fuentenueva s/n., 18071 Granada, Spain Received 3 October 2003; received in revised form 27 November 2003; accepted 30 January 2004 Available online 13 April 2004
The review of this paper was arranged by Prof. C.K. Maiti
Abstract A comprehensive study of the transport properties of bulk and SOI strained-Si MOSFETs has been performed. The influence of the strain in the silicon layer is studied in detail, including the quantization of the inversion layer. The conductivity-effective electron mass, the inversion charge centroid and the mobility, including the most important scattering mechanisms for these devices, are simulated and modelled. Non-steady-state high-longitudinal-field transport is also dealt with from the modelling and simulation viewpoint. The main features for the performance enhancement of these devices are highlighted and design guidelines are given to take advantage of the improvements that can be achieved making use of them. 2004 Elsevier Ltd. All rights reserved. Keywords: Electron mobility; Strained-Si/SiGe MOSFETs; Inversion charge centroid; Strained-Si MOSFET mobility model; Velocity overshoot; Strained-Si/SiGe-OI MOSFETs
1. Introduction The scaling of MOSFET dimensions has pushed channel lengths to under 0.1 lm, and therefore a high doping concentration has to be used in order to limit short-channel effects. These doping profiles reduce mobility due to higher Coulomb scattering rates [1,2]. To solve these problems, the use of non-uniform doping concentrations and many other design approaches have been suggested, nevertheless the reduction of the low-field mobility is still very important. In this context, the use of strained-Si layers, where important improvements in the mobility are achieved, is very seriously considered as an alternative for conventional devices in the IC industry.
* Corresponding author. Tel.: +34-958-244071; fax: +34-958243230. E-mail addresses: [email protected] (J.B. Roldan), fgamiz@ ugr.es (F. G amiz).
The mobility improvement observed in strained-Si channel MOSFETs has been explained by means of the reduction of the carrier conductivity-effective mass and the intervalley scattering rates. This is due to the split of the sixfold degeneracy in the Si conduction band minimum, caused by the interface strain [3]. The sixfold degenerate valleys separate into two groups: two lowered valleys with a longitudinal mass axis normal to the interface and four raised valleys having a longitudinal mass axis parallel to the interface [3,4]. The mobility improvement explanation based on the split of the sixfold degeneracy of the conduction band has been done qualitatively; that is why we present here a more quantitative description of these effects in order to accurately predict the behavior of devices whose fabrication is based on strained-Si on relaxed Si1x Gex heterostructures. To achieve such a description, we have undertaken a comprehensive study on the electron transport in strained-Si channel MOSFETs in different parts: (i) The first one was the study of the inversion charge and the
0038-1101/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2004.01.016
1348
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
low-longitudinal-electric-field channel mobility (Section 3). (ii) Models of the inversion charge centroid and the mobility are developed by using the data obtained in Section 3 and some experimental data (Section 4). (iii) The difference of the relaxation times observed for different Ge mole fractions led us to study non-localtransport effects such as electron-velocity overshoot (Section 5) and the modelling of these effects (Section 6). (iv) Finally, we have simulated strained-Si/SiGe-oninsulator MOSFETs (Section 7), these devices combine the advantages of strained-Si/SiGe bulk MOSFETs and those of ultrathin fully depleted silicon-on-insulator (SOI) MOSFETs, at the same time overcoming the deficiencies they present separately [5,6]. Monte Carlo simulation was chosen because it is held to contain a more rigorous description of device physics than the models based on the solution of the fundamental balance equations [7,8].
2. Simulator description We have developed a strained-Si n-type Monte Carlo simulator by adapting a previous unstrained-Si one which includes inversion-layer quantization and a nonparabolic band model [9,10]. The electron energy for all our simulations was always under 0.5 eV, and so a nonparabolic simplified band structure can be used to accurately describe the Si band structure [8]. The quantization effects are included solving the Poisson equation coupled with the one-dimensional Schroedinger equation all along the channel. We use the procedure explained in [9] to solve the two-dimensional Poisson equation making use of the solutions of the onedimensional self-consistently solved Schroedinger and Poisson equations in different positions along the channel. In this way, we take into account short-channel effects, known to be important for submicrometer devices. The Monte Carlo simulator is coupled with the Poisson and Schroedinger equations as explained in Ref. [9]. The value of the conduction band offset for the fourfold in-plane bands over the value for the twofold out-of-plane bands was 0:67x eV, where x was the Ge mole fraction [11] and the valley shape was not modified by the strain. Phonon, surface-roughness and Coulomb scattering rates have been evaluated at each point of the channel making use of the same models, constants and band structure for our unstrained-Si MOSFET simulator as described elsewhere [9,10].
3. Inversion charge and low-field mobility simulation study In order to study the mobility, we have simulated a long-channel MOSFET for a small drain–source voltage and several gate–source voltages. The MOSFET struc-
ture was formed by a strained-silicon layer (10 nm thick) grown epitaxially on a relaxed Si1x Gex substrate. The doping profile used was reported by Iwase et al. [12] for the 0.1 lm channel length MOSFET they fabricated (oxide thickness was 4 nm). We have chosen this doping profile to ensure the results obtained in this section are coherently related to the work in later sections. The ratio between the mobility enhancement for a strained-silicon long-channel MOSFET and the mobility in an unstrained-silicon long-channel MOSFET at both T ¼ 300 and 77 K as a function of the Ge mole fraction for a EEFF ¼ 5 105 V/cm is shown in Fig. 1, where phonon and surface-roughness scattering mechanisms have been used. The mobility enhancement observed is comparable to the one obtained experimentally [13]. This improvement is noticeable at 77 and 300 K for nonzero Ge mole fractions and saturates for x ¼ 0:2 and 0.05 at room and low temperatures respectively, as can be seen in Fig. 1. This behavior can be explained by studying the evolution of the subbands population as the germanium mole fraction rises. In this respect, the population of the unprimed subbands is increased as x rises with respect to the primed subbands due to the higher separation of both subgroups of subbands produced by the strain [14]. The conductivity-effective mass of the carriers in the unprimed subbands is lower. Apart from that, the separation of both groups of subbands reduce intervalley phonon-scattering mechanisms and it is clear that the greater the separation (the strain of the silicon layer) the higher is the mobility. In order to see the reduction of the conductivity-effective mass quantitatively we show (Fig. 2) the evolution of this parameter as the germanium mole fraction rises for different temperatures and effective fields. It is important to highlight
Fig. 1. Ratio between the mobility enhancement for a strainedsilicon long-channel MOSFET and the mobility in an unstrained-silicon long-channel MOSFET at both T ¼ 300 and 77 K as a function of the Ge mole fraction for a EEFF ¼ 5 105 V/cm.
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
Fig. 2. Ratio between the average-conductivity-effective mass and the free electron mass versus Ge mole fraction x (N: T ¼ 300 K, j: T ¼ 77 K, EEFF ¼ 7:7 105 V/cm (- - -) and EEFF ¼ 5:5 105 V/cm (––)).
the saturation of the improvement which is achieved at higher germanium mole fraction at room temperature it is almost coincident to the saturation of the mobility enhancement that can be seen in Fig. 1. The high doping profiles used in short-channel MOSFETs led us to study the influence of Coulomb scattering mechanism in the low-field mobility. The MOSFET structure we have simulated in this case was formed by a strained-silicon layer (10 nm thick) grown epitaxially on a relaxed Si1x Gex substrate. The oxide thickness was considered to be 5 nm. Fig. 3 shows simulated mobility curves assuming (a) no Coulomb scattering and (b) an interface charged layer Nit ¼ 1 1011 cm2 , for strained-silicon inversion layers. We have first considered a low uniform doping concentration (NA ¼ 9 1014 cm3 ), and that the Coulomb
1349
scattering is only due to charges trapped right at the interface. As can be seen, mobility enhancement clearly decreases in the low electric field region when Coulomb scattering is taken into account. The following conclusion can be drawn from Fig. 3: For a fixed value of the transverse electric field, the greater the germanium mole fraction the greater the Coulomb limited mobility. This improvement in the Coulomb limited mobility is produced by the way the electrons are distributed in the electric subbands for different germanium mole fractions. For a fixed value of the transverse electric field, as the germanium mole fraction increases, the higher band splitting causes the ground subband population to increase, thus decreasing the number of electrons in the excited subbands. Therefore, the screening of the charged centers by the mobile carriers will be more effective, thereby reducing Coulomb scattering, and increasing the electron mobility. In the previous analysis we have considered a very low doped substrate. Nevertheless, in state-of-art technology, very high non-uniform doped substrates are used to avoid MOSFET short-channel effects. In such cases, channel impurity profiles are carefully selected to obtain higher transconductance and to prevent punchthrough. Fig. 4 shows electron mobility curves for one of these doping profiles. The simulated channel impurity profile was described in [15]. Fig. 4b shows the Coulomb mobility obtained by applying Mathiessen rule, it can be seen that Coulomb scattering is very slightly improved by the strain. Nevertheless, only at very low effective fields, where Coulomb scattering becomes the main scattering mechanism, do all the mobility curves tend to coincide, thus canceling mobility enhancement. At higher effective fields, where phonon and surfaceroughness mechanisms are more important there can be seen an improvement of the mobility curve in both cases (Figs. 3 and 4).
Fig. 3. Electron mobility (a) without Coulomb scattering and (b) including Coulomb scattering versus transverse electric field at room temperature in strained-silicon inversion layers pseudomorphically grown on Si1x Gex (––: x ¼ 0; : x ¼ 0:1; N: x ¼ 0:2; : x ¼ 0:3; j: x ¼ 0:4) (NA ¼ 9 1014 cm3 ).
1350
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
Fig. 4. Electron mobility (a) including Coulomb scattering versus transverse electric field at room temperature in strained-silicon inversion layers pseudomorphically grown on Si1x Gex for a high doped substrate. (b) Coulomb limited mobility (––: x ¼ 0; h: x ¼ 0:1; N: x ¼ 0:2; : x ¼ 0:3; j: x ¼ 0:4) (high doping profile, see [15]).
4. Modelling the low-field mobility and the inversion charge centroid
A conventional model for the surface roughness limited mobility is:
The importance of these devices in current R&D activities in the IC arena make the availability of models for device and circuit simulation essential. In this respect, we have simulated a very wide set of mobility curves changing the germanium mole fraction, doping concentrations and surface-roughness parameters in order to obtain an accurate analytical model for the mobility. The devices used in our simulations were superficial strained-Si MOSFETs, with a structure similar to the ones studied in [13,14]. In particular the ones simulated here presented the following technological features: NA ¼ 5 1017 cm3 , Tox ¼ 8 nm, TW ¼ 10 nm (strained-silicon layer thickness), and a germanium mole fraction ranging from x ¼ 0 to 0.4. The mobility model used was separated in the three main components of the mobility in MOSFETs devices as follows:
lsr ¼
1 1 1 1 ¼ þ þ lTOTAL lsr lph lC
dðxÞ1014 2 EEFF
ð5Þ
The Coulomb mobility is calculated as follows: l1 C ¼ C
NA NS
ð6Þ
For a deeper explanation of the model see [16]. Finally, we have plotted (Fig. 5) several experimental mobility curves as well as analytical curves obtained with our model. The data reported by Welser et al. [17], Rim et al. [18] and Currie et al. [19] are shown in symbols. As can be seen, our model (solid lines) fits well Rim’s curves. The parameters used were (ab ¼ 11, bb ¼ 15, aa ¼ 3, ba ¼ 25) for the phonon component and (ad ¼ 28, bd ¼ 3, Dd ¼ 5:75, d0 ¼ 5:8) for the surfaceroughness component of the mobility. As can be ob1000
ð1Þ
x=0.2
T=300K
where phonon mobility is calculated as, " 0:2aðxÞ # 1 1 EEFF 1þ ¼ E0 lph lphB ð300 KÞbðxÞ
ð2Þ
where, bðxÞ ¼ 1þ
aðxÞ ¼
ab x þ1 a x bb b1b
ð3Þ
b
800
x=0.1
x=0.29
x=0.30
Currie
x=0.2
600
x=0
x=0.1 x=0.2
400
Rim Welser
x=0 x=0
Analytical model
200
6
5
1x10
1x10
2:7
aa x þ1 a x ba b1a a 1þ 0:9
Mobility (cm2 /Vs)
x=0.15
Effective Field (V/cm)
ð4Þ
Fig. 5. Electron mobility versus effective field for strained-Si on Si1x Gex MOSFETs at room temperature. Analytical model results are shown in lines. Data reported by Welser et al. (h), Rim et al. ( ) and Currie et al. (–H–).
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
served, this group of parameters needs to be fitted for each different technology in order to describe the high effective field component of the mobility (the surfaceroughness component) dependent on the quality of the insulator interface. The C parameter of Eq. (6) used here is 45.45 · 109 V s/cm. It is very important to highlight that we have not seen lC dependencies on the germanium mole fraction. This fact is in agreement with the results obtained by MC simulations in the previous sections. For the development of the inversion charge centroid model we have used again our simulator and the structures used previously. A Nþ POLY gate was used in these cases. The model presented here can be considered as an extension of a previously introduced one [20]. The particular features of strained-Si on SiGe MOSFETs are included in this new version of the model. Taking this fact into consideration, we regard the latter model [20] as our starting point, Eq. (1). 1=2 rffiffiffiffiffiffiffi 1=3 MV QD QD 1 QI zI ¼ zI0 1 þ ð7Þ cm eSi eSi 2 eSi where eSi is the silicon permittivity, QD and QI are the depletion and inversion charges respectively and zI0 is a fitting parameter which provided a good agreement in conventional Si MOSFETs for a value of 1.2 nm and for the doping concentration range we are dealing with [20]. It is interesting to take into consideration the particular technological features of strained-Si devices in relation to the germanium mole fraction (x) and to the width of the strained-Si layer (TW , the values of this parameter used in this paper are lower than those needed for the strain to accommodate the lattice mismatch). To do so, we analytically solved the one-dimensional Poisson equation in these devices in the direction perpendicular to the Si–SiO2 interface. We obtained the electric
1351
field and the potential both in the strained-Si and the SiGe alloy layers. The width of the depletion charge layer is given by the following expression: sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi a 2 a wdep kT =q a WDPL ¼ TW þ TW TW2 þ 2 ð8Þ b b b b where a and b are constant parameters for a constant doping profile NA a eSiGe ¼1 ; b eSi
b¼
qNA eSiGe
ð9Þ
eSiGe is the SiGe permittivity (which depends on x) and wdep is defined following Ref. [20] as wdep ¼ wS
1 zI Q I eSi
ð10Þ
where wS is the surface potential. We can make use of the magnitudes described so far zI in strained-Si MOSFETs; to do so we employ Eq. (1) where a new parameter zI0 has been introduced. x ; zI0 ¼ 1:2 nm 1 b NA ðcm3 Þ b ¼ 1:5 þ 0:22 1 1017 17 10 TW ðnmÞ 5 ð11Þ þ 12:5 NA This expression accurately reproduces the simulation results for a wide range of germanium mole fractions (x ¼ 0 to 0.4, the usual experimental values of the SiGe alloys) and TW values (TW ¼ 5–30 nm). The results obtained with the simulator (solid lines) and with our model (symbols) are shown in Fig. 6, both for the inversion charge centroid and the inversion charge calculated by using the model. The reproduction
2.5 14
x=0.3 TW=5 nm
18
1.5
1.0
-3
NA=10 cm
8 6
17
NA=10
-3
cm
4
18
-3
NA=3x10 cm
2 T=300 K
0.1
(a)
10
12
z I (nm)
2.0
T=300 K x=0.3 TW=5 nm
12
-2
-3
NINV (x10 cm )
17
NA=10 cm
18
-3
NA=3x10 cm
1 12 -2 N inv (x10 cm )
18
0
N A=10
1
10
(b)
2
-3
cm
3
4
5
6
VG (V)
Fig. 6. (a) Inversion charge centroid versus inversion charge for strained-Si on Si0:7 Ge0:3 MOSFETs at room temperature. (b) Inversion charge versus gate voltage for strained-Si on Si0:7 Ge0:3 MOSFETs for different doping concentrations at room temperature. TW ¼ 5 nm. The results obtained with the simulator are shown in solid lines and the data calculated with our model in Tox ¼ 50 A, symbols.
1352
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
of the simulation results is good for the following germanium mole fractions (x ¼ 0 to 0.4), doping concentrations (NA ¼ 1017 –3 · 1018 cm3 ), and strained-Si layer widths (TW ¼ 5–30 nm). There is a maximum error of 10– 15% in all cases. 5. Velocity overshoot effects simulation study One of the most important MOSFET figures of merit when dealing with current integrated circuits is transconductance. MOSFET transconductance and drain current are both affected by electron-velocity overshoot (VO) effects in very short-channel MOSFETs. We have shown in previous papers that strained-Si devices are subject of important VO effects [14]. We have studied velocity overshoot effects by applying a sudden longitudinal-electric field of 2 · 105 V/cm to a steady-state electron distribution achieved under the influence of a longitudinal-electric field of 1 · 104 V/cm. The transverse-electric field chosen was the same one used in other simulations, 7.7 · 105 V/cm. The time evolution of the electron velocity is shown in Fig. 7. It is clear that the time taken to reach the steady-state velocity corresponding to a longitudinal-electric field of 2 · 105 V/cm increases as x rises. The electron-velocity increase caused by the high-longitudinal-field gradient found at the source of short-channel MOSFETs makes the drain current and the transconductance higher than in cases where these overshoot effects do not exist in this edge of the channel. The inversion charge and electron velocity at the source fix the drain current value, which is constant throughout the channel. The velocity increase as electrons go toward the drain is accompanied by a reduction of the inversion charge in order to keep their product constant and equal to the drain current all along the channel.
Fig. 7. Transient overshoot velocity with a sudden application of the field 2 · 105 V/cm at room and low temperature for EEFF ¼ 7:7 105 V/cm. Unstrained-silicon (––), x ¼ 0:2 (- - -), x ¼ 0:4 (– – –).
We have simulated several 0.1 lm channel length MOSFETs for x ¼ 0, 0.1, 0.2 and 0.3 using our Monte Carlo simulator. The doping profile was as reported previously, oxide thickness was 4 nm, and the source and drain junction depths were xj ¼ 100 nm. The MOSFET external bias was VDS ¼ 0:5 V, VGS ¼ 1:3 V, and VSB ¼ 0 V. The inhomogeneous steady-state velocity distribution along the channel obtained for each Ge mole fraction is plotted in Fig. 8 at room temperature. The electron velocity is higher than the saturation velocity (which has been shown to be the same for all x [14]) for strained and unstrained-Si channel MOSFETs near the drain edge. This effect is due to the highlongitudinal-electric-field gradient the carriers face as they travel toward the drain. This gradient makes the electrons overshoot the velocity they would have if they were subject to homogeneous steady-state transport (long channels). In order to estimate what the homogeneous steady-state electron velocity would be, we have plotted the velocity obtained by means of Thornber’s expression [21] using the low-longitudinal-field-mobility curve and the longitudinal-field distribution obtained along the channel for x ¼ 0 (dotted line) and x ¼ 0:1 (solid line) in our Monte Carlo simulation. It is always below the saturation velocity limit, as expected. The homogeneous steady-state electron velocity is slightly lower than the inhomogeneous steady-state electron velocity even at the source edge. This is produced by the high-longitudinal-electric-field step the electrons face as they enter the channel. It can be seen that the velocity values obtained for strained-Si devices are higher than the unstrained-Si
Fig. 8. Electron velocity versus channel position at T ¼ 300 K. Velocity distribution obtained in an 0.1 lm MOSFET with VGS ¼ 1:3 V and VDS ¼ 0:5 V for x ¼ 0 (j), x ¼ 0:1 ( ), x ¼ 0:2 (N), x ¼ 0:3 (H). Low-longitudinal-electric-field velocity corrected using Thornber’s expression and the longitudinal-field distribution obtained for the previous MOSFET with x ¼ 0 ( ) and x ¼ 0:1 (––).
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
1353
devices at the source side. The results are in agreement with the simulations performed by Bufler and Fichtner [22] and Jungemann and Meinerzhagen [23]. This fact is directly connected with the increase of drain current at high drain voltages in strained-Si devices as pointed out by [22–24].
6. Modelling velocity overshoot effects In order to model VO effects, taking into consideration their importance in these devices we have simulated several 0.1 lm channel length strained-Si MOSFETs for x ¼ 0, 0.1, 0.2, 0.3 and 0.4. The doping profile used was the one reported later [12]. The oxide thickness was 4 nm, and the source and drain junction depths were xj ¼ 100 nm. The MOSFET external bias was VDS ¼ 0:5 V, VGS ¼ 1:3 V, and VSB ¼ 0 V. The drift electron-velocity profiles along the channel for each Ge mole fraction were fitted using Eq. (12). The low-field mobility curves for each MOSFET and the longitudinalelectric field distribution were obtained using the Monte Carlo calculation for these transistors following the procedure explained in Refs. [9,25]: lðEk ; EEFF Þ ¼ 1þ
l0 ðEEFF Þ 1 oEk þk bðEk Þ bðE1k Þ E k ox l ðE ÞxE 0
EFF
k
vsat
ð12Þ l0 being the low-field mobility, Ek the longitudinalelectric field (along the channel), and EEFF the transverse-electric field (perpendicular to the silicon–SiO2 interface). vsat ¼ 1:1 107 cm/s for all x used here [14] and bðEk Þ ¼ 3 0:31 logðEk Þ [9]. We have obtained the k parameter for different x and temperatures (Fig. 9). It can be observed that parameter k increases as x rises; therefore the electron-velocity overshoot effects (contained in the second term on the right-hand side of expression (12)) show the same trend. This fact is mainly due to the reduction of the intervalley scattering (connected with the split of the sixfold degeneracy in the Si conduction band minimum) responsible for the energy relaxation in the high-longitudinal-electric-field transport regime [14]. As can be observed, the k parameter shows an almost linear dependence on x at both temperatures. We have obtained an empirical analytical expression for k as a function of temperature and x (Ge mole fraction) (Eq. (13)): kðxÞ ðbðT Þ þ 100xÞ105 cm3 =V s
ð13Þ
where bðT Þ is a constant that depends on the temperature: bð300 KÞ ¼ 4 and bð77 KÞ ¼ 6:4.
Fig. 9. Parameter k versus Ge mole fraction used in expression (12) to take into account electron-velocity overshoot effects in strained-Si on Six Ge1x channel MOSFETs at T ¼ 300 and 77 K. More details in [25].
7. Strained-Si/SiGe-on-insulator MOSFETs These new devices based on strained-Si layers and SOI structures are motivated by recent studies that have shown the feasibility of strained-Si/SiGe-on-insulator (SiGe-OI) structures. Such studies have obtained highquality crystalline relaxed SiGe layers with a thickness of less than 10 nm on SiO2 substrates by separation-byimplanted-oxygen techniques [26,27] or by solid-phase epitaxy. Using these structures as a starting point, and growing a thin strained-silicon layer on the relaxed SiGe-OI substrate, both n- and p-channel strained-Si/ SiGe-OI MOSFETs have been fabricated and successfully operated, showing high electron and hole mobilities with a germanium mole fraction as low as 0.1. These strained-Si/SiGe-OI structures combine the advantages of strained-Si/SiGe bulk MOSFETs and those of ultrathin fully depleted silicon-on-insulator. We have used our simulator to study the mobility curves of one of these structures [28] and the mobility curves obtained are shown in Fig. 10. Where we have assume that the semiconductor layer between the two oxides is TW ¼ 10 nm, and take into account different values of the strained-Si layer TSi subjected to the two following constraints: (i) TW ¼ TSiGe þ TSi , and (ii) TSi < TSiGe (where TSiGe is the SiGe layer thickness). The germanium mole fraction has been taken as x ¼ 0:3. In Fig. 10, bold circles correspond to TSi ¼ TSiGe ¼ 5 nm, and bold squares correspond to TSi ¼ 2:5 nm and TSiGe ¼ 7:5 nm. For the sake of comparison, we have also shown mobility curves corresponding to strained-Si/ SiGe bulk MOSFETs (no buried oxide) with the same
1354
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355
them a serious alternative to conventional devices in the ultrahigh scale integration landscape.
Electron Mobility (cm 2/Vs)
2000
SiGe-OI Tw=10nm Bulk SiGe 1600
Acknowledgements
x=0.3 1200
This study was carried out in the framework of Research Project TIC2001-3243 supported by the Spanish Government (MCYT and FEDER).
800
400
References
TSi=2.5nm TSi=5.0nm 0
5
10
10
6
Effective Field (V/cm) Fig. 10. Electron mobility curves versus the transverse effective field for a strained-Si/SiGe-OI MOSFET at room temperature for different values of TSi (TW ¼ TSi þ TSiGe ¼ 10 nm, x ¼ 0:3).
TSi (open symbols) and mobility curves corresponding to unstrained MOSFETs: the solid line represents an unstrained bulk MOSFET (conventional MOSFET); while the dashed line represents an unstrained SOI-MOSFET (conventional SOI-MOSFET) with a silicon thickness of TW ¼ TSi ¼ 10 nm. As can be seen, in the strained case, there is an important increase in the electron mobility compared to the unstrained case, as experimentally observed, due to the reasons explained at the beginning of the paper. The mobility curves corresponding to strained-Si/SiGe-OI MOSFETs are slightly lower than those corresponding to strained-Si/SiGe bulk MOSFETs especially at low transverse effective fields. This is due to the greater phonon-scattering rate in the SiGe case, arising from the greater confinement of the carriers due to the well formed by the two oxides (TW ).
8. Conclusions A comprehensive study of the transport properties of bulk and SOI strained-Si MOSFETs has been performed. Different models for the low-field mobility, the inversion charge centroid and the velocity overshoot effects are introduced. The role that non-local effects, such as velocity overshoot, play in very short transistors is deeply analyzed. The advantages of the newly introduced strained-Si/SiGe-on-insulator (SiGe-OI) structures are described in the last section and the results are in the line of the previous sections where it is clearly stated that the advantages of strained-Si devices make
[1] Gamiz F, L opez-Villanueva JA, Banqueri J, Carceller JE, Cartujo P. IEEE Trans Electron Dev 1995;ED-42:258. [2] Takagi S, Iwase M, Toriumi A. IEEE Tech Digest 1988: 398. [3] Abstreiter G, Brugger H, Wolf T, Jorke H, Herztog HJ. Phys Rev Lett 1985;54:2441. [4] People R. IEEE J Quantum Electron 1985;22:1696. [5] Gamiz F, Fischetti MV. J Appl Phys 2001;89:5478. [6] Chau R, Kavalieros J, Roberds B, Murthy A, Doyle B, Barlage B, et al. Tech Digest––Int Electron Dev Meet 2001; 2001:621. [7] Baccarani G, Wordeman MR. Solid-State Electron 1985; 28:407. [8] Laux SE, Fischetti MV. IEEE Electron Dev Lett 1988; 9:467. [9] Roldan JB, Gamiz F, L opez-Villanueva JA, Carceller JE. Semicond Sci Technol 1997;12:321–30. [10] Gamiz F, L opez-Villanueva JA, Banqueri J, Carceller JE, Cartujo P. IEEE Trans Electron Dev 1995;ED-42:258. [11] Vogelsang T, Hofmann KR. Appl Phys Lett 1993;63(2): 186–8. [12] Iwase M, Mizuno T, Takahashi M, Niiyama H, Fukumoto M, Ishida K, et al. IEEE Electron Dev Lett 1993;14:51. [13] Welser J, Hoyt JL, Gibbons JF. Electron mobility enhancement in strained-Si n-type metal-oxide semiconductor field-effect transistors. IEEE Electron Dev Lett 1994; 15(3):100–2. [14] Roldan JB, Gamiz F, L opez-Villanueva JA, Carceller JE. J Appl Phys 1996;80:5121. [15] Gamiz F, Roldan JB, L opez-Villanueva JA, Cartujo P. Appl Phys Lett 1996;69:797–9. [16] Roldan JB, Gamiz F, Cartujo-Cassinello P, Cartujo P, Carceller JE, Roldan A. IEEE Trans Electron Dev 2003; ED-50:1408. [17] Welser J, Hoyt JL, Takagi S, Gibbons JF. IEDM 1994; 94:373–6. [18] Rim K, Koester S, Hargrove M, Chu J, Mooney PM, Ott J. In: 2001 Symposium on VLSI Technology Digest of Technical Papers, 2001. p. 59–60. [19] Currie MT, Leitz CW, Langdo TA, Taraschi G, Fitzgerad A, Antoniadis DA. J Vac Sci, Technol B 2001;19(6): 2268. [20] Lopez-Villanueva JA, Cartulo-Cassinello P, Banqueri J, Gamiz F, Rodrıquez S. IEEE Trans Electron Dev 1997; ED-44:1915. [21] Thornber KK. J Appl Phys 1980;51:2127.
J.B. Roldan, F. Gamiz / Solid-State Electronics 48 (2004) 1347–1355 [22] Bufler FM, Fichtner W. IEEE Trans Electron Dev 2003; ED-50(2):278. [23] Jungemann C, Meinerzhagen B. Proc ESSDERC 2003;33:9. [24] Lundstrom M. IEEE Electron Dev Lett 2001;ED-22:293. [25] Rold an JB, G amiz F, L opez-Villanueva JA, Carceller JE. IEEE Trans Electron Dev 1998;ED-45:993.
1355
[26] Ishikawa Y, Shibata N, Fukatsu S. Appl Phys Lett 1999; 75:983. [27] Mizuno T, Sugiyama N, Tezuka T, Takagi S. IEEE Trans Electron Dev 2002;49:7. [28] Gamiz F, Roldan JB, Godoy A. Appl Phys Lett 2002; 80:4160.