Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

Author’s Accepted Manuscript Implementation of nanoscale circuits using dual metal gate engineered Nanowire MOSFET with high-k dielectrics for low power applications J Charles Pravin, D. Nirmal, P. Prajoon, J. Ajayan www.elsevier.com/locate/physe

PII: DOI: Reference:

S1386-9477(16)30254-5 http://dx.doi.org/10.1016/j.physe.2016.04.017 PHYSE12412

To appear in: Physica E: Low-dimensional Systems and Nanostructures Received date: 30 January 2016 Revised date: 13 April 2016 Accepted date: 18 April 2016 Cite this article as: J Charles Pravin, D. Nirmal, P. Prajoon and J. Ajayan, Implementation of nanoscale circuits using dual metal gate engineered Nanowire MOSFET with high-k dielectrics for low power applications, Physica E: Lowdimensional Systems and Nanostructures, http://dx.doi.org/10.1016/j.physe.2016.04.017 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting galley proof before it is published in its final citable form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

Implementation of Nanoscale Circuits Using Dual Metal Gate Engineered Nanowire MOSFET With high-k Dielectrics for Low Power Applications J Charles Pravin, D. Nirmal, Prajoon. P, Ajayan. J Department of Electronics and Communication Engineering, Karunya University, Coimbatore, Tamil Nadu, India Abstract This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO2 than SiO2 in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, ION/IOFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO2, DIBL shows a reduction of 61.5% over SiO2. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO2 when compared to SiO2. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO2 based device. From the analysis, it is found that HfO2 will be a better alternative for the future nanoscale device.

Keywords: Dual Metal Gate engineering; Junctionless Nanowire MOSFET; High-k gate dielectric; Implementation of inverter circuits using the device for different gate dielectrics and delay decreases for high-k dielectrics than SiO2

1.

Introduction

Intensive Scaling of the semiconductor devices in recent years, results in the ultra-short gate dimension of about 14 nm technology node in low power circuits. This complicates the device fabrication process, as the concentration gradients required are n-type with concentration 1x10-19 cm-3 and p-type with concentration of 1x10-18 cm-3. Expensive millisecond annealing techniques are needed to form such a distinct junction. This paved the way for a new type of device called junctionless MOSFET [1]. The work function difference between the gate metal and silicon provides switching of the device. The device has CMOS functionality with the goodness of no junction. It has also been reported that the device has almost ideal DIBL, ideal subthreshold slope and less leakage current than inversion mode device [1], [2]. Many works have been published in this device including single gate, double gate and triple gate structure with much more improvement in performance has been reported [3]-[9]. The cylindrical structure in conventional MOSFET has reported good short channel performance it also has good gate control by the all-around gate [10]. The dual metal gate structure produces improved carrier transport efficiency, drain current and transconductance compared to single metal gate structure [11]-[13].

The Baruah et al., has formed, a dual metal double gate structure with SiO2 as gate dielectric and high-k spacer. They have reported good transconductance, early voltage etc; for their device [14]. Lou et al., has proposed, cylindrical gate structure with dual metal gate engineering and SiO2 as gate dielectric [22]. They found a suppression in DIBL and ON-current improvement than Single metal gate counterpart. Though there is improvement in analog parameters the SiO 2 gate dielectric reaches its scaling limit. Due to intensive scaling, the dimension of the semiconductor devices become rigorously small and the oxide thickness also becomes very small, hence the leakage and short channel effects has become serious issues. The high-k dielectric instead of SiO2 is the suitable alternative for this bottleneck. As the gate oxide thickness is scaled down, the gate oxide leakage increases exponentially, this is the reason for the search of high-k gate dielectric material [16]. In this work, we have implemented dual metal cylindrical gate structure with high-k dielectrics, Nano sizing of high-k dielectric materials seems to have improved properties than SiO2, due to large surface area [16]. The high-k dielectric material such as Si3N4, Al2O3, Y2O3, HfO2 and TiO2 are used for this analysis and found to provide much improvement in leakage current with high-k dielectric's than SiO2. The nanoscale inverter circuit is also implemented with different high-k dielectrics and found that it has superior performance with high-k dielectric than SiO2 due to its improvement in gain, output resistance, transconductance generation factor and transconductance. 2. Device structure and parameters The 3D view of dual metal surround gate junctionless transistor (DMSGJLT) is shown in the fig1. This is a cylindrical structure with two different metal gates, that is metal M1 of workfunction 4.97 and metal M2 made of workfunction 4.27 taken as per [22]. The length of the first metal is L1=20 nm and the length of second metal is L2=20 nm. The centre rod is a cylindrical silicon rod with a doping of 2x10 19 cm-3 uniformly throughout the device layer. This is the device active region where the device operation takes place.

(a)

N+

N+

N+

(b) Fig. 1. (a) 3D view of DMSGJLT, (b) Crossectional view of DMSGJLT

The device cross section is shown in Figure 1(b). The layer above the silicon region is the gate oxide region which should provide a good capacitance value for lesser thickness. SiO2 is most widely used as gate oxide materials due to its large band gap of about 9 eV with good conduction and valence band offset's. The oxide thickness becomes less than 2nm due to continuous scaling of the device. This increases the leakage current due to tunnelling which in turn elevates the power consumption and reduces device reliability [17–20]. The device is formed by replacing gate oxide with various high-k dielectrics and comparing them to SiO2. Due to high-k gate oxide, gate capacitance increases and leakage effect decreases. Table.1 Comparison of properties of different high-k gate dielectric materials [15] [21] [23] [24]. Sl. No

Properties

SiO2

Si3N4

Al2O3

Y2O3

HfO2

TiO2

1

Dielectric Constant

3.9

7.5

10

15

23

40

2

Band gap (eV)

9

5

8.8

5.6

6

3.5

3

Band offset for electrons (eV)

3.5

2.5

2.8

2.3

1.4

1.2

4

Band offset for holes (eV)

4.4

1.78

4.9

2.6

1.5

1.8

5

Refractive index

1.4

2.0

1.7

1.9

2.1

2.6

Table.1 shows the parameters of different high-k dielectric used for this analysis. From the table it is found that TiO2 has high dielectric constant but less band gap which may result in the increase of leakage. 3.

Results and discussion

The DMSGJNT is investigated using Sentaurus TCAD simulator. The TCAD simulation, employing physical model such as temperature dependant carrier transport model, quantum and band gap narrowing model. Auger, Radiative recombination and Shockley-Read-Hall, is included for analysis of leakage current. 3.1. Electrical Parameters The parameters such as electric potential, electric field and electron velocity are analysed in this section. The electric potential variation along the channel length for DMSGJLT is shown in Fig.2.for various high-k oxide materials. In a device with high dielectric constant, electric potential decreases with respect to position along channel.

Fig.2. Variation of electric Potential in the Channel length for different high-k dielectrics The workfunction of the gate metal and the electric potential is related as

where W is the

workfunction of the gate material and q is the charge of the electron. From the above equation, it is clear that electric potential ( ) decreases with increase in the workfunction of the gate material. Due to this phenomena, a step increase is noted in the interface of the two gate metal, which is also reported in [21] [22]. The step increase in the potential, increases the carrier velocity and its transport efficiency and an increase in drain current is observed [21]. In this work we have taken the workfunction of the two metal M1 as 4.97 eV, which corresponds to cobalt and M2 as 4.27 eV, which corresponds to Aluminium, in accordance with [15]. In Fig.2. electric potential with SiO 2 as gate dielectric, is validated with the data taken from [22]. From the results, it is observed that as the dielectric constant of the gate dielectric increases, the potential decreases. This is due to the fact that as the dielectric constant k increases, the mobility of the electron decreases and hence the resistance of the channel increases. Due to this a small dip in the potential is noticed as the dielectric constant increases. The dip in the potential with high-k dielectric is very small, when compared with SiO2 which can be negligible. The variation of electric field along channel is shown in the Fig.3. The step increase in the potential contributes an additional electric field Peak in addition to the existing peak at the drain end, this effect is also reported in [14][22].

Fig.3. Variation of electric field in the Channel for different high-k dielectric The effective field in the drain end is reduced, due to the additional electric field peak that arises because of gate engineering. This results in less DIBL and hot-carrier effects, which is important in short-channel devices

shown in Fig. 3. With the usage of high-k dielectric, the peak observed in the source region shows an increase of 40 % for HfO2 than SiO2, this increase in the peak value improves the electron velocity of the device and the first peak controls the electron velocity by proper choice of gate metal [24]. In the interface of the two metal an electric field peak is obtained which results in the large average velocity of the electron entering from the source to the channel. Variation of electron velocity in the channel is shown in Fig.4. for different high-k dielectrics. It is also found from the results that, as the value of dielectric increases the electron velocity peak also increases. HfO2 shows about 31 % increase in the peak value than the conventional SiO2. This shows that good carrier transport can be made with HfO2.

Fig. 4. Variation of electron velocity along the Channel length 3.2. Drain Current characteristics The saturation current is the ON current of the device. In Fig.5.the ON current of DMSGJLT are plotted for various dielectrics and it’s found to decreases exponentially with increasing k values. This is due to the fact that as the dielectric constant k increases, the resistance of the channel increases and hence the ON current shows a slight decrease.

Fig. 5. ON current variation with respect to drain source voltage for different high-k gate dielectrics OFF current is plotted against drain voltage for different high-k dielectrics and is shown in the Fig. 6. The leakage current is given by the OFF current of the device. From the results, it is clear that SiO2 is reported to have high off current and it reduces with the increase in k value, as the barrier potential faced by the carrier in the channel increases with the increases in dielectric constant. Thus by using high-k dielectric as gate dielectric the leakage current is reduced to a great extent

Fig. 6. OFF current variation with respect to drain source voltage for different gate dielectrics The ION/IOFF and DIBL is plotted against different high-k values are shown in Fig.7. It is clear that ION/IOFF ratio is high as the order of 109 with high- k dielectric such as HfO2 than SiO2 having value of about 104. The device will have a proper switching if the ION/IOFF ratio is high. Since the DMSGJLT with HfO2 has a large ratio, the switching of the device between ON and OFF state is spontaneous. Eventhough TiO2 has good ON/OFF ratio it will not be suitable because of its low band gap, which increases the leakage.

Fig. 7. Comparison of ION/IOFF and DIBL for different high-k materials DIBL is the short channel effect that has to be consider for scaling the device. The DIBL is given as

where

and

are the threshold voltages at linear and saturation region. From Fig. 7, it is evident that

DIBL shows exponential decrease of about 61.5% for HfO2 than SiO2 in DMSGJLT. 3.3. Analog Performance Output resistance (Ro), Transconductance (gm) and transconductance generation factor (gm/IDS) are analysed for different high-k gate oxide materials in this section. The Fig. 8 shows the two graphs of transconductance and drain current variation with respect to gate voltage. The transconductance shows an improvement of 44% for HfO2, when compared with SiO2 for the gate voltage of 0.8V. The improvement in gm is attributed to the charge control of the device. For higher gate voltage of above 0.9V the drain current shows a considerable improvement of 33% for the gate voltage of 1V.

Fig. 8. Variation of transconductance (gm) and drain Current (IDS) with VGS The transconductance generation factor shows an improvement of about 35% for HfO2 than SiO2 for 0.8V gate voltage which is shown in Fig 9.

Fig. 9. Variation of transconductance generation factor gm/IDS with VGS The intrinsic gain and output resistance is plotted against different dielectric and shown in the Fig. 10.

Fig. 10. Variation of R0 and gain with dielectric constant (k) The output resistance, Ro of a MOS device is given as Where VA is the early voltage and ID is the saturated drain current. The device with TiO2 as gate dielectric has high R 0, compared to the device with SiO2 gate dielectric, because the output resistance increases with increase in k value of the oxide material. Hence this can be applied for feedback and cascade amplifier. The gain also shows a 2 unit's improvement from SiO2 to HfO2. 3.4.

Circuit Implementation

The Fig. 11(a) is the CMOS inverter in which the gate voltage is given as the input. The voltage transfer characteristics of the inverter circuit implemented using DMSGJLT with different dielectric constant dielectric material is shown in Fig. 11(b).

(a)

(b)

Fig. 11. (a) Inverter Circuit. (b) Comparison of voltage transfer characteristics of inverter using DMSGJLT with different high-k materials. Due to the increase in transconductance, transconductance generation factor and gain of the device with HfO2 than SiO2, the circuit application shows an improvement in performance. Due to the improvement in transconductance (gm), transconductance generation factor (gm/I DS), gain and output resistance for the high-k dielectrics such as HfO2, the device performance will show enhancement when implemented in the circuit. From the analysis it is found that hafnium oxide is the good alternative for SiO2.

Fig. 12. Variation of output voltage with time Period of the inverter The output voltage variation with respect to time period is shown in the Fig.12. The performance of device with high-k dielectrics such as HfO2 shows a considerable improvement when implemented in the circuit. The delay of the device shows a decrease of about 4 % while using HfO2 rather than using SiO2. Thus the speed of the device and the circuit improves a lot by using high-k dielectrics. From all the analysis it is clear that HfO2 will be a better alternative for SiO 2 for future scaling of the device.

3.5 Power Dissipation in Inverter Circuit The power dissipation of the CMOS inverter circuit for different high-k dielectrics is given in the Fig. 13. We have found from the previous analysis that as the dielectric constant of the gate dielectric increases the leakage current decreases. Due to this the power dissipation also decreases in the circuit. The power dissipation analysis is carried out in inverter circuit for various high-k

dielectric materials. From the results it is evident that the power dissipation decreases at higher dielectric constants. For HfO2 we have obtained power dissipation as 4.5x10 -15W. Whereas for SiO2 the power dissipation is found to be 9x10-9 W.

Fig. 13. Comparison of Power Dissipation for Different high-k Dielectrics From this it is clear that using high-k dielectrics such HfO2 as gate dielectrics provides a circuits with low power dissipation.

4.

Conclusion In this work, the influence of high-k dielectrics is analysed for the gate engineered junctionless

surround gate transistor for different high-k dielectrics. A comparison in performance is made between SiO2 and various high-k materials as gate dielectrics. Here HfO2 is found to be the best alternative for SiO2, as HfO2 has a moderate band gap of 6 eV, which is favourable for switching purposes. The ION/IOFF ratio increases and as the dielectric constant of the gate dielectric increases the leakage current decreases. The DMSG-JLT device shows an improved drain current of about 33% and increase in transconductance of about 44%. DIBL shows exponential decrease of about 61.5% with the HfO2 k dielectric based device over conventional device. The device also shows improvement in performance with high-k dielectrics for the inverter circuit. The high-k dielectrics in the DMSG-JLT improves the device performance to make the device as a good choice for semiconductor industry. The inverter circuit is also implemented with this device, for different high-k dielectrics and the performance shows an improvement, with high-k dielectrics than SiO2. The delay of the inverter circuit shows a 4% decrease with HfO 2 when compared to SiO2. Moreover, the result implies that power dissipation in the inverter circuit is substantially reduced when the circuit is implemented with high -k dielectric DMSGJLT. As a result, DMSGJLT with HfO2 as gate dielectric can be considered a good alternative for the low power VLSI circuits.

Acknowledgments The authors would like to thank VLSI Laboratory of Karunya University to carry out this research work.

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Highlights    

Dual metal gate engineered Junctionless MOSFET with various high-k dielectric is implemented.

Analysis of different parameters in DMSGJLT with various high-k gate dielectrics is made. Implementation of Nanoscale inverter circuit using DMSGJLT with various high-k gate dielectrics and improvement in delay is observed. This device is applicable for low power applications.