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Ge interface quality by surface and annealing treatments
Accepted Manuscript Title: Improving the ALD-grown Y2 O3 /Ge interface quality by surface and annealing treatments Author: C. Zimmermann O. Bethge K. Winkler B. Lutzer E. Bertagnolli PII: DOI: Reference:
S0169-4332(16)30235-5 http://dx.doi.org/doi:10.1016/j.apsusc.2016.02.066 APSUSC 32584
To appear in:
APSUSC
Received date: Revised date: Accepted date:
10-12-2015 4-2-2016 5-2-2016
Please cite this article as: C. Zimmermann, O. Bethge, K. Winkler, B. Lutzer, E. Bertagnolli, Improving the ALD-grown Y2 O3 /Ge interface quality by surface and annealing treatments, Applied Surface Science (2016), http://dx.doi.org/10.1016/j.apsusc.2016.02.066 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
Improving the ALD‐grown Y2O3/Ge interface quality by surface and annealing treatments
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C. Zimmermann1, O. Bethge1, K. Winkler1, B. Lutzer1 and E. Bertagnolli1 1 Institute of Solid State Electronics, Technische Universität Wien, Floragasse 7, 1040 Wien, Austria
Highlights
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• Investigation of interfacial mechanisms for hydrofluoric and thermal pre-treated Ge-surfaces • Improvement of interface trap density due to proper annealing treatments • Further improvement of interfacial and electrical properties due to catalytic acting thin platinum layer Abstract
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Metal Oxide Semiconductor capacitors are investigated, employing ALD grown Y2O3 as gate dielectric, and n‐type (100) germanium as channel substrate. The effect of post deposition
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annealing (PDA) in oxygen and forming gas atmosphere using a thin catalytically acting
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platinum (Pt)‐layer on the Y2O3/Ge interface is electrically analysed for buffered hydrofluoric (BHF) and thermally pre‐treated Ge‐surfaces.
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The Pt‐assisted PDA ensures even for BHF pre‐treated samples very low values for the interface trap density Dit of 1.55*1011 eV‐1cm‐2 and low leakage current densities J of <7*10‐9 A /cm2 outperforming conventional PDA treatments. The interfacial formation of GeO2 and Yttrium germanate after PDA is proven by using X‐ray Photoelectron Spectroscopy measurements.
Introduction
The successful use of silicon in Complementary Metal Oxide Semiconductor (CMOS) technology in recent decades was largely based on the existence of a stable intrinsic oxide and a high‐quality SiO2/Si interface. The progressive miniaturization of Si/SiO2 MOS transistors has induced a dramatically increase of the leakage current caused by the extremely thin SiO2. To overcome this issue the “High‐k + Metal Gate” (HKMG) technique was successfully implemented [1]. In addition, the relatively low charge carrier mobility of the Si
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channel used so far is considered as limiting factor for high‐speed CMOS devices. Germanium has indeed a high hole and electron mobility (3900 cm²/Vs; 1900 cm²/Vs), but several shortcomings like the thermodynamic instability (above of 400 °C) and the water solubility of the native germanium‐oxide prevented the successful implementation of germanium in
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CMOS devices [2‐4]. Therefore, some research for suitable cleaning and passivation‐ techniques was done to improve and stabilize the interface quality in Ge based HKMG stacks
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[5, 6].
Surface cleaning using hydrofluoric (HF), hydrogenbromid (HBr), hydrogenchlorid (HCl), and
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ammonium sulfide ((NH4)2S) provided partially the complete removal of GeOx and led to a hydrogen (H), chlorine (Cl) and sulfide (S) terminated Ge‐surface [7‐12]. Conventional cleaning methods with HF showed not only a rougher surface compared to HCl pre‐treated
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Ge‐surfaces [7], but also depending on the HF concentration a defective and deteriorated surface quality [13]. The research carried out by Xue et al. showed that with a cyclic HF/DI
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water dip a smoother surface can be achieved in comparison to a highly concentrated HF solution, which induce surface damage [9]. A complete removal of the native germanium‐ oxide by a thermal evaporation step at 360 °C in an ultrahigh vacuum UHV was demonstrated
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by Dimoulas et al., using reflection high‐energy electron diffraction (RHEED) measurement
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[14]. Prabhakaran et al. achieved an atomically clean Ge‐surface by thermally decomposing a thin oxide layer at about 430 °C to 450 °C, identified by XPS and UPS measurements [3, 15].
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In literature a combination of both methods, wet chemical pre‐treatment with a following thermal desorption step, is frequently reported. For example, Delabie et al. removed the natural germanium‐oxide initially by a HF solution followed by thermal desorption at 650 °C to remove O and C residues which arise after HF etching [7, 16]. Concerning a high quality surface passivation, an oxide free Ge‐surface or one of the Ge‐ oxides/nitrides (GeO2; Ge3N4; GeOxNy ...) combined with non‐native oxides like La2O3, Al2O3, HfO2 or Y2O3 exhibiting promising interface characteristics [5, 6, 17‐21]. It is also important that high‐k oxides form a good electrical transition with the semiconductor in terms of roughness and defects at the interface. Especially high‐k oxides from the rare earths elements, such as Y2O3, allow a lattice‐matched growth with only few lattice defects between semiconductor and oxide [22‐24]. For the deposition of thin high‐k oxide films, atomic layer deposition (ALD) is the method of choice due to ultra‐smooth and homogeneous film‐surfaces with highest step coverage [25]. In comparison, techniques such
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as reactive sputtering or metal organic chemical vapour deposition (MOCVD) produce uneven dielectric surfaces leading to charge trapping [26]. Dong and co‐workers reported that a porous Pt‐layer deposited on different metals is leading to an increased oxidation of the metals during an O2 annealing process which is induced by
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dissociated O2 [27]. Henkel et al. demonstrated a reduction of the interface trap density Dit to mid 10*1011 eV‐1 cm‐2 in ZrO2/La2O3/Ge capacitors by using the Pt‐assisted oxidation of the
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Ge/high‐k interface [28]. Up to now, the lowest Dit of 4.5*1010 eV‐1 cm‐2 was achieved in
Al2O3/GeO2/Ge capacitors by using an electron cyclotron resonance plasma formed GeO2 on
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a Ge‐surface pre‐treated by diluted HF [18]. Another promising passivation technique after HF (0.5 %) pre‐treatment, is using O2 plasma for growing high quality GeO2 leading to an interface trap density of 5*1011 eV‐1 cm‐2 in TiO2/HfO2/GeO2/n‐Ge capacitors [19]. By using a
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combined surface pre‐treatment of HF and thermal desorption at 650 °C, thermally grown GeO2 in HfO2/GeO2/Ge capacitors yield also to low Dit of 3*1011 eV‐1 cm‐2 [16].
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In this study, the effect of Pt‐assisted annealing in oxygen and forming gas atmosphere compared to conventional PDA annealing is discussed by using ALD grown Y2O3 on differently pre‐treated Ge‐surfaces. The native oxide is either initially wet chemically removed or
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measurements.
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thermally desorbed from the Ge‐surface. The interface is examined by means of in‐situ XPS‐
As metal gate a titan nitride/tungsten (TiN/W) stack is used with W acting as a good cover
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and conducting layer able to prevent an oxidation of the underlying TiN layer, which is employed due to a proper work function for pMOS devices.
Experimental
For the fabrication of the MOS‐capacitors antimony (Sb) doped (100) Ge with a resistivity of 4.9 to 5.9 Ωcm (MTI Corporation) was used as substrate. Two methods were used for the surface preparation (i) wet‐chemical treatment with a 3 min cyclical 15 sec NH4F/HF (7:1) / 15 sec DI‐water dip, denoted in the following as “BHF” and (ii) thermal surface treatment in an ultrahigh vacuum (UHV) chamber by heating the sample, denoted in the following as “desorb”. In order to analyse the semiconductor surface of remaining GeOx residues XPS‐ measurements were performed within 5 min after pre‐treatment. Subsequently, the samples were transferred into the ALD chamber (TFS 200, Beneq) within 1 min without breaking the
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vacuum. For this purpose a cluster tool is used consisting of ALD and XPS tool, which are connected by a vacuum transfer system with load lock access. As a metal organic precursor tris(methylcyclopentadienyl)yttrium kept at 150 °C was used, which reacts with water as an oxidizing agent to form Y2O3 on the surface and by‐products are purged by nitrogen. The
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growth rate of the as deposited yttrium oxide was measured to be 0.15 nm/cycle by using spectroscopic ellipsometry (J.A. Woollam). To analyse interfacial reactions of the as
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deposited Y2O3, the samples were transferred without breaking the vacuum for further XPS investigations.
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Subsequently, 50 cycles Y2O3 (~7.5 nm) were deposited onto the different pre‐treated Ge‐ surfaces for the fabrication of MOS capacitors and on one subset of samples a 5 nm platinum layer was sputtered (Von Ardenne) on the top of the as deposited oxide layer. All samples
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have been exposed to an O2 PDA for 10 min at 550 °C followed by forming gas annealing (FGA) at 350 °C for 30 min in a rapid thermal annealing (RTA) furnace (UniTemp). A metal
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stack of TiN (25 nm) and W (78 nm) was deposited for the circular shaped gate electrodes with a diameter of 100 µm which were lithographically patterned and structured by means of reactive ion etching (RIE) in SF6 / N2 plasma. As back contact a Ti/Au‐metallization was
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applied after Ar+ cleaning of the Ge backside. Finally, one part of the samples underwent a
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post metallization annealing (PMA) in forming gas at 350 °C for 30 min. Oxide and interface quality was evaluated via capacitance‐voltage (CV), conductance‐
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frequency (Gf) and current‐voltage (IV) measurements using a parameter analyser (4200‐SCS Keithley), a capacitance bridge (AH‐2700A Andeen Hagerling) and a probe station (Cascade MicroTech). Electrical properties like the oxide capacitance per area Cox_□, capacitance equivalent thickness CET, flatband‐voltage VFB and hysteresis width were extracted from the CV‐measurement. The CV‐curves were measured in a voltage range of ‐2 V to +2 V at different frequencies (1 MHz, 500 kHz, 100 kHz, 50 kHz, 10 kHz, 1 kHz, 100 Hz). The influence of a lossy dielectric interface layer or series resistance was eliminated by a correction formula after Kwa et al. [29]. The CET was calculated according to CET = ε0*3.9/ Cox_□, whereat the value of Cox_□ was taken from the 100 Hz CV‐curve in accumulation at +2 V. For the determination of the hysteresis width, the voltage values at the capacitance Cmin + (Cmax ‐ Cmin)/2 were taken from the forward and backward CV‐curve at 1 MHz and the flat band voltage was calculated by using the CVC‐program from Hauser et al. from the 1 MHz CV‐ curve [30]. Gf‐measurements were used for the calculation of the interface trap density Dit
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after the conductance method [31, 32] in a frequency range from 1 kHz to 10 MHz. Dit values were extracted close to the Ge mid‐gap state. Breakdown voltage Vbreak and leakage current density J were obtained by IV‐measurements. The value of the breakdown voltage was extracted from the IV‐measurement where a sudden increase of the current by several
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orders of magnitude occurs and the leakage current density was read‐off at 1V+VFB in forward bias.
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Chemical and interfacial properties of the films were examined by XPS using Al Kα as X‐ray source (Phoibos 150 MCD‐9 detector, Specs). The binding energies of all XPS spectra were
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calibrated for the C1s and Ge2p states. For the fitting of the peak positions the Gaussian‐ Lorentzian line shape was used, provided by the analysing tool Casa XPS (VAMAS Processing Software).
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Results and Discussion
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(A) XPS analysis
After the pre‐treatment of the Ge surface, XPS‐measurements (Fig.1) were performed in
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order to analyse the surface of GeOx residues.
Fig.1: XPS of the Ge2p core‐level of thermally pre‐treated and BHF pre‐treated Ge surfaces. No evidence of GeOx residuals are visible by XPS. The inset shows the Ge starting surface covered by native oxide.
The XPS‐measurements show for both preparation methods neither a GeO2‐peak at 1220.6 eV nor a GeOx (x <2) peak at 1219.3 eV [15]. This suggests that the substrate oxide of the Page 5 of 18
starting surface (Fig.1, inset) was successfully reduced below the XPS detection limit of 0.1 atom%. Such removal of the native germanium‐oxide by thermal evaporation is already well known [14]. Concerning the BHF treatment for GeOx removing, no unambiguous evidence can be found in literature. It is reported by XPS study that no oxide after hydrofluoric (HF)
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pre‐treatment can be found [5] , while it was also contrary reported that non‐negligible sub‐ oxides (~ 5 Å) remain on the surface after HF etching, measured with second harmonic
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generation (SHG) [5, 8].
Deposited oxide thickness after 10 ALD cycles was measured by ellipsometry to be 1.58 nm
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for the BHF pre‐treated surface and 2.28 nm for the thermal pre‐treated surface. The corresponding in situ XPS spectra of the Ge2p and Y3d state are shown in Fig.2 for the wet‐
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chemically (left) and thermally pre‐treated (right) Ge‐surfaces.
Fig.2: In‐situ XPS spectra of the Ge2p and the Y3d state (inset) of (c) pre‐treated Ge‐surface with Y3d state of Si/Y2O3 as reference (b) as deposited Y2O3 and (a) annealed Y2O3 (O2 at 550 °C for 30 sec) on wet‐chemically (left) and thermally (right) pre‐treated Ge surfaces.
10 cycles of as deposited Y2O3 (Fig.2b, left), forms a broad shoulder in the Ge2p spectrum of the wet‐chemical treated surface which indicates the growth of GeO (at 1218.88 eV) and YGeO (at 1219.59 eV) on the differently pre‐treated starting surfaces (Fig.2c). Notably, in the Page 6 of 18
as deposited samples significant formation of interfacial YGeOx is apparent also indicated by the shift of the Y3d peak (Fig.2 insets) to higher binding energy (BHF: 156.92 eV/desorb: 156.93 eV) compared to Y2O3 deposited on Si (156.2 eV, Fig.2c inset) or compared to data as reported elsewhere (156.6 eV) [33]. In the case of the thermally pre‐treated sample (Fig.2b,
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right), only a slight growth of GeO and YGeO is detected. The GeO vanishes by applying PDA (Fig.2a) at 550 °C for 30 sec and the formation of a significant yttrium germanate phase
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(YGeOx) as well as an additional growth of GeO2 is observed. Wang et al. reported that during the process of annealing, GeO desorbs from the interface and is trapped into the oxygen
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deficient YGeOx leading to an oxygen densification, which suppresses GeO volatilization and maintains the quality of Ge/GeO2 interfaces [24]. The peak deconvolution in Fig.2a reveals a more pronounced YGeO peak of the wet‐chemically pre‐treated sample in comparison to the
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thermally pre‐treated sample. It seems that during the annealing a larger amount of GeO desorbs from the interface of the wet‐chemically pre‐treated sample and incorporates into
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the yttrium germanate layer inducing a more pronounced germanate phase. In the case of the thermally pre‐treated sample, however, less GeO desorbs from the interface resulting in
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an increased growth of interfacial GeO2. The good passivation properties of the grown GeO2
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layer are proven in the electrical characterization part of this study.
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(B) Electrical characterization
Electrical characterization was carried out based on W/TiN/Pt/Y2O3/n‐Ge and W/TiN/Y2O3/n‐ Ge capacitors. For the fabrication of the samples, two different methods of surface preparation were used. On both sets of samples, ALD grown Y2O3 of 50 cycles resulted in a layer thickness of ~7.5nm determined by means of ellipsometry. Measurements of several samples show a small deviation in thickness of only +/‐ 0.24 nm. In the case of the BHF pre‐ treated samples, especially the influence of a thin catalytically acting Pt‐layer in conjunction with a PMA on the electrical properties has been studied. Also the additional effect of PMA was examined on the basis of the thermally pre‐treated samples. From the CV‐characteristics of the gate stacks with wet‐chemically pre‐treated Ge‐surfaces, shown in Fig.3(a, b) left, we can conclude that a Pt‐assisted PDA at 550 °C reduces the hysteresis width which indicates a lower amount of oxide charges. In addition, the flat band
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voltage is positively shifted compared to a sample with conventional PDA. This effect can be explained by an increased amount of oxygen induced by the PDA, which decreases the density of fixed oxide charges leading to a shift of the flat band voltage [34]. Thereby, also a reduction of the Dit from 2.34*1011 eV‐1cm‐2 down to 1.55*1011 eV‐1cm‐2 was achieved. An
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improvement in the leakage current density by about two orders of magnitude, and a twice as high breakdown voltage is also achieved by Pt‐assisted PDA. It is worth mentioning here
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that the IV‐measurements were made at multiple spots distributed over the fabricated
sample. In the case of the Pt‐assisted PDA sample the JV‐characteristic shows an almost
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homogeneous behaviour over different spots, whereas those of the sample with
conventional PDA strongly differ for individual spots. Due to these discrepancies in leakage current it is generally difficult to make clear statements about it. However, in principle it can
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be said that due to the conventional PDA less reinforced oxide growth at the Y2O3/Ge interface occurs and therefore a lower oxide thickness results in higher leakage current.
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Fig.3: CV‐ and JV‐characteristic of the wet‐chemical pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitors with Pt‐assisted PDA (a), and conventional PDA (b) in oxygen at 550 °C for 10 min. FGA and PMA each at 350 °C for 30 min were conducted on both samples.
A further method to estimate the quality of the oxide is the determination of its conduction mechanisms [35]. Based on the sample in Fig.3a, three different conduction mechanisms are observed (Fig.4) within the Pt‐assisted PDA Y2O3‐stack deposited on a wet‐chemical pre‐ treated Ge‐substrate, whereby Fowler‐Nordheim (FN) tunnelling and direct tunnelling (DT) are most significant. While for high bias (>7 V) FN tunnelling is the dominant mechanism, DT is evident for the low bias region (<2.7 V). Also Poole‐Frenkel (PF) emission is observed in the middle bias region (3.4 V‐4.6 V), indicating that the leakage current in this voltage range is governed by a trap assisted mechanism [35].
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Fig.4: Leakage current mechanisms of the BHF pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitor with Pt‐assisted PDA. Fowler‐Nordheim (FN), direct tunnelling (DT) and Poole‐Frenkel (PF)
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regimes are identified and indicated. FN tunnelling is observed in the high bias region (7.14 V‐10 V), DT in the low bias region (0.37 V‐2.7 V) and PF emission in the middle bias region
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(3.4 V‐4.6 V).
In Fig.5, CV‐characteristics for thermally pre‐treated W/TiN/Y2O3/n‐Ge MOS‐capacitors are
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shown employing Pt‐assisted PDA (Fig.5b, d) and conventional PDA (Fig.5a, c) at 550 °C for 10 min, as well as additional PMA (Fig.5c, d) treatments. Comparing the PDA sample in Fig.5a with the Pt‐assisted PDA sample in Fig.5b where no PMA is provided, only minor differences in the electrical parameters can be obtained, whereby the Dit is slightly reduced from 4.91*1011 eV‐1cm‐2 to 3.18*1011 eV‐1cm‐2. By using a PMA, the Dit of the Pt‐assisted PDA sample in Fig.5b can be reduced from 3.18*1011 eV‐1cm‐2 to a low value of 1.04*1011 eV‐1cm‐2 which is shown in Fig.5d. Additionally, the flat band voltage can be reduced from ‐468 mV to ‐56.3 mV and the hysteresis width from 228 mV to 59.71 mV at constant CET and Cox_□. For the sample with conventional PDA, shown in Fig.5a, only a slight reduction of Dit from 4.91*1011 eV‐1cm‐2 to 1.94*1011 eV‐1cm‐2 (Fig.5c) is observed whereby a noticeable reduction of VFB and hysteresis width have been achieved.
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Fig.5: CV‐characteristic of the thermal pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitors with Pt‐assisted PDA (b, d) and conventional PDA (a, c) in oxygen at 550 °C for 10 min.
All samples received a FGA at 350 °C for 30 min after the oxygen annealing. PMA was
applied to the samples c) and d) only.
In Table1 all measured properties of the examined samples are depicted.
Sample
Dit
CET
J(VFB+1V)
Vbreak
VFB
Hysteresis
Cox_□
1/(eV*cm²)
(nm)
(A/cm²)
(V)
(mV)
(mV)
(µF/cm²)
BHF w. Pt (PMA)
1.55e11
10.23
6.46e‐09
9.6
‐6.66
94.47
0.34
BHF w/o Pt (PMA)
2.34e11
4.61
1.52e‐07
4.73
‐253.1
606.49
0.75
Desorb w. Pt (PMA)
1.04e11
9.89
6.07e‐09
8.66
‐56.26
59.71
0.35
Desorb w. Pt
3.18e11
9.89
‐
‐
‐468.3
228.12
0.35
Desorb w/o Pt (PMA)
1.94e11
7.67
8.52e‐09
11.5
‐115.9
172.83
0.45
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Desorb w/o Pt
4.91e11
7.75
‐
‐
‐307.6
294.96
0.45
Table1: Measured electrical parameters of the wet‐chemically (BHF) and thermally (desorb) pre‐ treated surfaces of W/TiN/Y2O3/n‐Ge MOS capacitors with Pt‐assisted PDA (w. Pt) and conventional PDA (w/o Pt) in oxygen at 550 °C for 10 min. A subsequent FGA at 350 °C for 30 min was applied to all
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samples after the oxygen annealing. The utilization of a PMA at 350 °C for 30 min is indicated.
For the samples with conventional PDA and PMA (Fig.3b and Fig.5c) Dit's in the range of
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2.34*1011 eV‐1cm‐2 for BHF and 1.94*1011 eV‐1cm‐2 for thermally pre‐treated Ge surfaces are
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achieved, comparable to values reported elsewhere [21, 23, 36‐38]. The CET is determined between 4.5 nm (BHF‐samples) and 7.6 nm (desorb samples) and is well below the values of the Pt‐assisted PDA samples (10.23 nm and 9.89 nm) also indicating a stronger growth of
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interfacial GeO2 by the Pt‐assisted PDA approach. Comparing the wet‐chemically pre‐treated samples from Fig.3 with the thermally pre‐treated samples from Fig.5, an increased oxide
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growth at the interface can be observed for the Pt‐assisted PDA samples, which is independent of the substrate pre‐treatment. This results in a relatively high CET of ~ 10 nm
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and a low capacitance per area Cox_□ of ~ 0.35 μF/cm², as shown in Table1.
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In agreement with the XPS investigations, the lower Dit for Pt‐assisted PDA samples can be explained due to an enhanced growth of a GeO2 layer. The interface trap densities of the wet‐
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chemically and thermally pre‐treated surfaces stay nearly constant when they are annealed under same conditions, while a higher hysteresis width of the BHF pre‐treated sample with conventional PDA is notable. We expect that the broader hysteresis of the wet‐chemically pre‐treated sample is most likely induced by a larger amount of GeO formed by ALD, which desorbs from the interface during PDA [39]. The remaining dangling bonds at the interface possibly saturate during the oxygen annealing leading to the low Dit even in case of the BHF pre‐treated samples. Another explanation could be that more OH‐groups are dissociated in O and H, whereas interstitial H [40] may be captured into the Y2O3 structure inducing the broader hysteresis [32], while O remains at the interface continuing to saturate dangling bonds. In Table1, it is also shown that CET of the thermally pre‐treated surface is about 1.7 times higher than the CET of the wet‐chemically pre‐treated surface when compared to the samples with conventional PDA. We assume that after BHF pre‐treatment the Ge‐surface is H‐terminated [7, 10]. In this case more GeO is formed during ALD compared to the thermal
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pre‐treated samples as shown by XPS (Fig.2). The reduced CET of the BHF pre‐treated samples is most likely due to a stronger GeO volatilization followed by delayed interfacial GeO2 growth during oxygen annealing, which is also visible in the deconvoluted XPS spectra
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of Fig.2 (left).
In summary, ALD‐grown Y2O3 on n‐type (100)‐Ge was electrically characterized by means of
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CV‐ and IV‐measurements of W/TiN/Y2O3/n‐Ge and W/TiN/Pt/Y2O3/n‐Ge capacitors. XPS‐
measurements show that interfacial yttrium germanate is formed during the ALD process.
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The O2 PDA at 550 °C leads to an enhanced growth of interfacial GeO2 most likely inducing a strong improvement of the interface quality. In this work a remarkable low Dit is achieved with a 5 nm PVD deposited Pt‐layer on top of the gate oxide in conjunction with thermal
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annealing in oxygen. Notably, for simply BHF pre‐treated Ge samples, the Pt‐assisted catalytic PDA leads to a low Dit of 1.55*1011 eV‐1cm‐2, low hysteresis width of 94.5 mV, low
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leakage currents of 6.46*10‐9 A/cm2 and high breakdown voltage of 9.6 V. It turns out that along with the oxygen containing PDA also a PMA is necessary for reducing the interface
Acknowledgement
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traps significantly from 3.18*1011 eV‐1cm‐2 down to 1.04*1011 eV‐1cm‐2.
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This work is funded by the Austrian Science Fund (FWF), project № P24506 – N27. The „Zentrum für Mikro‐ und Nanostrukturen (ZMNS)“ and the "Gesellschaft für Mikroelektronik (GMe)" are gratefully acknowledged.
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Fig.1: XPS of the Ge2p core‐level of thermally pre‐treated and BHF pre‐treated Ge surfaces. No evidence of GeOx residuals are visible by XPS. The inset shows the Ge starting surface covered by native oxide.
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Fig.2: In‐situ XPS spectra of the Ge2p and the Y3d state (inset) of (c) pre‐treated Ge‐surface with
Y3d state of Si/Y2O3 as reference (b) as deposited Y2O3 and (a) annealed Y2O3 (O2 at 550 °C for 30
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sec) on wet‐chemically (left) and thermally (right) pre‐treated Ge surfaces.
Fig.3: CV‐ and JV‐characteristic of the wet‐chemical pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitors
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with Pt‐assisted PDA (a), and conventional PDA (b) in oxygen at 550 °C for 10 min. FGA and PMA each at 350 °C for 30 min were conducted on both samples.
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Fig.4: Leakage current mechanisms of the BHF pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitor with Pt‐assisted PDA. Fowler‐Nordheim (FN), direct tunnelling (DT) and Poole‐Frenkel (PF)
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regimes are identified and indicated. FN tunnelling is observed in the high bias region (7.14 V‐10 V), DT in the low bias region (0.37 V‐2.7 V) and PF emission in the middle bias region (3.4 V‐4.6 V).
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Fig.5: CV‐characteristic of the thermal pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitors
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with Pt‐assisted PDA (b, d) and conventional PDA (a, c) in oxygen at 550 °C for 10 min. All samples received a FGA at 350 °C for 30 min after the oxygen annealing. PMA was
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applied to the samples c) and d) only.
Table1: Measured electrical parameters of the wet‐chemically (BHF) and thermally (desorb) pre‐ treated surfaces of W/TiN/Y2O3/n‐Ge MOS capacitors with Pt‐assisted PDA (w. Pt) and conventional PDA (w/o Pt) in oxygen at 550 °C for 10 min. A subsequent FGA at 350 °C for 30 min was applied to all samples after the oxygen annealing. The utilization of a PMA at 350 °C for 30 min is indicated.
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[4] Y. Kamata, “High‐k/Ge MOSFETs for Future Nanoelectronics,” Materials Today, vol. 11, no. 1‐2, pp. 30 – 38, 2008. [5] A. Dimoulas, E. Gusev, P. C. McIntyre, M. Heyns, “Advanced Gate Stacks for High‐Mobility Semiconductors,” Springer Series in advanced microelectronics, Berlin Heidelberg, 2007. [6] Q. Xie, S. Deng, M. Schaekers, D. Lin, M. Caymax, A. Delabie, X.‐P. Qu, Y.‐L. Jiang, D. Deduytsche and C. Detavernier, “Germanium surface passivation and atomic layer deposition of high k dielectrics – a tutorial review on the based MOS capacitors,” Semiconductor Science and Technology, vol. 27, 074012 (14pp), 2012. DOI: 10.1088/0268‐1242/27/7/074012 [7] S. Sun, Y. Sun, Z. Liu, D.‐I. Lee, S. Peterson and P. Pianetta, “Surface Termination and Roughness of Ge(100) Cleaned by HF and HCl Solutions,” Applied Physics Letters, vol. 88, issue 2, p. 021903, 2006. DOI: 10.1063/1.2162699 [8] D. Bodlaki, H. Yamamoto, D.H. Waldeck, E. Borguet, “Ambient stability of chemically passivated germanium interfaces,” Surface Science, 543, 63‐74, 2003. DOI:10.1016/S0039‐6028(03)00958‐0 [9] B.‐Q. Xue, H.‐D. Chang, B. Sun, S.‐K. Wang, H.‐G. Liu, “The Impact of HCl Precleaning and Sulfur Passivation on the Al2O3/Ge Interface in Ge Metal Oxide Semiconductor Capacitors,” Chinese Physics Letters, vol. 29, no. 4, 046801, 2012. DOI: 10.1088/0256‐307X/29/4/046801 [10] S. Rivillon, Y. J. Chabal, F. Amy and A. Kahn, “Hydrogen passivation of germanium (100) surface using wet chemical preparation,” Applied Physics Letters, vol. 87, issue 25, p. 253101, 2005. DOI: 10.1063/1.2142084 [11] B. Onsia, T. Conard, S. De Gendt, M. Heyns, I. Hoflijk, P. Mertens, M. Meuris, G. Raskin, S. Sioncke, I. Teerlinck, A. Theuwis, J. Van Steenbergen and C. Vinckier, “A Study of the Influence of Typical Wet Chemical Treatments on the germanium Wafer Surface,” Solid State Phenomena Vols. 103‐104, pp. 27‐30, Trans Tech Publications, Switzerland, 2005. DOI:10.4028/www.scientific.net/SSP.103‐104.27 Page 15 of 18
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S0169-4332(16)30235-5 http://dx.doi.org/doi:10.1016/j.apsusc.2016.02.066 APSUSC 32584
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Received date: Revised date: Accepted date:
10-12-2015 4-2-2016 5-2-2016
Please cite this article as: C. Zimmermann, O. Bethge, K. Winkler, B. Lutzer, E. Bertagnolli, Improving the ALD-grown Y2 O3 /Ge interface quality by surface and annealing treatments, Applied Surface Science (2016), http://dx.doi.org/10.1016/j.apsusc.2016.02.066 This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.
Improving the ALD‐grown Y2O3/Ge interface quality by surface and annealing treatments
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C. Zimmermann1, O. Bethge1, K. Winkler1, B. Lutzer1 and E. Bertagnolli1 1 Institute of Solid State Electronics, Technische Universität Wien, Floragasse 7, 1040 Wien, Austria
Highlights
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• Investigation of interfacial mechanisms for hydrofluoric and thermal pre-treated Ge-surfaces • Improvement of interface trap density due to proper annealing treatments • Further improvement of interfacial and electrical properties due to catalytic acting thin platinum layer Abstract
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Metal Oxide Semiconductor capacitors are investigated, employing ALD grown Y2O3 as gate dielectric, and n‐type (100) germanium as channel substrate. The effect of post deposition
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annealing (PDA) in oxygen and forming gas atmosphere using a thin catalytically acting
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platinum (Pt)‐layer on the Y2O3/Ge interface is electrically analysed for buffered hydrofluoric (BHF) and thermally pre‐treated Ge‐surfaces.
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The Pt‐assisted PDA ensures even for BHF pre‐treated samples very low values for the interface trap density Dit of 1.55*1011 eV‐1cm‐2 and low leakage current densities J of <7*10‐9 A /cm2 outperforming conventional PDA treatments. The interfacial formation of GeO2 and Yttrium germanate after PDA is proven by using X‐ray Photoelectron Spectroscopy measurements.
Introduction
The successful use of silicon in Complementary Metal Oxide Semiconductor (CMOS) technology in recent decades was largely based on the existence of a stable intrinsic oxide and a high‐quality SiO2/Si interface. The progressive miniaturization of Si/SiO2 MOS transistors has induced a dramatically increase of the leakage current caused by the extremely thin SiO2. To overcome this issue the “High‐k + Metal Gate” (HKMG) technique was successfully implemented [1]. In addition, the relatively low charge carrier mobility of the Si
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channel used so far is considered as limiting factor for high‐speed CMOS devices. Germanium has indeed a high hole and electron mobility (3900 cm²/Vs; 1900 cm²/Vs), but several shortcomings like the thermodynamic instability (above of 400 °C) and the water solubility of the native germanium‐oxide prevented the successful implementation of germanium in
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CMOS devices [2‐4]. Therefore, some research for suitable cleaning and passivation‐ techniques was done to improve and stabilize the interface quality in Ge based HKMG stacks
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[5, 6].
Surface cleaning using hydrofluoric (HF), hydrogenbromid (HBr), hydrogenchlorid (HCl), and
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ammonium sulfide ((NH4)2S) provided partially the complete removal of GeOx and led to a hydrogen (H), chlorine (Cl) and sulfide (S) terminated Ge‐surface [7‐12]. Conventional cleaning methods with HF showed not only a rougher surface compared to HCl pre‐treated
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Ge‐surfaces [7], but also depending on the HF concentration a defective and deteriorated surface quality [13]. The research carried out by Xue et al. showed that with a cyclic HF/DI
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water dip a smoother surface can be achieved in comparison to a highly concentrated HF solution, which induce surface damage [9]. A complete removal of the native germanium‐ oxide by a thermal evaporation step at 360 °C in an ultrahigh vacuum UHV was demonstrated
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by Dimoulas et al., using reflection high‐energy electron diffraction (RHEED) measurement
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[14]. Prabhakaran et al. achieved an atomically clean Ge‐surface by thermally decomposing a thin oxide layer at about 430 °C to 450 °C, identified by XPS and UPS measurements [3, 15].
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In literature a combination of both methods, wet chemical pre‐treatment with a following thermal desorption step, is frequently reported. For example, Delabie et al. removed the natural germanium‐oxide initially by a HF solution followed by thermal desorption at 650 °C to remove O and C residues which arise after HF etching [7, 16]. Concerning a high quality surface passivation, an oxide free Ge‐surface or one of the Ge‐ oxides/nitrides (GeO2; Ge3N4; GeOxNy ...) combined with non‐native oxides like La2O3, Al2O3, HfO2 or Y2O3 exhibiting promising interface characteristics [5, 6, 17‐21]. It is also important that high‐k oxides form a good electrical transition with the semiconductor in terms of roughness and defects at the interface. Especially high‐k oxides from the rare earths elements, such as Y2O3, allow a lattice‐matched growth with only few lattice defects between semiconductor and oxide [22‐24]. For the deposition of thin high‐k oxide films, atomic layer deposition (ALD) is the method of choice due to ultra‐smooth and homogeneous film‐surfaces with highest step coverage [25]. In comparison, techniques such
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as reactive sputtering or metal organic chemical vapour deposition (MOCVD) produce uneven dielectric surfaces leading to charge trapping [26]. Dong and co‐workers reported that a porous Pt‐layer deposited on different metals is leading to an increased oxidation of the metals during an O2 annealing process which is induced by
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dissociated O2 [27]. Henkel et al. demonstrated a reduction of the interface trap density Dit to mid 10*1011 eV‐1 cm‐2 in ZrO2/La2O3/Ge capacitors by using the Pt‐assisted oxidation of the
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Ge/high‐k interface [28]. Up to now, the lowest Dit of 4.5*1010 eV‐1 cm‐2 was achieved in
Al2O3/GeO2/Ge capacitors by using an electron cyclotron resonance plasma formed GeO2 on
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a Ge‐surface pre‐treated by diluted HF [18]. Another promising passivation technique after HF (0.5 %) pre‐treatment, is using O2 plasma for growing high quality GeO2 leading to an interface trap density of 5*1011 eV‐1 cm‐2 in TiO2/HfO2/GeO2/n‐Ge capacitors [19]. By using a
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combined surface pre‐treatment of HF and thermal desorption at 650 °C, thermally grown GeO2 in HfO2/GeO2/Ge capacitors yield also to low Dit of 3*1011 eV‐1 cm‐2 [16].
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In this study, the effect of Pt‐assisted annealing in oxygen and forming gas atmosphere compared to conventional PDA annealing is discussed by using ALD grown Y2O3 on differently pre‐treated Ge‐surfaces. The native oxide is either initially wet chemically removed or
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measurements.
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thermally desorbed from the Ge‐surface. The interface is examined by means of in‐situ XPS‐
As metal gate a titan nitride/tungsten (TiN/W) stack is used with W acting as a good cover
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and conducting layer able to prevent an oxidation of the underlying TiN layer, which is employed due to a proper work function for pMOS devices.
Experimental
For the fabrication of the MOS‐capacitors antimony (Sb) doped (100) Ge with a resistivity of 4.9 to 5.9 Ωcm (MTI Corporation) was used as substrate. Two methods were used for the surface preparation (i) wet‐chemical treatment with a 3 min cyclical 15 sec NH4F/HF (7:1) / 15 sec DI‐water dip, denoted in the following as “BHF” and (ii) thermal surface treatment in an ultrahigh vacuum (UHV) chamber by heating the sample, denoted in the following as “desorb”. In order to analyse the semiconductor surface of remaining GeOx residues XPS‐ measurements were performed within 5 min after pre‐treatment. Subsequently, the samples were transferred into the ALD chamber (TFS 200, Beneq) within 1 min without breaking the
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vacuum. For this purpose a cluster tool is used consisting of ALD and XPS tool, which are connected by a vacuum transfer system with load lock access. As a metal organic precursor tris(methylcyclopentadienyl)yttrium kept at 150 °C was used, which reacts with water as an oxidizing agent to form Y2O3 on the surface and by‐products are purged by nitrogen. The
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growth rate of the as deposited yttrium oxide was measured to be 0.15 nm/cycle by using spectroscopic ellipsometry (J.A. Woollam). To analyse interfacial reactions of the as
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deposited Y2O3, the samples were transferred without breaking the vacuum for further XPS investigations.
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Subsequently, 50 cycles Y2O3 (~7.5 nm) were deposited onto the different pre‐treated Ge‐ surfaces for the fabrication of MOS capacitors and on one subset of samples a 5 nm platinum layer was sputtered (Von Ardenne) on the top of the as deposited oxide layer. All samples
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have been exposed to an O2 PDA for 10 min at 550 °C followed by forming gas annealing (FGA) at 350 °C for 30 min in a rapid thermal annealing (RTA) furnace (UniTemp). A metal
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stack of TiN (25 nm) and W (78 nm) was deposited for the circular shaped gate electrodes with a diameter of 100 µm which were lithographically patterned and structured by means of reactive ion etching (RIE) in SF6 / N2 plasma. As back contact a Ti/Au‐metallization was
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applied after Ar+ cleaning of the Ge backside. Finally, one part of the samples underwent a
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post metallization annealing (PMA) in forming gas at 350 °C for 30 min. Oxide and interface quality was evaluated via capacitance‐voltage (CV), conductance‐
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frequency (Gf) and current‐voltage (IV) measurements using a parameter analyser (4200‐SCS Keithley), a capacitance bridge (AH‐2700A Andeen Hagerling) and a probe station (Cascade MicroTech). Electrical properties like the oxide capacitance per area Cox_□, capacitance equivalent thickness CET, flatband‐voltage VFB and hysteresis width were extracted from the CV‐measurement. The CV‐curves were measured in a voltage range of ‐2 V to +2 V at different frequencies (1 MHz, 500 kHz, 100 kHz, 50 kHz, 10 kHz, 1 kHz, 100 Hz). The influence of a lossy dielectric interface layer or series resistance was eliminated by a correction formula after Kwa et al. [29]. The CET was calculated according to CET = ε0*3.9/ Cox_□, whereat the value of Cox_□ was taken from the 100 Hz CV‐curve in accumulation at +2 V. For the determination of the hysteresis width, the voltage values at the capacitance Cmin + (Cmax ‐ Cmin)/2 were taken from the forward and backward CV‐curve at 1 MHz and the flat band voltage was calculated by using the CVC‐program from Hauser et al. from the 1 MHz CV‐ curve [30]. Gf‐measurements were used for the calculation of the interface trap density Dit
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after the conductance method [31, 32] in a frequency range from 1 kHz to 10 MHz. Dit values were extracted close to the Ge mid‐gap state. Breakdown voltage Vbreak and leakage current density J were obtained by IV‐measurements. The value of the breakdown voltage was extracted from the IV‐measurement where a sudden increase of the current by several
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orders of magnitude occurs and the leakage current density was read‐off at 1V+VFB in forward bias.
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Chemical and interfacial properties of the films were examined by XPS using Al Kα as X‐ray source (Phoibos 150 MCD‐9 detector, Specs). The binding energies of all XPS spectra were
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calibrated for the C1s and Ge2p states. For the fitting of the peak positions the Gaussian‐ Lorentzian line shape was used, provided by the analysing tool Casa XPS (VAMAS Processing Software).
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Results and Discussion
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(A) XPS analysis
After the pre‐treatment of the Ge surface, XPS‐measurements (Fig.1) were performed in
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order to analyse the surface of GeOx residues.
Fig.1: XPS of the Ge2p core‐level of thermally pre‐treated and BHF pre‐treated Ge surfaces. No evidence of GeOx residuals are visible by XPS. The inset shows the Ge starting surface covered by native oxide.
The XPS‐measurements show for both preparation methods neither a GeO2‐peak at 1220.6 eV nor a GeOx (x <2) peak at 1219.3 eV [15]. This suggests that the substrate oxide of the Page 5 of 18
starting surface (Fig.1, inset) was successfully reduced below the XPS detection limit of 0.1 atom%. Such removal of the native germanium‐oxide by thermal evaporation is already well known [14]. Concerning the BHF treatment for GeOx removing, no unambiguous evidence can be found in literature. It is reported by XPS study that no oxide after hydrofluoric (HF)
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pre‐treatment can be found [5] , while it was also contrary reported that non‐negligible sub‐ oxides (~ 5 Å) remain on the surface after HF etching, measured with second harmonic
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generation (SHG) [5, 8].
Deposited oxide thickness after 10 ALD cycles was measured by ellipsometry to be 1.58 nm
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for the BHF pre‐treated surface and 2.28 nm for the thermal pre‐treated surface. The corresponding in situ XPS spectra of the Ge2p and Y3d state are shown in Fig.2 for the wet‐
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chemically (left) and thermally pre‐treated (right) Ge‐surfaces.
Fig.2: In‐situ XPS spectra of the Ge2p and the Y3d state (inset) of (c) pre‐treated Ge‐surface with Y3d state of Si/Y2O3 as reference (b) as deposited Y2O3 and (a) annealed Y2O3 (O2 at 550 °C for 30 sec) on wet‐chemically (left) and thermally (right) pre‐treated Ge surfaces.
10 cycles of as deposited Y2O3 (Fig.2b, left), forms a broad shoulder in the Ge2p spectrum of the wet‐chemical treated surface which indicates the growth of GeO (at 1218.88 eV) and YGeO (at 1219.59 eV) on the differently pre‐treated starting surfaces (Fig.2c). Notably, in the Page 6 of 18
as deposited samples significant formation of interfacial YGeOx is apparent also indicated by the shift of the Y3d peak (Fig.2 insets) to higher binding energy (BHF: 156.92 eV/desorb: 156.93 eV) compared to Y2O3 deposited on Si (156.2 eV, Fig.2c inset) or compared to data as reported elsewhere (156.6 eV) [33]. In the case of the thermally pre‐treated sample (Fig.2b,
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right), only a slight growth of GeO and YGeO is detected. The GeO vanishes by applying PDA (Fig.2a) at 550 °C for 30 sec and the formation of a significant yttrium germanate phase
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(YGeOx) as well as an additional growth of GeO2 is observed. Wang et al. reported that during the process of annealing, GeO desorbs from the interface and is trapped into the oxygen
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deficient YGeOx leading to an oxygen densification, which suppresses GeO volatilization and maintains the quality of Ge/GeO2 interfaces [24]. The peak deconvolution in Fig.2a reveals a more pronounced YGeO peak of the wet‐chemically pre‐treated sample in comparison to the
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thermally pre‐treated sample. It seems that during the annealing a larger amount of GeO desorbs from the interface of the wet‐chemically pre‐treated sample and incorporates into
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the yttrium germanate layer inducing a more pronounced germanate phase. In the case of the thermally pre‐treated sample, however, less GeO desorbs from the interface resulting in
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an increased growth of interfacial GeO2. The good passivation properties of the grown GeO2
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layer are proven in the electrical characterization part of this study.
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(B) Electrical characterization
Electrical characterization was carried out based on W/TiN/Pt/Y2O3/n‐Ge and W/TiN/Y2O3/n‐ Ge capacitors. For the fabrication of the samples, two different methods of surface preparation were used. On both sets of samples, ALD grown Y2O3 of 50 cycles resulted in a layer thickness of ~7.5nm determined by means of ellipsometry. Measurements of several samples show a small deviation in thickness of only +/‐ 0.24 nm. In the case of the BHF pre‐ treated samples, especially the influence of a thin catalytically acting Pt‐layer in conjunction with a PMA on the electrical properties has been studied. Also the additional effect of PMA was examined on the basis of the thermally pre‐treated samples. From the CV‐characteristics of the gate stacks with wet‐chemically pre‐treated Ge‐surfaces, shown in Fig.3(a, b) left, we can conclude that a Pt‐assisted PDA at 550 °C reduces the hysteresis width which indicates a lower amount of oxide charges. In addition, the flat band
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voltage is positively shifted compared to a sample with conventional PDA. This effect can be explained by an increased amount of oxygen induced by the PDA, which decreases the density of fixed oxide charges leading to a shift of the flat band voltage [34]. Thereby, also a reduction of the Dit from 2.34*1011 eV‐1cm‐2 down to 1.55*1011 eV‐1cm‐2 was achieved. An
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improvement in the leakage current density by about two orders of magnitude, and a twice as high breakdown voltage is also achieved by Pt‐assisted PDA. It is worth mentioning here
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that the IV‐measurements were made at multiple spots distributed over the fabricated
sample. In the case of the Pt‐assisted PDA sample the JV‐characteristic shows an almost
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homogeneous behaviour over different spots, whereas those of the sample with
conventional PDA strongly differ for individual spots. Due to these discrepancies in leakage current it is generally difficult to make clear statements about it. However, in principle it can
an
be said that due to the conventional PDA less reinforced oxide growth at the Y2O3/Ge interface occurs and therefore a lower oxide thickness results in higher leakage current.
M
Ac ce p
te
d
Page 8 of 18
ip t cr us an M d te
Ac ce p
Fig.3: CV‐ and JV‐characteristic of the wet‐chemical pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitors with Pt‐assisted PDA (a), and conventional PDA (b) in oxygen at 550 °C for 10 min. FGA and PMA each at 350 °C for 30 min were conducted on both samples.
A further method to estimate the quality of the oxide is the determination of its conduction mechanisms [35]. Based on the sample in Fig.3a, three different conduction mechanisms are observed (Fig.4) within the Pt‐assisted PDA Y2O3‐stack deposited on a wet‐chemical pre‐ treated Ge‐substrate, whereby Fowler‐Nordheim (FN) tunnelling and direct tunnelling (DT) are most significant. While for high bias (>7 V) FN tunnelling is the dominant mechanism, DT is evident for the low bias region (<2.7 V). Also Poole‐Frenkel (PF) emission is observed in the middle bias region (3.4 V‐4.6 V), indicating that the leakage current in this voltage range is governed by a trap assisted mechanism [35].
Page 9 of 18
ip t cr us an
Fig.4: Leakage current mechanisms of the BHF pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitor with Pt‐assisted PDA. Fowler‐Nordheim (FN), direct tunnelling (DT) and Poole‐Frenkel (PF)
M
regimes are identified and indicated. FN tunnelling is observed in the high bias region (7.14 V‐10 V), DT in the low bias region (0.37 V‐2.7 V) and PF emission in the middle bias region
te
d
(3.4 V‐4.6 V).
In Fig.5, CV‐characteristics for thermally pre‐treated W/TiN/Y2O3/n‐Ge MOS‐capacitors are
Ac ce p
shown employing Pt‐assisted PDA (Fig.5b, d) and conventional PDA (Fig.5a, c) at 550 °C for 10 min, as well as additional PMA (Fig.5c, d) treatments. Comparing the PDA sample in Fig.5a with the Pt‐assisted PDA sample in Fig.5b where no PMA is provided, only minor differences in the electrical parameters can be obtained, whereby the Dit is slightly reduced from 4.91*1011 eV‐1cm‐2 to 3.18*1011 eV‐1cm‐2. By using a PMA, the Dit of the Pt‐assisted PDA sample in Fig.5b can be reduced from 3.18*1011 eV‐1cm‐2 to a low value of 1.04*1011 eV‐1cm‐2 which is shown in Fig.5d. Additionally, the flat band voltage can be reduced from ‐468 mV to ‐56.3 mV and the hysteresis width from 228 mV to 59.71 mV at constant CET and Cox_□. For the sample with conventional PDA, shown in Fig.5a, only a slight reduction of Dit from 4.91*1011 eV‐1cm‐2 to 1.94*1011 eV‐1cm‐2 (Fig.5c) is observed whereby a noticeable reduction of VFB and hysteresis width have been achieved.
Page 10 of 18
ip t cr us an M d te
Ac ce p
Fig.5: CV‐characteristic of the thermal pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitors with Pt‐assisted PDA (b, d) and conventional PDA (a, c) in oxygen at 550 °C for 10 min.
All samples received a FGA at 350 °C for 30 min after the oxygen annealing. PMA was
applied to the samples c) and d) only.
In Table1 all measured properties of the examined samples are depicted.
Sample
Dit
CET
J(VFB+1V)
Vbreak
VFB
Hysteresis
Cox_□
1/(eV*cm²)
(nm)
(A/cm²)
(V)
(mV)
(mV)
(µF/cm²)
BHF w. Pt (PMA)
1.55e11
10.23
6.46e‐09
9.6
‐6.66
94.47
0.34
BHF w/o Pt (PMA)
2.34e11
4.61
1.52e‐07
4.73
‐253.1
606.49
0.75
Desorb w. Pt (PMA)
1.04e11
9.89
6.07e‐09
8.66
‐56.26
59.71
0.35
Desorb w. Pt
3.18e11
9.89
‐
‐
‐468.3
228.12
0.35
Desorb w/o Pt (PMA)
1.94e11
7.67
8.52e‐09
11.5
‐115.9
172.83
0.45
Page 11 of 18
Desorb w/o Pt
4.91e11
7.75
‐
‐
‐307.6
294.96
0.45
Table1: Measured electrical parameters of the wet‐chemically (BHF) and thermally (desorb) pre‐ treated surfaces of W/TiN/Y2O3/n‐Ge MOS capacitors with Pt‐assisted PDA (w. Pt) and conventional PDA (w/o Pt) in oxygen at 550 °C for 10 min. A subsequent FGA at 350 °C for 30 min was applied to all
ip t
samples after the oxygen annealing. The utilization of a PMA at 350 °C for 30 min is indicated.
For the samples with conventional PDA and PMA (Fig.3b and Fig.5c) Dit's in the range of
cr
2.34*1011 eV‐1cm‐2 for BHF and 1.94*1011 eV‐1cm‐2 for thermally pre‐treated Ge surfaces are
us
achieved, comparable to values reported elsewhere [21, 23, 36‐38]. The CET is determined between 4.5 nm (BHF‐samples) and 7.6 nm (desorb samples) and is well below the values of the Pt‐assisted PDA samples (10.23 nm and 9.89 nm) also indicating a stronger growth of
an
interfacial GeO2 by the Pt‐assisted PDA approach. Comparing the wet‐chemically pre‐treated samples from Fig.3 with the thermally pre‐treated samples from Fig.5, an increased oxide
M
growth at the interface can be observed for the Pt‐assisted PDA samples, which is independent of the substrate pre‐treatment. This results in a relatively high CET of ~ 10 nm
d
and a low capacitance per area Cox_□ of ~ 0.35 μF/cm², as shown in Table1.
te
In agreement with the XPS investigations, the lower Dit for Pt‐assisted PDA samples can be explained due to an enhanced growth of a GeO2 layer. The interface trap densities of the wet‐
Ac ce p
chemically and thermally pre‐treated surfaces stay nearly constant when they are annealed under same conditions, while a higher hysteresis width of the BHF pre‐treated sample with conventional PDA is notable. We expect that the broader hysteresis of the wet‐chemically pre‐treated sample is most likely induced by a larger amount of GeO formed by ALD, which desorbs from the interface during PDA [39]. The remaining dangling bonds at the interface possibly saturate during the oxygen annealing leading to the low Dit even in case of the BHF pre‐treated samples. Another explanation could be that more OH‐groups are dissociated in O and H, whereas interstitial H [40] may be captured into the Y2O3 structure inducing the broader hysteresis [32], while O remains at the interface continuing to saturate dangling bonds. In Table1, it is also shown that CET of the thermally pre‐treated surface is about 1.7 times higher than the CET of the wet‐chemically pre‐treated surface when compared to the samples with conventional PDA. We assume that after BHF pre‐treatment the Ge‐surface is H‐terminated [7, 10]. In this case more GeO is formed during ALD compared to the thermal
Page 12 of 18
pre‐treated samples as shown by XPS (Fig.2). The reduced CET of the BHF pre‐treated samples is most likely due to a stronger GeO volatilization followed by delayed interfacial GeO2 growth during oxygen annealing, which is also visible in the deconvoluted XPS spectra
ip t
of Fig.2 (left).
In summary, ALD‐grown Y2O3 on n‐type (100)‐Ge was electrically characterized by means of
cr
CV‐ and IV‐measurements of W/TiN/Y2O3/n‐Ge and W/TiN/Pt/Y2O3/n‐Ge capacitors. XPS‐
measurements show that interfacial yttrium germanate is formed during the ALD process.
us
The O2 PDA at 550 °C leads to an enhanced growth of interfacial GeO2 most likely inducing a strong improvement of the interface quality. In this work a remarkable low Dit is achieved with a 5 nm PVD deposited Pt‐layer on top of the gate oxide in conjunction with thermal
an
annealing in oxygen. Notably, for simply BHF pre‐treated Ge samples, the Pt‐assisted catalytic PDA leads to a low Dit of 1.55*1011 eV‐1cm‐2, low hysteresis width of 94.5 mV, low
M
leakage currents of 6.46*10‐9 A/cm2 and high breakdown voltage of 9.6 V. It turns out that along with the oxygen containing PDA also a PMA is necessary for reducing the interface
Acknowledgement
te
d
traps significantly from 3.18*1011 eV‐1cm‐2 down to 1.04*1011 eV‐1cm‐2.
Ac ce p
This work is funded by the Austrian Science Fund (FWF), project № P24506 – N27. The „Zentrum für Mikro‐ und Nanostrukturen (ZMNS)“ and the "Gesellschaft für Mikroelektronik (GMe)" are gratefully acknowledged.
Page 13 of 18
Fig.1: XPS of the Ge2p core‐level of thermally pre‐treated and BHF pre‐treated Ge surfaces. No evidence of GeOx residuals are visible by XPS. The inset shows the Ge starting surface covered by native oxide.
ip t
Fig.2: In‐situ XPS spectra of the Ge2p and the Y3d state (inset) of (c) pre‐treated Ge‐surface with
Y3d state of Si/Y2O3 as reference (b) as deposited Y2O3 and (a) annealed Y2O3 (O2 at 550 °C for 30
cr
sec) on wet‐chemically (left) and thermally (right) pre‐treated Ge surfaces.
Fig.3: CV‐ and JV‐characteristic of the wet‐chemical pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitors
us
with Pt‐assisted PDA (a), and conventional PDA (b) in oxygen at 550 °C for 10 min. FGA and PMA each at 350 °C for 30 min were conducted on both samples.
an
Fig.4: Leakage current mechanisms of the BHF pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitor with Pt‐assisted PDA. Fowler‐Nordheim (FN), direct tunnelling (DT) and Poole‐Frenkel (PF)
M
regimes are identified and indicated. FN tunnelling is observed in the high bias region (7.14 V‐10 V), DT in the low bias region (0.37 V‐2.7 V) and PF emission in the middle bias region (3.4 V‐4.6 V).
d
Fig.5: CV‐characteristic of the thermal pre‐treated W/TiN/Y2O3/n‐Ge MOS capacitors
te
with Pt‐assisted PDA (b, d) and conventional PDA (a, c) in oxygen at 550 °C for 10 min. All samples received a FGA at 350 °C for 30 min after the oxygen annealing. PMA was
Ac ce p
applied to the samples c) and d) only.
Table1: Measured electrical parameters of the wet‐chemically (BHF) and thermally (desorb) pre‐ treated surfaces of W/TiN/Y2O3/n‐Ge MOS capacitors with Pt‐assisted PDA (w. Pt) and conventional PDA (w/o Pt) in oxygen at 550 °C for 10 min. A subsequent FGA at 350 °C for 30 min was applied to all samples after the oxygen annealing. The utilization of a PMA at 350 °C for 30 min is indicated.
Page 14 of 18
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