In-situ processing of semiconductors by combining MBE, lithography, pattern transfer, implantation and annealing

313

Microelectronic Engineering 9 (1989) 313-320 North-Holland

IN-SITU PROCESSING LITHOGRAPHY,

PATTERN

OF

SEMICONDUCTORS BY TRANSFER, IMPLANTATION

COMBINING MBE, AND ANNEALING

H. Ahmed Microelectronics Research Laboratory, Department of Physics, Cambridge University, Cambridge Science Park, Milton Road, Cambridge CB4 4FW.

Research in the physics of low dimensionality and for future optoeletronics requires the fabrication of ultra-small structures and multiple layers of semiconductor material overgrown eptaxially on implanted layers. The properties of such structures are degraded by exposure to air and in-situ processing in a vacuum environment is considered desirable. The important features of proposed systems which incorporate MBE, focused ion and electron beams, gas assisted etching and selective metal deposition are reviewed in this paper.

1

Introduction

The recent ,mwth of research into semiconductor structures and devices which show some form of ‘quantum’ effect has led to a reappraisal of the fabricaiion techniques develoned for silicon integrated circuit manufacture. The main steps in the manuf&turing process for integrated circuits such as patterning of the wafer surface, introduction of impurities, etching of selected parts and the growth of appropriate layers on the patterned surfaces are still relevant. However the indirect methods generally used for patterning, such as photo-resist on the wafer to define patterns, solvents to clean surfaces, various chemical compounds to etch and chemical vapours to deposit layers are no longer These processes require the appropriate techniques. frequent exposure of the wafer surface to air which causes surface oxidation or other form of deterioration of the surface condition and also leads to contamination of the surface by dust particles. Since the quality of the surface layers and interfaces must be of a much higher standard and the sizes of the artefacts needed for the proposed studies must be much smaller than required hitherto new approaches to fabrication must be investigated. In-situ processing seeks to develop direct fabrication processes that can be carried out either in a vacuum environment or in an acceptable gaseous environment. In this paper the viability of such processing is considered for the fabrication of nanometric-scale structures for effects which occur in investigating ‘quantum’ low-dimensionality transport studies. To observe these effects the semiconductor layers must be free of contaminants and it must be possible to grow overlayers with very small degrees of crystalline mismatch and very few dangling bonds. Layer thickness must also be accurately controlled since layers as thin as OSnm must be grown compared with the minimum layer thickness of a few tens of nanometres required for the gate oxide in a typical silicon integrated circuit. The best available technique for such layer growth is molecular beam epitaxy (MBE). Doping of layers and compositional changes in the layers The can be achieved in the conventional MBE process. fabrication of patterns in such layers and the introduction of impurities in selected regions presents a challenge if it is to be carried out in a all-vacuum environment. Selective doping of certain areas to form lateral microstructures is only possible by implantation methods. The two 0167.9317/89/$3.50

possibilittes are either to pattern a resist, compatible with the MBE process, and to use a broad-beam ion implanter to dope the exposed area or to use focused ion beam implantation. The anealing of the ion implantation damage is possible using rapid thermal processes. Other beam methods and dry processing methods are required to implement the complete fabrication sequence. 2

Nanometre scale structures for IOW dimensionality studies.

The basic structures required for low dimensionalitv , electron transport studies have lateral sizes and layer thicknesses that are 10 to 100 times smaller than those required for silicon integrated circuits. Typically for low temperature studies at aroundlK the conducting channel length must be -O.lum. With such small sizes several structures have demonstrated quantization effects in measurements of conductance, magnetoresistance Hall resistance, etc. Fine metallic and semiconducting wires, thin channels in the 2DEG formed in the GaAs: Al GaAs heterostructure and ring structures for investigating the Aharonov-Bohm effect in metals or the 2DEG are some examples of structures that have been studied. A number of techniques have been evolved for forming these structures. The most direct process is to use e-beam lithography to define the structure in resist followed by dry etching to create mesas on insulating or a semi-insulating substrates. A lift-off process may also be used to form the structure in a metal defined in resist. Indirect methods for forming these structures have also been implemented. Many researchers have been working in this field and a few examples from the author’s laboratory are presented to illustrate the fabrication need. A split-gate device/l] can be used to squeeze a channel by changing the depletion width as shown in Fig l(a). This type of structure has the advantages that it does not have to be fabricated with very small sizes to explore one-dimensional transport and its effective size may be changed electrically over a wide range by applying gate voltages. A loop can also be formed in a 2DEG by forming a structure of the type shown in Fig.l(b) which was used to obtain 18% oscillations in the loop resistance[2,3] and a short split-gate device as shown in Fig. 1(c) can be used to investigate ballistic transport in high mobility material [4]. Developments of the ideas have led to the double

@ 1989, Elsevier Science Publishers B.V. (North-Holland)

H. Ahmed 1 In-situ processing of semiconductors Be (40 to 100keV)

.........

annel

___=.Scan direction

undoped GaAs

Short Split-Gate Mesfet (b)

Split-Gate Mesfet (a)

Fig.2

Double Split-Gate Device (cl

Depleted / PDEG

Quantum

Box-Gate

Device

(d)

/

Auxiliary Gate

(a) Unique doping profile obtained in GaAs by scanning an ion beam while varying its energy. (from Hashimoto and Miyauchi [8]). (b) Narrow conducting Ga.As channel formed by ion implantation with a FIB system to increase the resistance of adjacent confining regions (from Hiramoto et al. [9]).

short split-gate structure Fig.l(d) [S] and the ‘quantum’ box for investigating zero-dimensional transport Fig. l(e) [6]. These two-terminal devices demonstrate significant effects which may be used effectively in device configurations if control electrodes could be devised and fabricated in these structures. An example of a conaol electrode is shown in Fig. 2(f) in which one arm of an A-B ring may be squeezed further than the other by applying different voltages to the cross-arms of the structure. So far these structures have been fabricated by sequential processes carried out in several different processing systems. Better results are likely to come from in-situ processing which avoids degradation of surfaces and enables more direct fabrication processes to be employed.

Definition of in-situ processing system 3 Subsidiarv Control Gates on an Aharonov-Bohm Loop Layer growth is best achieved by using MBE. Layers are Using Thick Dielectric deposited epitaxially on appropriate substrates, the (f) composition of the layer can be changed abruptly without interupting the vacuum, dopants can be introduced and layer thickness can be controlled accurately. P particularly _ _._ important layered structure is the GaAs:AlGaAs heterostructure to form a 2DEG. Other important layers are of structures with which low Fig. 1 Examples superlattices, thin epitaxial silicon layers or SiGe layers. dimensionality transport phenomena may be Layers with high mobilities around 106cm2V-s at 4K and investigated. These structures use a bias-induced very few defects can be grown in many commercial depletion region formed under the gates to squeeze systems and these are of sufficient quality for ‘quantum’ the channel in a high mobility ZDEG. effects to be investigated. Aharonov-Bohm Loop in PDEG under a Gate Structure (e)

315

H. Ahmed /In-situ processing of semiconductors

Layer growth must be combined with means for making lateral microstructures of nanometre-scale linewidths. These may be formed by a variety of lithographic methods but the most suitable technique for in-situ work is a focused ion beam (FIB) system attached to the MBE system. This system can be. used in a number of ways to make changes in the uniform layers produced by MBE so that lateral confinement of the in-plane properties of the layer is achieved. A typical FIB system has a beam diameter of 0.05 to 0.1ltn-1, beam energy of 100 to 200keV and a beam current density of 3 to 5A.cmm2. Ion sources of Ga, Be, Si, B and As and several other materials are available so that the technologically important dopants for both the most commonly used semiconductors, GaAs and Si, can be implanted. With this system localised regions gratings, grids or arbitrary patterns of implanted areas can be formed. Ions can be implanted with doping concentration tailored along the length of the implantation region [7], or adjacent regions of n-type and p-type can be formed by ion implantation. The energy may be varied along the implant track to give novel doping profiles [8] (Fig. 2(a)). Selected areas can be sputtered to form mesas of active material on a semi-insulating substrate and regions can be selectively disordered to leave fine conducting wires in which dimensionality effects can be observed [9] (Fig.2(b)).

The advantage of in-situ overgrowth of layers is best illustrated by the results reported by Takamori et al. [ll] reproduced in Fig.4 where they show the dip in the PL intensity at the interface for GaAs overgrowth when the interface region is exposed to air compared with in-situ growth. Any surface grown by MBE and exposed to air is degraded resulting in carrier depletion and high resistivity at the surface. In-situ overgrowth avoids the problems [ 111. 4

Limitations

of in-situ

FIB : MBE systems

Several important limitations of focused ion beam systems

. Direction

of PL measurement

Be implant 1El 3cm’ GaAs sub

Etching can be enhanced by gas assistance of a focused ion beam to make gratings or grids in materials and focused ion beams can also be used to deposit material selectively on the surface of a substrate. Another application of the etching capabilities of ion beams is in micro-sectioning of layers to reveal the cross-section of the device [IO]. Maskless ion implantation can be used for three-dimensional doping of structures in III-V compound semiconductors and a 160 keV GaAs multilayer structure has been formed with selected area Si++ doping overgrown with Qtrn thick GaAs and the overgrown layer again doped selectively with Be+ 80 keV ions as shown in Fig. 3. This complex layered structure which has its finely patterned dopants alined vertically as well as laterally with respect to each other is an elegant example of the versatility of a combined FIB:MBE system [ 1 I]. Focused ion beam research has been reviewed by Melngailis [ 121.

Fig. 3 Cross-section schematic representation of a multilayer structure in GaAs implanted with alined Be and Si beams in a FIB system (as reported by Hashimoto and Miyauchi [8]).

Fig. 4 Localised Be implant in GaAs, with overgrowth to form a multilayer, and PL measurements showing the degradation of the interface when it is &posed to air rather than overgrown in situ. Both the implanted and the unimplanted regions are degraded.

H. Ahmed / in-situ processing of semiconductors

316

incorporated with MBE systems must be overcome. The beam landing energy is too high in instances where very thin layers must be patterned. Since the extraction voltage for metal ion sources is around 10 kV this limitation can only be overcome by using a retarding electrode arrangement in the final stage of the ion optical column design so that the beam is decelerated before it lands on the substrate. Work on this arrangement has been reported [13,14]. The landing energy can be reduced to < 1keV with some loss of resolution because the probe diameter increases. For high resolution FIB lithography the working distance between the substrate and the final lens or deflector must be small (about 10 mm). This makes it difficult to attach such a system directly to an MBE chamber where multiple sources, shutters and substrate holders must be incorporated. The difficulty is overcome by using a wafer track to transport the wafer between the growth system and the beam column or other processing areas. A schematic diagram of a proposal for an in-situ processing system is shown in Fig. 5 which can be used in a flexible manner to fabricate structures.

Combined e-beam i-beam

system

Another limitation of focused ion beams is that it is difficult to overlay patterned levels using ion beam lithography. The ion beam damages areas over which it is scanned and any registration marks on the surface have to be used with care otherwise the accuracy of registration is impaired because of damage to the marks. Furthermore it is only possible to detect registration marks that have been buried under an overgrown layer if the layer is very thin because of the low penetration of ion beams. The registration marks have to be exposed before each stage of alignment and this is impractical in any in-situ processing system. A method of overcomine this limitation has been uronosed 1151. It requires the use of a dual electron and ion beam column in which two beams may be generated on the same optic axis as shown in the first column of Fig. 5. In such a system the electron beam may be used for registration mark detection before the ion beam is used to carry out the active processing of the layer. This system can also be used to examine fabricated structures with the electron beam before the substrate is removed from the vacuum system.

Rapid thermal e-beam processing

I

Beam assisted metal deposition

e-beam

e-beam

registration

registration

Fig. 5 Proposed arrangement for a comprehensive and flexible in-situ fabrication system using focused beams of ions and electrons, with registration capability and with metal deposition and dry etching. A combined ion and electron beam system overcomes many problems associated with FIB processing of layers.

.

_

317

H. Ahmed /In-situ processing of semiconductors

detector

Fig. 6

Back-wafer registration scheme showing initialization target for co-registration of the two beams on thefront and back surfaces of the wafer.

Another approach to solving the problems of registration is to use the back surface of the wafer for registration [16]. This method is also illustrated in Fig. 5. A wafer which is polished on both sides is prepared with registration marks on the back surface. These can be detected using an electron beam system incident on the back and subsequently all patterning on me upper surface may be carried out with the upper beam using positional references from the lower beam after the two beams have been initialised using a common beam registration pattern (Fig.6). Sub-O.5 micron registration accuracy has been achieved with such an arrangement. 5

In-situ rapid thermal processing

In-situ thermal processing does not offer any great difficulty because rapid thermal techniques using lamps, lasers or electron beams have become available. The wafer can be tracked into an appropriate chamber where the energy source may be turned on. These processing system can be easily attached to a UHV environment and also have the advantage that they are very rapid so that layers may be processed without excessive diffusion of implanted dopants. Processing at temperatures around 1000 “C in timescales around 10s can be carried out with lamp systems [17]. Millisecond anneal times have been achieved using multiple electron beam sources 1181. These processes can also be used to improve layer quality by annealing crystalline defects, ion implants can be activated and metallic contacts can be annealed.

6

In-situ

etching

In-situ etching remains a significant problem. The requirement is for a highly localised etching method which does not damage the substrate. Conventional drv etchine techniques using gaseous sources are only s&able fo; attachment to in-situ processing systems via intermediate cleaning chambers before the wafer is returned to the UHV regime. It is possible to track the substrate into an appropriate chamber via isolating valves. A multiple chamber system in which reactive ion beam etching may be carried out starting from a ultra high-vacuum base has been reported by Asakiwa and Sugata rl9]. Their system in Fig. 7 shows a five chamber system in which RIBE is obtained with an electron-cyclotron-resonance plasma source, a cleaning chamber and other chambers are used for monitoring the surface condition with reflection high energy electron diffractin and Auger analysis. The deposition chamber was used for in-situ metallization to form Schottky diodes. With this system GaAs and AlGaAs surfaces were prepared which werefree from the damage often associated with dry etching and also free from surface contamination layers. Pig. 7(aj shows Auger electron spectra before and after cleaning and Fig. 7(b) shows the imnrovement in the measured c&er profile after cleaning. If-such systems are incorporated into a fully in-situ process then it is essential to have a preparation chamber in which thorough cleaning of the substrate may be carried out by techniques such as the radical beam method reported by Asakawa so that it is not contaminated during subsequent processing in the MBE system [20].

318

H. Ahmed 1 In-situ processing of semiconductors

Large area etching requires the use of a protective layer on parts of the substrate and special electron or ionsensitive resists must be deposited and patterned in-situ before the etching process is carried out. Focused ion beams do not require intermediate resist processes but there are problems with local&d damage because of the high beam energy and also from the re-deposition of material initially removed by the ion beam. Gas assisted etching with a focused ion beam can enhance the etching rate significantly and reduce the re-deposition of material [21]. Further delveopment of low energy gas-assisted etching with FIB is required for a satisfactory process. Electron beam assisted etching is also being investigated as a possible alternative. ,.

.* -,i,

,

05 oem

Fig. 7

, , , 10

hnml

(a) Schematic diagram of a multiple chamber etching system containing RIBE with an ECR plasma source, preparation, cleaning and analysis chambers. (b) Auger spectrum after radical beam cleaning showing virtually complete removal of C and 0 peaks. (c) Carrier profile of GaAs interface with overgrown layer showing the considerable improvement resulting from H radical cleaning after exposure to air (from Asakawa et al., 1261).

Fig. 8 Schematic diagram of a selective deposition system using FIB and a gas nozzle source (Harriott and Vasile 12.51).

H. Ahmed fin-situ processing of semiconductors

7

Metal Deposition

Metal layers are required to form inter-connecting tracks between smctures and for contact pads. This step can often be carried out externally if the sensitive surface has been protected by an overgrown layer. However, in some cases in-situ deposition is desirable. Conventional metal deposition techniques can be used for in-situ fabrication processes as in the case of dry etching if an MBE system compatible resist layer such as the rare earth fluorides can be patterned by electron or ion beams. Metal can be evaporated on the surface by conventional thermal evaporation before the patterning and subsequently etched to form conducting tracks and contact pads. There are again problems with this approach concerned with finding suitable resist technology and resolution is inadequate. An alternative approach is direct writing of metal tracks by laser assisted deposition of metal from a gas phase. The deposition of W lines from WF, and H gas mixtures under laser irradiation has been reported [2& Electron beam induced localised deposition of Si tracks from SiH2 Cl2 gas has also been reported [23] and several different materials have been deposited using focused ion beam exposure of gases [24].

319

All these methods are capable of being incorporated into a comprehensive in-situ processing system so that the fabrication process may be completed in a vacuum environment. A process for focused ion beam deposition of opaque carbon films is described by Harriott and Vasile [25], with a system arranged as shown in Fig. 8. 8

Conclusion

The fabrication of lateral microstructures with nanometre-scale line widths in very high quality semiconductor layers wihout degrading the quality of the layers and interfaces opens the way towards new quantum effect structures in which 2D, 1D and zero dimensionality The construction of a studies may be carried out. comprehensive in-situ processing system for optoelectronics research has been reported [20]. This system illustrated in Fig. 9 has pioneered future developments in the fabrication of other devices by in-situ methods.

Ion beam control/wrlrmg

Fig. 9 Schematic diagram of the most comprehensive in-situ system constructed so far; the system was developed for optoelectronics research. MBE, FIB, annealing, etching, and sample preparation chambers are all interconnected in a UHV system environment. This system has demonstrated the considerable advantages to be gained by not exposing the inte$ace to air before overgrowth is carried out. ( Courtesy Dr. H. Hashimoto Fujitsu Ltd.)

H. Ahmed / In-situ processing of semiconductors

320 Acknowledgements The contribution Semiconductor acknowledged.

of members Physics

of the Microelectronics Research Groups

and are

18. D.A. Smith, R.A. McMahon, H.Ahmed and D.J. Godfrey, Mat. Res. Sot. 100,725 (1988).

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2. 3.

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5.

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6.

C.G. Smith, M. Peuner, H. Ahmed, J.E.F. Frost, D.G. Hasko, D.C: -Peacock, D.A. Ritchie and G.A.C. Jones, J. Phys. C: Solid State Phys. 21, L893 (1988).

7.

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8.

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9.

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A

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22. D. Bauerle, T. Szorenyi, G.Q. Zhang, K. Piglmayer, M. Eyett and R. Kullmer in Emerging Technologies for In Situ Processing D.J. Ehrlich and V.T. Nguyen (eds.) p-33 (1988). 23. S. Matsui and M. Mito, Submitted Lett. 24. J. Melngailis, H. Lez&, Technologies V.T. Nguyen

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26 K. Asakawa, N. Takadoh, M. Uchida and T. Yuasa, NEC Research and Development 87, (October 1987).