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VLSI logic
World Abstracts on Microelectronics and Reliability CHRONES. Electron. Packaging Prodn, 35 (February 1982). For today's fast paced LSI technology, independent test laboratories offer a wide spectrum of services, from evaluations and characterizations to high volume'screening of LSI components.
Pentagon moves to expand VHSIC. RAY CONNOLLY. Electronics, 96 (5 May 1982). Proposals to include software and other technologies follow special study's praise for triservice effort. Custom ICs spread their influence. RODERIC BERESFORDand HARVEY J. HINDIN. Electronics, 93 (5 May 1982). Fourth
5. M I C R O E L E C T R O N I C S - - D E S I G N
Crystal slicing equipment directions. RON ISCOFF. Semiconductor Int., 51 (February 1982). The crystal slicing process demands a high degree of operator skill in using sophisticated equipment. Manufacturers are beginning to develop more automated systems for near-future introduction. ln-situ testability design (ISTD)--a new approach for testing high-speed LSI/VLSI logic. FRANK F. TSUI. Proc. IEEE 70 (1), 59 (1982). After a discussion of the main problems encountered in conventional methods used for testing highspeed. LSI/VLSI logic, a new approach, to be called the "'insitu testability design" (ISTD), will be presented. The approach consists of extending the use of latches and serial-shift arrangements (SSA's) provided in the hardware system to be tested, by incorporating on-chip feedback arrangements designed in such a way that the chips and modules will be self-sufficient for testability--that they will be testable in-situ and in-isolation, despite their interconnections after being assembled in the system. By proper design, chips can be made testable also on-wafer prior to their dicing. For economical implementation, arrangements for sharing the use of latches and multiplexors will be introduced and explained. The ISTD approach will fundamentally simplify and facilitate the testing of high-speed LSI/VLSI logic and greatly reduce the costs of test equipment and testing. Design procedure for its implementation, and test strategy based on its use, will be described.
Heterostrueture bipolar transistors and integrated circuits. HERBERT KROEMER. Proc. IEEE 70 (1), 13 (1982). Two new epitaxial technologies have emerged in recent years (molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD)), which offer the promise of making highly advanced heterostructures routinely available. While many kinds of devices will benefit, the principal and first beneficiary will be bipolar transistors. The underlying central principle is the use of energy gap variations beside electric fields to control the forces acting on electrons and holes, separately and independently of each other. The resulting greater design freedom permits a re-optimization of doping levels and geometries, leading to higher speed devices. Microwave transistors with maximum oscillation frequencies above 100 GHz and digital switching transistors with switching times below 10ps should become available. An inverted transistor structure with a smaller collector on top and a larger emitter on the bottom becomes possible, with speed advantages over the common "emitter-up" design. Double-heterostructure (DH) transistors with both wide-gap emitters and collectors offer additional advantages. They exhibit better performance under saturated operation. Their emitters and collectors may be interchanged by simply
193
Rochester conference typifies growth of market with papers on applications, technology and software.
Graduate and undergraduate educational methods for microelectronics. PHILLIP E. ALLEN, NOEL R. STRADER II and RANDALL L. GEIGER. IEEE Trans. Components Hybrids mfg Technol. CHMT-5 (1), 105 (1982). Methods applicable to teaching microelectronics at the undergraduate and graduate level in conjunction with an industrial fabrication capability are presented. Results of three semesters of teaching microelectronics at the graduate level with emphasis on both digital and analog circuits are summarized. Plans for teaching an undergraduate course utilizing the fabrication of integrated circuits are discussed.
AND CONSTRUCTION changing biasing conditions, greatly simplifying the architecture of bipolar IC's. Examples of heterostructure implementations of I2L and ECL are discussed. The present overwhelming dominance of the compound semiconductor device field by FET's is likely to come to an end, with bipolar devices assuming an at least equal role, and very likely a leading one.
Deep UV exposure technology. JERRY BACHUR. Solid St. Technol., 124 (February 1982). A review of Deep Ultra Violet (DUV) exposure systems is presented. The sensitivities of various commercially available photoresists are outlined. The advantages and shortcomings of a number of different DUV sources are described. Optical systems for producing collimated beams of light are discussed. The importance of measurement and control of exposure intensity in achieving repeatable results is emphasized. Finally, two exposure techniques are described: (1) alignment and exposure, and (2) flood exposure. The growth of semi-insulating gallium arsenide by the LEC process. B. LENT, M. BONNET, N. VISENTIN and J. P. DUCHEMIN. Microelectron. J. 13 (1), 5 (1982). A research and development programme has been launched at the Laboratoire Central de Recherche, to optimize the growth parameters for the production of high quality semi-insulating bulk gallium arsenide by the Liquid Encapsulation Czochralski (LEC) technique. Mono-crystals up to 3" diameter, weighing up to 2.5ks, have been grown and assessed for a range of crystal-growth parameters. A method of minimizing the concentration of gallium inclusions within the bulk material is described. Finally, we discuss an alternative method of minimizing arsenic loss, namely growth under a partial pressure of arsenic, and present preliminary thoughts on the concept of a "hot wall" puller. Wafer flatness testing. TED C. BETTES.Semiconductor Int., 77 (February 1982). A major commitment to automated flatness testing has been made by some equipment manufacturers, but manual systems will continue to hold a spot in the marketplace. The most common methods of measuring flatness are acoustic, interferometric, capacitance, and reflected laser beam. Comparison of GaAs device approaches for ultrahigh-speed VLSI. RICHARD C. EDEN. Proc. IEEE 70 (1), 5 (1982). The superior electronic properties of gallium arsenide and related III-V compound semiconductors, as compared with silicon, have made them of great interest for ultrahigh-speed logic applications. Many ingenious device structures have been proposed or demonstrated for utilizing the advantageous
Pentagon moves to expand VHSIC. RAY CONNOLLY. Electronics, 96 (5 May 1982). Proposals to include software and other technologies follow special study's praise for triservice effort. Custom ICs spread their influence. RODERIC BERESFORDand HARVEY J. HINDIN. Electronics, 93 (5 May 1982). Fourth
5. M I C R O E L E C T R O N I C S - - D E S I G N
Crystal slicing equipment directions. RON ISCOFF. Semiconductor Int., 51 (February 1982). The crystal slicing process demands a high degree of operator skill in using sophisticated equipment. Manufacturers are beginning to develop more automated systems for near-future introduction. ln-situ testability design (ISTD)--a new approach for testing high-speed LSI/VLSI logic. FRANK F. TSUI. Proc. IEEE 70 (1), 59 (1982). After a discussion of the main problems encountered in conventional methods used for testing highspeed. LSI/VLSI logic, a new approach, to be called the "'insitu testability design" (ISTD), will be presented. The approach consists of extending the use of latches and serial-shift arrangements (SSA's) provided in the hardware system to be tested, by incorporating on-chip feedback arrangements designed in such a way that the chips and modules will be self-sufficient for testability--that they will be testable in-situ and in-isolation, despite their interconnections after being assembled in the system. By proper design, chips can be made testable also on-wafer prior to their dicing. For economical implementation, arrangements for sharing the use of latches and multiplexors will be introduced and explained. The ISTD approach will fundamentally simplify and facilitate the testing of high-speed LSI/VLSI logic and greatly reduce the costs of test equipment and testing. Design procedure for its implementation, and test strategy based on its use, will be described.
Heterostrueture bipolar transistors and integrated circuits. HERBERT KROEMER. Proc. IEEE 70 (1), 13 (1982). Two new epitaxial technologies have emerged in recent years (molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD)), which offer the promise of making highly advanced heterostructures routinely available. While many kinds of devices will benefit, the principal and first beneficiary will be bipolar transistors. The underlying central principle is the use of energy gap variations beside electric fields to control the forces acting on electrons and holes, separately and independently of each other. The resulting greater design freedom permits a re-optimization of doping levels and geometries, leading to higher speed devices. Microwave transistors with maximum oscillation frequencies above 100 GHz and digital switching transistors with switching times below 10ps should become available. An inverted transistor structure with a smaller collector on top and a larger emitter on the bottom becomes possible, with speed advantages over the common "emitter-up" design. Double-heterostructure (DH) transistors with both wide-gap emitters and collectors offer additional advantages. They exhibit better performance under saturated operation. Their emitters and collectors may be interchanged by simply
193
Rochester conference typifies growth of market with papers on applications, technology and software.
Graduate and undergraduate educational methods for microelectronics. PHILLIP E. ALLEN, NOEL R. STRADER II and RANDALL L. GEIGER. IEEE Trans. Components Hybrids mfg Technol. CHMT-5 (1), 105 (1982). Methods applicable to teaching microelectronics at the undergraduate and graduate level in conjunction with an industrial fabrication capability are presented. Results of three semesters of teaching microelectronics at the graduate level with emphasis on both digital and analog circuits are summarized. Plans for teaching an undergraduate course utilizing the fabrication of integrated circuits are discussed.
AND CONSTRUCTION changing biasing conditions, greatly simplifying the architecture of bipolar IC's. Examples of heterostructure implementations of I2L and ECL are discussed. The present overwhelming dominance of the compound semiconductor device field by FET's is likely to come to an end, with bipolar devices assuming an at least equal role, and very likely a leading one.
Deep UV exposure technology. JERRY BACHUR. Solid St. Technol., 124 (February 1982). A review of Deep Ultra Violet (DUV) exposure systems is presented. The sensitivities of various commercially available photoresists are outlined. The advantages and shortcomings of a number of different DUV sources are described. Optical systems for producing collimated beams of light are discussed. The importance of measurement and control of exposure intensity in achieving repeatable results is emphasized. Finally, two exposure techniques are described: (1) alignment and exposure, and (2) flood exposure. The growth of semi-insulating gallium arsenide by the LEC process. B. LENT, M. BONNET, N. VISENTIN and J. P. DUCHEMIN. Microelectron. J. 13 (1), 5 (1982). A research and development programme has been launched at the Laboratoire Central de Recherche, to optimize the growth parameters for the production of high quality semi-insulating bulk gallium arsenide by the Liquid Encapsulation Czochralski (LEC) technique. Mono-crystals up to 3" diameter, weighing up to 2.5ks, have been grown and assessed for a range of crystal-growth parameters. A method of minimizing the concentration of gallium inclusions within the bulk material is described. Finally, we discuss an alternative method of minimizing arsenic loss, namely growth under a partial pressure of arsenic, and present preliminary thoughts on the concept of a "hot wall" puller. Wafer flatness testing. TED C. BETTES.Semiconductor Int., 77 (February 1982). A major commitment to automated flatness testing has been made by some equipment manufacturers, but manual systems will continue to hold a spot in the marketplace. The most common methods of measuring flatness are acoustic, interferometric, capacitance, and reflected laser beam. Comparison of GaAs device approaches for ultrahigh-speed VLSI. RICHARD C. EDEN. Proc. IEEE 70 (1), 5 (1982). The superior electronic properties of gallium arsenide and related III-V compound semiconductors, as compared with silicon, have made them of great interest for ultrahigh-speed logic applications. Many ingenious device structures have been proposed or demonstrated for utilizing the advantageous