- Email: [email protected]
Novel design of the output stage for four-phase dynamic VLSI logic
0026-269218411503-0012 $5.0010
Novel design of the output stage for four-phase dynamic VLSI logic by D. C. Patel U n i v e r s i t y of Surrey, Guildford, UK
A novel output stage design for four-phase rstioless dynamic logic is proposed for a low speed asynchronous pump circuit. The main features of the proposed circuit are that the precharge capacitance is reduced significantly, leading to lower power consumption, and the circuit can operate in the synchronous mode. Although more transistors are used in the circuit, there is no increase in the chip area.
1. Introduction Novel circuit techniques t~ allow designers to choose the optimum technology for the design of VLSI circuits. The important criteria for VLSI are low power dissipation, minimum transistor sizes, high packing density, high yield and low cost. Advantages of the ratioless dynamic logic 3.4 are that: 1. the circuit can be implemented using minimum size transistors; 2. many functions such as shift registers and flip-flops can be implemented using fewer transistors; 3. absence of race hazards due to the synchronous operation of the circuit; and 4. power dissipation is low. The only power required to drive internal circuitry is due to the precharging of the total output nodal capacitances, C, and is given by 1/2CV2fwhere f is the clock frequency. r
II
,'y-r"
9 t
C1
T2
-=--
C2
! 8
rri-n
v~., ,----~ ' T2 Fig. 1 Output Stage (pump circuit) 12
MICROELECTRONICS JOURNAL Vo115 No 3 9 1984 Benn Electronics Publications Ltd, Luton
c~ r
E-o JL
T
i
u~
II
t~
0 "o Q
-qF--~
~h
c~
i
i
~T P
J
!
T
T r
ol,-4
13
Novel design of the output stage for four.phase dynamic VLSI logic continued from page 13
2. Output stage design MOS transistors are not suitable for sourcing the large load currents which may be required for interfacing with circuits external to the chip. Typically, a current sink of a few mA is preferred on the chip for interfacing with external circuits. Figure 1 shows the design of a pump circuit in the output stage of the four-phase dynamic logic major-minor configuration for low speed applications. The operation of the circuit is asynchronous and requries a number of clock cycles to switch the output transistor T4 on or off. The salient features of the pump circuit are that by design, C1 is a comparatively large capacitor to speed the switching time of T4 due to the charge sharing between C1 and C2. C1 is approximately one order of magnitude larger than C2. The drawbacks of the circuit are that: 1. in the quiescent state (T4=off), the power dissipation due to C1 which, in practice, is of the order of tens of pico-farads, is high compared with the power dissipated by a typical gate, which has a nodal capacitance of a fraction of a pico-farad, and, 2. it occupies a relatively large chip area. In this paper a novel circuit technique, shown in Fig. 2, is proposed for the design of the output stage of the four-phase ratioless dynamic logic of the major-minor configuration. 3. Circuit operation All aspects of the operation of the circuit can be explained by considering three cases. CASE l: Vin is at logic level I and C2 is at logic level 0 During clock period ~b, C1 and C5 precharge to logic level 1 via transistors T1 and TI' respectively. Transistors T7 and T8 switch on ahd any charge on C3 and CA is discharged to ground. As transistors T4 and T8 are off, C2 is isolated from C1 and CA, and C2 remains at logic level 0. During the sampling interval ~b---l.~b2,C1 and C5 will discharge to logic level 0 as T2, T2' and T3 are on. T7 switches off. During clock period th3, T6 switches on and precharges C3 to logic level 1. T4 and T8 are switched on, but as C1 and C4 are at logic level 0, there is little effect of this on C2 and it remains at logic level 0. 3.1
CASE I1: Vin changes from logic level I to level 0 During clock period ~bl, C1 and C5 precharge to logic level. During the sampling interval ~-].th2, C1 and C5 are established at the logic level 1 asT3 is now in the offstate. T7 is switched on. C3 and CA will be discharged. During clock period ~b3,T6 and T8 switch on; C3, C4 and C2 are charged to logic level 1 and the sink transistor T5 will switch on. When ~b3 goes to logic level 0, T4 and T8 switch off and C2 will be isolated and is not affected during the subsequent ~bl clock periods whenT7 andT8 switch on and both C3 and C4 discharge to ground. 3.2
CASE II1: Vin changes from thelogic level 0 to 1 During thl clock period, C1 and C5 precharge to logic level 1. T7 and T9 switch on and C3 and CA discharge to logic level 0. During the sampling interval ~-i.~b2, C1 and C5 begin to discharge, and when the voltage difference between C1 and C2 exceeds the |hreshold voltage, Vt, T4' switches on. C1 discharges to logic level 0 and T4' conducts until C2 discharges to the threshold voltage level. During ~b3clock period T4 and T8 switch on and the charge on C2 is shared with C1 and C4. C2 goes below the threshold voltage and T5 is switched off. 3.3
4.
Results
The circuit of Fig. 2 was simulated using the well-known SPICE program and the results are shown in Fig. 3. The aspect ratio of T2, T3 and T4 was chosen to be three times the aspect ratio of the minimum size transistor to enable discharging of C2 in a single clock period. Similarly T6, T7 and T8 were scaled to enable charging C2 to logic level 1 in a single clock period. To pull C2 to below the threshold voltage level, the value of C4 were chosen to be a 14
I ! !
If ....
0 CO
,
I
I ! I I
--|
l
o 0
o
-
0
..,4' IZ
i ..
I
i
J o
I _
(A) s S I o A
o
o
15
Novel design of the output stage for (eur-tpha.~ dynamic VLSIlogic continued from page 15 ! !
9 I I I 9
4-
:
I
i
'I
4 ,
o r
! !
i
'
i
9
_
|
i
--
O
U3
! ! !
I
N
/
L
E co (u ~q
_
,% r.
O ._= (u
~r
I' i
I-
E~
I I f l
1@,
.
~
-
9
.
o
I ------1" ! ! f !
...-_-------
I I I
O
I" L~ ,M
0
(A} ~IIoA
16
r~
=b b~
quarter of the value of C2. Values of all other capacitances was determined using the intrinsic properties of MOS technology. Although more transistors are used in the implementation of the circuit, the chip area of the circuit will be approximately the same as that of the pump circuit because the overall capacitance is reduced significantly. Power dissipation is reduced as .the overall 15recharge capacitance is smaller. Simulated results show that the circuit can operate in the synchronous mode and C4 is precharged only when the sink transistor is in the active state. Consequently, for low-duty cycle oeration, i.e. for low T5 on-to-off ratio, the power saving is greater. 5. References
[1] Hostica, B. J., Kleine, U. and Zimmer, G., "DICMOS -Novel MOS logic", Electronic Letters, 18, 21 (1982), pp. 930-932. [2] Patel, D. C., "Optimizing gate interconnections in four-phase dynamic logic MOS LSI technology", The Radio and Electronic Engineer, 52, 5 (1982), pp. 224-226. [3] Penney, W. M. and Lau, L. (Eds.), "MOS Integrated Circuits", Van Nostrand (1972). [4] Mavor, J., "MOST Integrated Circu!t Engineering", lEE Publications 1973.
17
Novel design of the output stage for four-phase dynamic VLSI logic by D. C. Patel U n i v e r s i t y of Surrey, Guildford, UK
A novel output stage design for four-phase rstioless dynamic logic is proposed for a low speed asynchronous pump circuit. The main features of the proposed circuit are that the precharge capacitance is reduced significantly, leading to lower power consumption, and the circuit can operate in the synchronous mode. Although more transistors are used in the circuit, there is no increase in the chip area.
1. Introduction Novel circuit techniques t~ allow designers to choose the optimum technology for the design of VLSI circuits. The important criteria for VLSI are low power dissipation, minimum transistor sizes, high packing density, high yield and low cost. Advantages of the ratioless dynamic logic 3.4 are that: 1. the circuit can be implemented using minimum size transistors; 2. many functions such as shift registers and flip-flops can be implemented using fewer transistors; 3. absence of race hazards due to the synchronous operation of the circuit; and 4. power dissipation is low. The only power required to drive internal circuitry is due to the precharging of the total output nodal capacitances, C, and is given by 1/2CV2fwhere f is the clock frequency. r
II
,'y-r"
9 t
C1
T2
-=--
C2
! 8
rri-n
v~., ,----~ ' T2 Fig. 1 Output Stage (pump circuit) 12
MICROELECTRONICS JOURNAL Vo115 No 3 9 1984 Benn Electronics Publications Ltd, Luton
c~ r
E-o JL
T
i
u~
II
t~
0 "o Q
-qF--~
~h
c~
i
i
~T P
J
!
T
T r
ol,-4
13
Novel design of the output stage for four.phase dynamic VLSI logic continued from page 13
2. Output stage design MOS transistors are not suitable for sourcing the large load currents which may be required for interfacing with circuits external to the chip. Typically, a current sink of a few mA is preferred on the chip for interfacing with external circuits. Figure 1 shows the design of a pump circuit in the output stage of the four-phase dynamic logic major-minor configuration for low speed applications. The operation of the circuit is asynchronous and requries a number of clock cycles to switch the output transistor T4 on or off. The salient features of the pump circuit are that by design, C1 is a comparatively large capacitor to speed the switching time of T4 due to the charge sharing between C1 and C2. C1 is approximately one order of magnitude larger than C2. The drawbacks of the circuit are that: 1. in the quiescent state (T4=off), the power dissipation due to C1 which, in practice, is of the order of tens of pico-farads, is high compared with the power dissipated by a typical gate, which has a nodal capacitance of a fraction of a pico-farad, and, 2. it occupies a relatively large chip area. In this paper a novel circuit technique, shown in Fig. 2, is proposed for the design of the output stage of the four-phase ratioless dynamic logic of the major-minor configuration. 3. Circuit operation All aspects of the operation of the circuit can be explained by considering three cases. CASE l: Vin is at logic level I and C2 is at logic level 0 During clock period ~b, C1 and C5 precharge to logic level 1 via transistors T1 and TI' respectively. Transistors T7 and T8 switch on ahd any charge on C3 and CA is discharged to ground. As transistors T4 and T8 are off, C2 is isolated from C1 and CA, and C2 remains at logic level 0. During the sampling interval ~b---l.~b2,C1 and C5 will discharge to logic level 0 as T2, T2' and T3 are on. T7 switches off. During clock period th3, T6 switches on and precharges C3 to logic level 1. T4 and T8 are switched on, but as C1 and C4 are at logic level 0, there is little effect of this on C2 and it remains at logic level 0. 3.1
CASE I1: Vin changes from logic level I to level 0 During clock period ~bl, C1 and C5 precharge to logic level. During the sampling interval ~-].th2, C1 and C5 are established at the logic level 1 asT3 is now in the offstate. T7 is switched on. C3 and CA will be discharged. During clock period ~b3,T6 and T8 switch on; C3, C4 and C2 are charged to logic level 1 and the sink transistor T5 will switch on. When ~b3 goes to logic level 0, T4 and T8 switch off and C2 will be isolated and is not affected during the subsequent ~bl clock periods whenT7 andT8 switch on and both C3 and C4 discharge to ground. 3.2
CASE II1: Vin changes from thelogic level 0 to 1 During thl clock period, C1 and C5 precharge to logic level 1. T7 and T9 switch on and C3 and CA discharge to logic level 0. During the sampling interval ~-i.~b2, C1 and C5 begin to discharge, and when the voltage difference between C1 and C2 exceeds the |hreshold voltage, Vt, T4' switches on. C1 discharges to logic level 0 and T4' conducts until C2 discharges to the threshold voltage level. During ~b3clock period T4 and T8 switch on and the charge on C2 is shared with C1 and C4. C2 goes below the threshold voltage and T5 is switched off. 3.3
4.
Results
The circuit of Fig. 2 was simulated using the well-known SPICE program and the results are shown in Fig. 3. The aspect ratio of T2, T3 and T4 was chosen to be three times the aspect ratio of the minimum size transistor to enable discharging of C2 in a single clock period. Similarly T6, T7 and T8 were scaled to enable charging C2 to logic level 1 in a single clock period. To pull C2 to below the threshold voltage level, the value of C4 were chosen to be a 14
I ! !
If ....
0 CO
,
I
I ! I I
--|
l
o 0
o
-
0
..,4' IZ
i ..
I
i
J o
I _
(A) s S I o A
o
o
15
Novel design of the output stage for (eur-tpha.~ dynamic VLSIlogic continued from page 15 ! !
9 I I I 9
4-
:
I
i
'I
4 ,
o r
! !
i
'
i
9
_
|
i
--
O
U3
! ! !
I
N
/
L
E co (u ~q
_
,% r.
O ._= (u
~r
I' i
I-
E~
I I f l
1@,
.
~
-
9
.
o
I ------1" ! ! f !
...-_-------
I I I
O
I" L~ ,M
0
(A} ~IIoA
16
r~
=b b~
quarter of the value of C2. Values of all other capacitances was determined using the intrinsic properties of MOS technology. Although more transistors are used in the implementation of the circuit, the chip area of the circuit will be approximately the same as that of the pump circuit because the overall capacitance is reduced significantly. Power dissipation is reduced as .the overall 15recharge capacitance is smaller. Simulated results show that the circuit can operate in the synchronous mode and C4 is precharged only when the sink transistor is in the active state. Consequently, for low-duty cycle oeration, i.e. for low T5 on-to-off ratio, the power saving is greater. 5. References
[1] Hostica, B. J., Kleine, U. and Zimmer, G., "DICMOS -Novel MOS logic", Electronic Letters, 18, 21 (1982), pp. 930-932. [2] Patel, D. C., "Optimizing gate interconnections in four-phase dynamic logic MOS LSI technology", The Radio and Electronic Engineer, 52, 5 (1982), pp. 224-226. [3] Penney, W. M. and Lau, L. (Eds.), "MOS Integrated Circuits", Van Nostrand (1972). [4] Mavor, J., "MOST Integrated Circu!t Engineering", lEE Publications 1973.
17