GaAs metamorphic high-electron mobility transistors with selective and nonselective recess gate processes

Microelectronic Engineering 217 (2019) 111107

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Research paper

InAlAs/InGaAs/GaAs metamorphic high-electron mobility transistors with selective and nonselective recess gate processes

T

Yu-Shyan Lin , Yeh-Chang Ma ⁎

Department of Materials Science and Engineering, National Dong Hwa University, 1, Sec. 2, Da Hsueh Rd., Shou-Feng, Hualien 974, Taiwan

ARTICLE INFO

ABSTRACT

Keywords: InAlAs InGaAs MHEMT Selective etching 2-DEG

InAlAs/InGaAs metamorphic high-electron-mobility transistors (MHEMTs) on GaAs substrates are fabricated. Two kinds of gate-recess schemes—nonselective and selective etching—are investigated. The selective-etch recessed-gate process appears to be well-suited to fabricating high-performance MHEMTs. The temperature-dependent dc characteristics of MHEMTs are also investigated. The maximum extrinsic transconductance (gm,max) of the MHEMT with nonselective recess gate is 303 mS/mm, while the gm,max of the MHEMT with nonselective recess gate is 347 mS/mm. The application of the developed selective-etch recessed-gate process to MHEMTs produces the reduced leakage currents, increased reverse breakdown voltage, reduced high-frequency noise, and increased high-frequency and increased power characteristics.

1. Introduction High-electron mobility transistors (HEMTs) have attracted substantial interest for wireless applications [1,2]. Over the last few years, numerous researchers have grown InAlAs/InGaAs metamorphic highelectron-mobility transistors (MHEMTs) on GaAs substrate [3–12]. Their efforts have been focused on developing the strain-relaxed InGaAs, InAlAs or InAlGaAs composition-graded layers as the metamorphic buffer layers on the GaAs substrates. Important strides have been made in increasing the breakdown voltage in InAlAs/InGaAs HEMT's using various methods, such as the use of gate recess, composite or quantized channels, and a barrier with a high aluminum content. The etching of recessed gates is the most critical step in the fabrication of HEMTs. The step provides the benefits of a recessed-n+InGaAs-cap design. Dry etching has the advantage of highly directional etching. However, wet etching has advantages over dry etching of low cost and little damage. Nonselective wet etching using H3PO4:H2O2:H2O for InAlAs/InGaAs HEMTs has been examined. Although gate-recessed HEMTs are formed using H3PO4-based solution, a carefully monitored gate-recess step is necessary to control the saturation currents of devices [4]. Numerous selective wet etching techniques for InAlAs/InGaAs HEMT have been used, including citric acidbased solution [8,9,13], succinic acid-based solutions [3,11,14], or adipic acid solutions [15]. Our earlier works have compared the performance of the doped channel metamorphic field-effect transistors (DCMFETs) made with nonselective and selective etching [16].

⁎

However, MHEMTs that are made using H3PO4-based and succinic acidbased solutions are not yet to be compared. Accordingly, this work concerns the influences of nonselective and selective gate-recess schemes on the performance of MHEMT. 2. Device structure and experiments This epilayer structure of MHEMT was grown by molecular beam epitaxy (MBE) on an insulating GaAs substrate. The material growth began with ten periods of 185 Å-thick Al0.24Ga0.76As/15 Å-thick GaAs superlattice layers; it was followed by the growth of metamorphic buffer layer, the growth of a In0.4Al0.6As layer, delta doping (7 × 1012 cm−2), the growth of a In0.4Al0.6As layer, the growth of a In0.4Ga0.6As layer, the growth of a In0.4Al0.6As layer, delta doping (2 × 1012 cm−2), and the growth of a In0.4Al0.6As layer. The structure was completed by the growth of a 300 Å-thick n+-In0.4Ga0.6As (1 × 1019 cm−3) cap layer. Fig. 1 displays a schematic diagram of the studied MHEMT structure. The MHEMT fabrication sequence comprised mesa isolation, ohmic contact fabrication, gate recess and metallization. Mesa isolation was achieved by phosphoric acid/hydrogen peroxide mixtures, followed by source/drain ohmic metallization. Ohmic contacts were AuGeNi/Au Ohmic contacts were deposited by thermal evaporation, and were annealed in flowing nitrogen. Then, photolithographic Ni/Au Schottky gates with a gate length of 1 μm were deposited by thermal evaporation. Both gate-recess schemes were examined on separate pieces of a

Corresponding author. E-mail address: [email protected] (Y.-S. Lin).

https://doi.org/10.1016/j.mee.2019.111107 Received 18 March 2019; Received in revised form 9 July 2019; Accepted 7 August 2019 Available online 08 August 2019 0167-9317/ © 2019 Elsevier B.V. All rights reserved.

Microelectronic Engineering 217 (2019) 111107

Y.-S. Lin and Y.-C. Ma

Source

increasing the reverse breakdown voltage of the device. The improvement in breakdown voltage of the MHEMT-S herein provides a significant advantage in high-power applications. The Schottky and ideality factor for the nonselective etching device are 0.61 eV and 1.22, respectively. Furthermore, the Schottky barrier height and ideality factor for the selective etching device are 0.69 eV and 1.15, respectively. The selective etching device has a higher Schottky barrier height and a lower ideality factor than the nonselective device. Fig. 3 shows ID-VDS (drain current versus drain-to-source voltage) characteristics obtained from the studied MHEMTs at 300 K, while the figure also shows how these curves alter at high temperatures. The 300 K ID-VDS output characteristics are well behaved, displaying a sharp pinch-off and small output conductance (gd). Nearly kink-free currentvoltage characteristics are achieved. Fig. 4 plots the extrinsic transconductance (gm) and drain current of the studied devices at various temperatures. The threshold voltage of MHEMT-NS is −1.2 V while that of MHEMT-S is −1.07 V. At a drain voltage of 2 V and a gate voltage of 1 V, MHEMT-NS has a maximum drain current (IDS,max) of 427 mA/mm, whereas MHEMT-S has a maximum drain current of 478 mA/mm. Maximum extrinsic transconductances (gm,max) of 303 mS/mm for MHEMT-NS and 347 mS/mm for MHEMT-S are measured. Fig. 5 plots extrinsic transconductance, output conductance, and voltage gain at 300 K. The output conductance monotonically decreases as the drain-source voltage increases. The ratio of extrinsic transconductance to output conductance influences the voltage gain (Av). The voltage gain is expressed as.

Drain Gate

n+-In0.4Ga0.6As

300 Å +

200 Å i-In0.4Al0.6As

)

30 Å i-In0.4Al0.6As 200 Å i-In0.4Ga0.6As +

40 Å i-In0.4Al0.6As

)

2000 Å In0.4Al0.6As barrier layer Metamorphic buffer layer Al0.24Ga0.76As/GaAs superlattice layer S. I. GaAs substrate Fig. 1. Schematic cross-section of MHEMT studied herein.

single MHEMT wafer. The nonselective, wet-chemical-etched devices were gate-recessed using 1:1:30 H3PO4:H2O2:H2O. In the second scheme, selective succinic acid/NH4OH/H2O2/H2O wet chemical etching was conducted to form the gate recess, prior to the deposition of Ni/Au gate. The etch selectivity of InGaAs over InAlAs is about 100 for the selective etching solution studied herein. The mechanism of the selectivity is attributed to be the formation of aluminum oxide layer, which behaves as an etch stopper [16]. Two kinds of devices, MHEMTNS and MHEMT-S, are compared herein. The last letters (NS or S) specify whether the gate-recess scheme is nonselective or selective.

Av =

With the cap layer removed, the proposed heterostructure has a two-dimensional electron gas (2-DEG) concentration of 2.1 × 1012 cm−2 and mobility of 7910 cm2/V-s measured at room temperature. A surface leakage current is undesirable and developing methods to diminish such a leakage current is very important. Fig. 2 plots the twoterminal gate-drain diode characteristics of the MHEMT-NS and MHEMT-S. The current is measured under both reverse and forward dc bias. The criterion of the two-terminal gate-drain breakdown voltage (BVGD) is set to be a gate current of 1 mA/mm. The values of BVGD for MHEMT-NS and MHEMT-S are 14.4 V and 15.6 V, respectively. Selective etching can reduce the reverse gate leakage current in MHEMT-S,

1.0

300 K 330 K 360 K 390 K 420 K 450 K 480 K

0.8 0.6 0.4 0.2 0.0

0.6 0.4 0.2 0.0

-0.2 -0.4

-0.4

-0.6

-0.6

-0.8

-0.8 -14

-12

300 K 330 K 360 K 390 K 420 K 450 K 480 K

0.8

-0.2

-1.0 -16

(1)

gd

The voltage gain of MHEMT-S is 287, which markedly exceeds that (252.5) of MHEMT-NS. On-wafer RF measurements of the studied MHEMTs are made in the frequency range of 0.25—50 GHz using an HP8510C network analyzer. Fig. 6 plots the small-signal short-circuit current gain and maximum stable/available gain (MSG/MAG) of the studied devices. The cutoff frequencies (fT) of MHEMT-NS and MHEMT-S are 25 and 26.4 GHz, respectively. The maximum frequency of oscillation (fmax) is obtained by extrapolation at −20 dB/decade. MHEMT-S exhibits an fmax of 54.5 GHz, which is higher than that, fmax = 51 GHz, of MHEMT-NS. Table 1 provides the dc and high-frequency characteristics of the previously reported In0.42Al0.58As/In0.46Ga0.54As/GaAs MHEMT [7] and our studied In0.4Al0.6As/In0.4Ga0.6As/GaAs MHEMT-NS and MHEMT-S. The studied MHEMT-S exhibits the improved device performance. Noise is measured using an HP 8970B noise figure meter. Fig. 7 plots the minimum noise figure (NFmin) and associated power gain (Ga) against frequency of the studied MHEMTs, with each device biased at VDS = 2 V and VGS = −0.5 V. MHEMT-S exhibits a smaller noise figure and a larger associated gain than MHEMT-NS. The lower noise figure of MHEMT-S is attributable to the significantly lower leakage current [17].

3. Results and discussion

1.0

gm

-10

-8

-6

-4

-2

0

-1.0 -16

2

-14

-12

MHEMT-S

-10

-8

-6

-4

-2

Fig. 2. Gate-source current, IG, against gate-source voltage for the (a) MHEMT-NS and (b) MHEMT-S. 2

0

2

Microelectronic Engineering 217 (2019) 111107

Y.-S. Lin and Y.-C. Ma

600

600

300 K V = 0.5 V ~ -3 V GS 330 K step = -0.5 V 360 K 390 K 420 K 450 K 480 K

500 400 300

500 VGS = 0.5 V 400 VGS = 0 V 300 VGS = -0.5 V

200 100

MHEMT-S VGS = 0.5 V VGS = 0 V

VGS = -0.5 V

200

VGS = -1 V

0 0.0

300 K V = 0.5 V ~ -3 V 330 K GS 360 K step = -0.5 V 390 K 420 K 450 K 480 K

100

VGS = -1 V VGS = -1.5 V 3.0 3.5 4.0

VGS = -1.5 V 0.5

1.0

1.5

2.0

2.5

3.0

3.5

0 0.0

4.0

0.5

1.0

1.5

2.0

2.5

Fig. 3. Plot of drain current versus drain-to-source voltage for a 1 μm gate-length (a) MHEMT-NS and (b) MHEMT-S at various temperatures. 400

300 250 200

400

600

300 K 330 K 360 K 390 K 420 K 450 K 480 K

350

VDS = 2 V

300 K 330 K 360 K 390 K 420 K 450 K 480 K

350

500

300 400

250 200

300

150

600

MHEMT-S

VDS = 2 V

500 400 300

150

200

200

100

100 100

50 0 -2

-1

0

1

100

50 0 -2

0

-1

0

1

0

Gate-

Fig. 4. Extrinsic transconductance and drain current characteristics (a) MHEMT-NS and (b) MHEMT-S at various temperatures. VDS = 2 V for all curves.

250

AV

200

gd

150

200 100

gm

100

0

Voltage Gain

300

350

50

1

2

3

0

300 K

VGS= -0.5 V

500

Extransic Transconductance, gm & Output Conductance, gd

Extransic Transconductance, gm & Output Conductance, gd

400

0

600

300 K

VGS= -0.5 V

300

AV

400

250 200

gd

300

150

200

0

0

100

MHEMT-S

gm

100

Voltage Gain

300

500

50 1

2

3

0

Fig. 5. Extrinsic transconductance, output conductance and voltage gain as a function of drain–source voltage for (a) MHEMT-NS and (b) MHEMT-S.

45

45 VDS = 2 V VGS = -0.5 V

40 35

35 30

30 MSG

25

MSG

20 MAG

Current gain

15

15 10

10

0 0.1

MHEMT-S

25

20

5

VDS = 2 V VGS = -0.5 V

40

300 K

MAG

Current gain 300 K

5 1

10

0 0.1

100

1

10

100

Fig. 6. Frequency dependence of short-circuit current gain, and MAG/MSG of (a) MHEMT-NS and (b) MHEMT-S at specified gate and drain voltages.

3

Microelectronic Engineering 217 (2019) 111107

Y.-S. Lin and Y.-C. Ma

Fig. 8 plots the measured CW power performance of our devices. MHEMT-S exhibits better power characteristics than MHEMT-NS, owing to the improved IDS,max, reduced leakage current, and improved breakdown voltage in the MHEMT-S. The lower gate leakage current causes the maximum drain voltage of MHEMT-S to exceed that of MHEMT-NS, favoring a higher maximum rf power. Fig. 9 plots the fundamental output power and third-order intermodulation distortion characteristics against input power of the studied MHEMTs at 2.4 GHz. The device linearity is assessed by finding the output third-order intercept point (OIP3). The extracted OIP3 is obtained from the extrapolated intercept of the curves of fundamental output power and thirdorder intermodulation component versus input power [18]. The OIP3 values for MHEMT-NS and MHEMT-S are 15.8 and 19.3 dBm, respectively. Consequently, MHEMT-S has better device linearity than MHEMT-NS. Table 2 exhibits that the studied MHEMT-S has better

Table 1 DC and high-frequency performance of the In0.42Al0.58As/In0.46Ga0.54As MHEMT in the literature and our studied In0.4Al0.6As/In0.4Ga0.6As MHEMT-NS and MHEMT-S.

IDS,max (mA/ mm) gm,max (mS/ mm) gd (mS/mm) Av fT (GHz) fmax (GHz)

MHEMT-NS (this work)

MHEMT-S (this work)

In0.42Al0.58As/ In0.46Ga0.54As MHEMT [7]

427

478

434

303

347

274

1.2 252.5 25 51

1.2 287 26.4 54.5

1.92 140 17.5 42.2

The gate length of the three MHEMTs is 1 μm. 40

4.0

35

3.5

30

3.0

30

3.0

25

2.5

25

2.5

20

2.0

20

2.0

15

1.5

15

10

1.0

10

0.5

5

0.5

5

0.0

0 10

0.0

5.0 4.5

VDS= 2 V , VGS= -0.5 V

4.0 3.5

1.5 1.0

0

1

2

3

4

5

6

7

8

9

40

MHEMT-S

VDS= 2 V , VGS= -0.5 V

0

1

2

3

4

5

6

7

8

9

35

0 10

Fig. 7. Noise performance of (a) MHEMT-NS and (b) MHEMT-S in frequency range of 1–9 GHz.

40 30 20

60

VDS = 2 V

40

60

MHEMT-S

VGS = -0.5 V

50

VGS = -0.5 V

30

PAE

Power Gain

VDS = 2 V PAE

50

POWER GAIN

10

40

20

30

10

40 30 OUTPUT POWER

0 Output Power -10 -20 -35

-30

-25

-20

-15

-10

-5

0

5

20

0

20

10

-10

10

0 10

-20 -35

-30

-25

-20

-15

-10

-5

0

5

0 10

Fig. 8. Load-pull data of (a) MHEMT-NS and (b) MHEMT-S at 300 K. Each device is biased to VDS = 2 V and VGS = −0.5 V, and measurements are made at 2.4 and 5.8 GHz.

30 IP3 20 10 0 fundamental -10 -20 -30 third-order -40 intermodulation -50 VDS = 2 V VGS = -0.5 V -60 f1 -70 f2 -80 -90 -30 -20 -10 0 10

30 20 10 fundamental 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -30 -20

IP3

MHEMT-S

third-order intermodulation

VDS = 2 V VGS = -0.5 V f1 f2 -10

0

10

Fig. 9. Curves of fundamental output power and third-order intermodulation component as functions of input power for (a) MHEMT-NS and (b) MHEMT-S. 4

Microelectronic Engineering 217 (2019) 111107

Y.-S. Lin and Y.-C. Ma

Acknowledgments

Table 2 Noise and power performance of the studied MHEMT-NS and MHEMT-S.

NFmin (dB) Associated gain (dB) Power gain (dB) at 2.4 GHz mW ) mm

Output power (dBm/

at 2.4 GHz

PAE (%) at 2.4 GHz OIP3 (dBm) at 2.4 GHz

MHEMT-NS

MHEMT-S

1.3 19.6 18.8 12.57/90.36

1.0 24.4 19.27 14.32/135.2

44 15.8

46.2 19.3

The authors would like to thank the Ministry of Science and Technology of the Republic of China for financially supporting this research under Contract No. MOST 108-2221-E-259-002-MY2. References [1] [2] [3] [4]

noise and power characteristics than the MHEMT-NS.

[5] [6]

4. Conclusion

[7] [8]

This investigation compares MHEMTs that are fabricated by nonselective-etch recessed-gate processes with those fabricated by selective-etch recessed-gate processes. A succinic- acid-based selective etchant is utilized to recess selectively the n+-InGaAs cap layer of the MHEMT-S herein. The improved dc, rf, noise, and power characteristics make the studied MHEMT-S suitable for high-frequency and highpower applications.

[9] [10] [11] [12] [13]

Declaration of Competing Interest

[14] [15]

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

[16] [17] [18]

5

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