Influence of defects upon the forward bias admittance of metal-semiconductor interfaces

Applied Surface Science56-58 (1992)341-347 North-Holland

appmeO Surface science

Influence of defects upon the forward bias admittance of metalsemiconductor interfaces P. Muter, D. Elguennouni CNRS, LalYdratoire d'Ettttle des prquridtds Eleel~niques des Solidus, 8P 166, 38042 Grenoble Cedex, France

M . Missous, E . H . R h o d e r i e k [lcpartment of Electrical Eng#teering arid Elet'l~nies Unil,ersity of Manchester, Insrit.te of Science and Technology PO. Box 88, Manchester MbO IQD. UK

R. Baptist and A. Pellissier Dh'ision L E I I / DOPT.CENG-&qX, 38041 Grenoble Cedex. France

Received b May 1991;accepted for publication 12 July 1991

Static and dynamiCoelectrlcal properties of .~everal metal-semiconductor interfaces in which the metal thickness is a few hundred or thousand A al~ analysed. First. admittance measurements have been made under forward bias in two types of Al/n-GaAs contacts. The AI and n-GaAs layers have been prepared by molecular beam epilaxyan an n *-GaAswafer. In the first type, which shows ideal current-voltage characteristics, only an inductive effect is observed. Such a result cannot be fitted by any elTect attributable to interface states bat rather by minority carrier injection into the bulk semiconductor. In the second type. differing only in the n-GaAs surface which was prepared under inferior vacuum conditions, non-ideality of current-vobage characteristics and excesscapacitances are both seen. The bach contact being the same in both type~of samples, the onset of excess capacitance must be related to the change in the defect densi~/near the inlerface. Second, polyerystallineYSil 7/Si samples are sludled. For all these imperfect metal/semiconductor contacts, Ihe capacitance measured under Co:ward bi~e. shOws behavior which can be explained by the existence of states lying within the band sap of the semiconductor and in equilibrium with the majority carrier band.

1. Introduction Experimental techniques which are able to probe buried interfaces are not numerous and suiface-sonsitive methods generally become useless when the metal coverage exceeds some monolayers. On the contrary, some insight into the metal-semiconductor interface problem can be obtained from electrical and opto-electrieal measurements in junctions although data often correspond to averaged properties over the whole contact area. Peculiarly, interface states energetically located within the semiconductor forbidden gap should have some influence on these proper-

ties in the same way as deep levels do in the bulk. Whatever the physical origin of interface states turns out to be, these states can be thought of as carrier traps which are described by a small number of parameters. Among them, the density and the distance 6 i which separates the metal and the effective center of the interface states are of fundamental importance. If ~i amounts only to few monolayers as expected for intrinsic interface states, tunnelling of carriers between these states and the metal makes their occupancy controlled by the metal Fermi level. In such a case, the interface charge, barrier height and asseeiated properties are very lightly dependent on the ap-

01fi9-4332/02/$05.00© 1992- ElsevierScience Publishers B.V,All rights rest:wed

342

I~ ~tltTel el al. / Electrical p~,~erlies o f metal-semic~zductot intcrfilces

plied voltage. Alternatively, if states induced by defects or impurities spread over a larger thickness, their occupancy turns to be controlled by quasi Fermi levels in the semiconductor and becomes much more voltage dependent under forv,,~rd bias. Such states may not be termed interface states because they can be related to a particular preparation process. However, it is difficult to make a clear cut between what is specific of a hypothetical ideal interface and what is preparation induced as far as m~'tal-somiconduetor interface formation is never free of possible damage. Moreover, according to their spatial extension/t i, the same states may belong now to the first kind, now to the second kind when electrical properties are concerned. This paper intends to show how both static and dynamic electrical properties arc influenced by these states, Partial results have been presented previously [ 1]. In two types of A I / G a A s samples differing only in the GaAs surface preparation conditions, dramatic changes occur when vacuum conditions deteriorate. Capacitance under forward bias is shown to be even more sensitive than current-voltage characteristics. The case of YSiL~/Si samples, which display an interface Fermi level position unusually high in the forbidden band gap, will also be studied. The basic arguments needed for understanding how the interface states occupancy and therefore the potential barrier affect the electrical properties of Schottky junctions will be given and the model used for interpreting their electrical characteristics will be outlined.

2. Preparatima proceduras and electrical characterization of the samples Two metal-semiconductor interfaces have been investigated. The first kind of samples consists in epitaxial AI(I00) films grown by molecular beam epitaxy (hfBE) on I .u.m n-GaAg(100) active layers (the deping concentration is N o = 2.5 × l0 l~ era-3), themselves epitaxially grown on n +OaAs(100) substrates covered with a n + buffer layer [2]. A h e r o,~',sassing and daso~;.ng the surface oxide at 620°C, the two GaAs epilayers were ,6~oc at a substrate temperature of 560~C and

subsequent heat treatments under different atomic fluxes were achieved between 300 and 6 0 f i e to obtain the various surface reconstructions. Then. the samples were cooled dawn to 5(PC within 30 rain, the pressure lying in the mid 10- "~ Torr range. Once the background pressure had reached the low 10 -I° Torr, the AI deposition proceeds at a ~'ate of 100 . ~ / h followed by a growth rate of 1000 or 2000 A / h for 1 h. Two kinds of vacuum conditions have been utilized. The first samples were cooled down with a ion gauge running (samples labelled G-ON) whereas later ones (samples labelled G-OFF) were prepared with the ion gauge switched off and a cryopump fitted to the growth chamber. Although quadrupole mass spectrometer analysis showed only change in the partial pressure of gases but not in the nature of the residual gases themselves, both (100) and (llfl) Al orientations or a mixture of them appeared depending on the AsGa surface termination in the former case whereas (100) orientation was obtained consistently for all the GaAs reconstructions and the sharpness of the R H E E D patterns of the AI layer was improved in tile latter ease. Although a possible effect of the ion gauge is to enhance the adsorption of oxygen on GaAs surfaces [3], a continuous layer of oxide is totally unlikely both because a R H E E D pattern still exists and no appreciable frequency dispersion of the diode conductance occurs in contrast to the thin insulating layer case [4]. Yttrium suicide (YSil.7) thin films have been prepared [5] by solid phase reaction on S i ( l l l ) substrates of each doping type with impurity concentration ranging from 2 X 10 u to 10 Ic' em -3. Si substrates were chemically etched with a conven. tional procedure leaving some tens of .A of oxide on the surface before introduction in the ultravacuum chamber, then Ar ÷ sputtered and annealed 5 rain at 1000~C in order to display the 7 × 7 low-energyo electron diffraction (LEED) pattern. A 250 A thick yttrium layer was then deposited at a pressure rising up to 8 × 10 lo T o r t on the substrate held at room temperature. The substrates were subsequently heated up to 4000C for 30 rain, then 550°C for 20 rain until the L E E D pattern of the hexagonal silicide showing a

I~ Muter et al. / Electrical propcrli¢$ of m¢lal-~miconductor interface~ structure o f the AIB 2 type was obtained. Epitaxy may be virtually perfect because no mismatch exists between the silicide and the Si(I 1 I) lattice parameters but polycrystailine films were obtained here.

,00

343

it; ......................

t0"4

~24SK

104

~

Electrical properties have been studied o n diodes defined by conventional p h o t o l i t h o g r a p h i c

and etching techniques. T h e metallic areas were circular dots 0,5 ram in diameter for A I / G a A s samples and squares with side length ranging from 0.5 to 2 m m for YSi,.7/Si samples+ Back

0

contacts were achieved by metallization of the

who'e back side area which was always n +. or p÷-doped either originally for the G a A s substrates or from a foregoing implantation for Si substrates. T h e series resistance was always evaluated from the intercept of the vertical axis for the static differential resistance d V / d I plotted as a function of ~he tota[ static resistance k T / q l . Correction of the ~oitage and admittance has been made when necessary. Current-voltage I ( V ) characteristics have been recorded between 135 K and room temperature. Current densities J ( V ) are displayed for re.presentative samples of each kind: A I / n - G a A s G - O F F (fig. la), A I / n - G a A s G - O N (fig. l b ) and YSihT/P-Si (fig. 2). in the first kind, almost perfect characteristics are obtained with ideality factors between 1.01 an 1.03 in the range 240-340 K. Important degradations occur in the second kind o f samples. Current in excess o f those of G - O N samplcs are visible both at low forward and reverse voltage. Ideality factor measured beyond this range in order to be free from this recombination current contribution is 1.12 at room temperature. It grows significantly at lower temperatures so that voltages in excess of those applied to G - O F F samples are necessary to obtain the same current (figs. l a and Ib). In the latter case (fig. 2), one must notice the two b u m p s in the 180 K curve. F o r these three types of sample, I ( V ) barrier heights measured in the temperature range where thermionic current dominates are, respectively, 0.71, 0.75 and 0.76 eV. These values represent zero voltage barrier heights. Extrapolation of the reverse bias capacitance C to the flat band voltage yields 0.74 e V in the first case but is not accurate in the two other because C - 2 ( V ) is not perfectly straight. The

135 K

t 0-1oT.~'~J.~LbJ.~.L~.. +H,. i.... i,, i , , .

100

O,t 0.2 0.3 OA 0.5 0.S 0,7 0~q Voltage IV) .... ~...[.,.,i.. 1j.i r4[llyrl,.],, . . . .

le'Z I

(

b

~

104 ~

~ ~

S00K 270K

180K 150K 13GK 1o-lO ,, i ,., o 0,1 0.2 0.3 0.4 0.5 0.6 0.7 0.e voaage (V) Fig. |. Cqrrent density as a function of forward bi~ ~ltage for various temperatures in (a) a G-OFF Al/n-GaAs sample; (b) a G-ON Al/n-GaP~s sample. -~

10 '

~

I ( V ) barrier height amounts to 0.35 e V in Y S i l . 7 / n - S i , corresponding to a sum of the n and p barrier heights very close to the silicon band 10° . . . . J . . . . , . . . . , . . . . i . . . .

1fl-2 4

~

180K

10 " '

" .... ' .... ' .... ' .... 0,1 0.2 03 0.4 0.5 Vo~ge (V)

Fig. 2. Current densily as a function of forward bias voltage for various temperatures in a YSiI.-I/Si s~mple.

344

P, Murezel aL / Electricalpro~nies of metal-semiconducwr inre~aces

gap, As a first conclusion, polyctystalline metal and/or worsening of surface preparation conditions induce voltage dependent barrier heights. In AI/GaAs samples, this change clearly comas from interface modifications.

3. ~ m e n U t l forward bias capacitance results and their interprelatiall Beyond some threshold of the bias voltage, a negative differential capacitance appears in AI/GaAs G-OFF samples wheseas a positive capacitance develops in G-ON ones, as shown as an example at 130 K in fig. 3. In both cases, the absolute value of the capacitance grows with the applied voltage, V, in connection with a decrease

E~

~

(a)

E F

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C"OFF1100Hzl G~'F (lkHz) G-O~(~ ~) G'csi' kYa)

i I

Osll

f"

EFL

"

/t.:"

~

1

Fig. 4. Energy diagram of a racial/semiconductor conlaet at

(a) zero voltageand (b) undera forwardbiasvollageV. -to"

0,2

. . . . .

03

0.4

~"" Voitage (Vl " ........ t

0-5 |

0.6

0.7

og

.

0 10z

or0,

--

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]

lo" tO~

Fig.3. (a) Posillve.and (b) .cgaliv¢capacilai~.~as a funcUon of forward biasvoltagefor two hequencies irl G-OFFand G-ONAI/n-GaAssamples.

of the band bending, ~s, in the semiconductor (fig. 4) and an increase of the carrier concentrations n and p at the interface. It is therefore more interesting to fix at least one of these lwo parameters: the majority carrier concentration. This has been done in the results presented below by maintaining the conductance of the diode as a constant (figs. 5, 6, 7). This method relies on the proportionality of the diode current I and conductance G. to the raajority carrier concentration at the interface n = N c e x p ( - ~ J k T ) or ND e x p [ - ( @ ~ . - e V ) / k T ] for an n-type semiconduc~r with effective density of conduction band states Nc, doping density ND; k being the Boltzmann constant and T the temperature. Perturbafions caused by the inteffacial layer are sup-

P Muteret at / Electricalproperties6f metal-semiconductorinterfaces posed to influence only the charge and potential distributions at the interface and to modify the Richardson constant A*, not the fundamental transport mechanism so that the current density is still expressed as:

J =A*T2n/N~.

(1)

This ia checked from the absence of any signifi. cant frequency dispersion of the conductance in contrast to the metal-insulator-semiconductor case. Then the barrier height ~ and the carrier concentration u can be deduced from the plot of the values of eV needed for maintaining a constant value of J / T 2 (or approximately of the experimental conductance) as a function of T since the relation eV = On~ - kT lu(ND/n) must hold. The linearity is not perfect because @~ depends on tile interface states occupancy which is partly governed by the, voltage V. Frcm the continuity of potential and the Gauss theorem, the barrier height can be expressed (see fig. 4) from the difference between the metal work function @s,, and electronic affinity of the semiconducto; X minus the dipole potential of the interface layer, Ci being its capacitance, Q~ and Q~, res,0eetNcty, the interface slates and depletion layer charges: e Oe~ = q'M - x - ~ [Q~ + Q~]. (2) The dependence of Qls o n voltage originates first from interfaces states with density D~b(EF + eV) (see fig. 4) whose electron population increases as a result of capture rate which exceeds the emission rates towards the semiconductor and metal conduction bands and hole capture rate. Secondly, it originates from states with density D~(E~) (seo fig. 4), whose electron population decreases when the voltage V increases because of the increase of @B, involved in the first mechanism. These changes 8Qi~ in interface states charge can be eva~uated from the product of small sinusoidal variations of voltage ~ V at circular frequency ¢o= 2wf and the complex capacitance Ci~+ GiJj,~, where j ~ ¢ ~ T . The capacitance Ci~ and conductance Gi~ come f~om the contribution of the various carrier capture and emission rates which determine the displacement

345

and conduction currents in interlace states [6] For example, ira contim,.ous density D~(E~ + eV) of interface states acts as majority carrier traps, it contributes for [7]:

C~ = e2D~ E v + eV) l---tan - I,a~',

(3a)

¢o.r

and

I

Gi~=e~Dsb(EF+eV)~-~cln(l + toLr2),

(3b)

with r =(c,,n) -I where cn is the product of capture cross section or. and thermal ve!oci.~'. The complex variations 8QJ,3V then ,~@~/SV can be deduced. Therefore, the admittance is written out from the dcrivati-ce of eq. (1) and the corresponding capacitance C~,~ is found: ( 2

Cc,¢=G.~'[e D,b [[ 2

In(1 + w2¢2)

2

2---~--~i~cz (Ci+e D~)]

In(1+~2¢2)]2

2

2

tan- lto¢ 2 (4)

where C D is the depletion capacitance. A more involved expression is necessary to describe the interface admittance when minority carrier cap. ture and emission cannot be neglected. This is the case when inversion takes place near the interface for barrier heights exceeding half the band gap. In that case, the density of interface states D~b must take into account the states which act as minority carrier traps and recombination centers. In all cases, the effective conductance is also affected by a frequency depende~R ideality factor but in a far lesser extent than capacitance so that neglecting its frequency dependence is wetl justified. Static variations can he obtained when ~0 vanishes. Capacitance C has bern recorded for G-ON samples at a constant conductance G~ = 0.5 11-~ cm -2 and is shown as a functic.~', of voltage and for some frequencies in fig. 5. Co only remains at

340

1~ Muwt el aL / Eleut~qca( properties el ,twtal-~emicondnctor i.terfacea

0]

?: ~ . . . . ,,~

10"¢

~

A ~ . aaaa

¢

--

104t.f ~ ' ' "

;

10.7

1001"~t

I: :...". .....

Io',~I

.*

50kHz,

t-,':,:::.: ..

lel ....

1

"~ .......

J

Fig, 5. Capacltanccs as a function o f [op.'~ald h i a i v o l t a i c

nmasurcd at ¢onstam conductance G.~0.5 I t - l e t -~ for various frcqucncles in a G-ON AI/GaAs sample. The broken line shows the iow-frcqw~n~saturation of the capacitance which is proportional to the apparent density of interface slates in ©quilibriumv/ilh the conducli(m band of the semiconductor.

the highest frequency At the lowest frequencies, C largely exceeds C o ;rod can be approximated by C~,~ The prefactor G j being constant in e q (4), Co,~ is proportional to D~,(EF+eV) when a~'r <~ 1 and D,b "~ C, + ceDe. The first condition is checked in fig. 6 for voltages lower than 0.5 V wberc saturation of C occurs below around 10 Hz. The dispersion of data is due to less accurate measurements in the low-frequency range. The corresponding ¢, is 2 X 113-m~cm-2. For voltages higher than 0.55 V. the capacitance C does not saturate in the experimental window of frequencies (see fig. 6). This could be due either to a decrease of w, or to the failure of the calculation

of Cis and G~, because of the fast variation of D~, as a function of energy, The ~ c o n d condition is also fulfillvd because Ci=eieJ#i amounts to about 2 5 x 10 -6 F / c m " for an absolute p e r m i t tivity ei¢ u = 1 0 in F / c m and an interracial t h i c k ness #i = 4 nm (such a value is in a fair a g r e e merit with experimental ones deduced by Tseng and Wu [8]) which is three orders of magnitude larger than e2D,b Therefore, a curve which f o l lows the low frequency capacitance and shows the density D~ can be drawn on fig 5 Assuming eD, a = 1013 cV -I cm -2, the coefficient relating eD~b( e V ' cm -2) and C~¢ (F cm -2) is near 10 .6 eV I F ' so that the broken line of f i g 5 r e p r e ~ n t s densities ranging from 10 I° to 10 t2 eV - i cm -2 These are only a part of the total density because states acting as hole traps and racombi nation centers also probably exist for the lowest voltage as evidenced from the suppression of the negative capacitance seen in G O F F samples which comes from the modulation of the c o n d u c tivity of the bulk semiconductor by minority c a r t s ers [9] In contrast to A I / G a A s samples in which monotonic variations of C¢~ appear, fig 7 shows the shift of the maxima of C,~¢ with a frequency which is characteristic of a discrete interface state [6] in YSi 7 / S t The position of the lowest f r e queucy maximum near V= 0 4 0 V is in a g r e e merit with the slope break in the I(V) curve at 180 K in fig 2 which indicates the correlation 1@ .a /

o

[f e~

ao •

|o

•

0.514 V )

•

0.467 V

:!:l,, .

Io.7 ~

~

-o-s0u

o~v

I I

,el

I "o tim)

F i g 6. Capacitances ~ a f u n c l i o n of frequency r a e ~ u r e d at constant ¢ o n d u c t ~ c e G n 0 5 ~ t cm 2 for various forward bias ~ohagcs in a G q O N A l / n G a A s s ~ p l c

104 0.3O

0.4O

0.5O

0.6O

0.70

Fig, 7. Capacitances as a function o f folxvard bias vohag¢ m e a s u r e d at constant ~ n d u c t a n c e G n = 2 2 × 10 - 3 f l z c m 2 for various frequencies in a Y S i l T / S J sample. T h e arrows indicate t h e position of t h e m a x i m a a n d t h e i r shift towards h i g h e r voltages w h e n the frequency i n c r e a s e s

t~ Muter et al. / Electffcal properties of metal-semiconductor OIterfaces

between current and admittance signatures of interface states. As a conclusion, we have shown here that interface states in defective m e t a l / s e m i c o n d u c t o r interfaces arc responsible for tfle anomalous admittance and voltage dependenl' barrier heights under forward bias, Peculiarly, lhe excess capacitances are very sensitlvc to states in equilibrium with the majority cartier band o f the semiconductor and they offer a valuable tool fer characterizing preparation damages. These effects are clearly absent in perfect interfaces or replaced by inductive effects likely due to injection of minority carriers in the bulk semiconductor.

347

References [I] P. Muter, D. ElguennounL M. Missous and E.H, Rhoderic~k.AppL Phys. Lclt. 58 (1991) 155. [2) M, Mis~lus, E.It, ghaderiek and K.E. Singer. J, Appl. Ph~s, 60 (Iq~5) 2430. [3] P. Pianena, I. Lindau C.M, Garner and W,E. Spicer. phS,s. Rev. L~O.37 (1976) 1166. [41 J. Wern©r, K, Pleas and H,J. Qu¢iss~r, phys, Rev, Lcn, 57 (1986) 10811. [51 R. BaplisL A. Pellissier and G, Chauvet. Solid Stale Commun, 6g (1998) 555. [6] P. Muter. Scmicond. Sci, T¢¢hnol. 3 (1988) 321.

[71 E,H, Nicallian and A. Go~tzbvrser, Boll Sysc T©¢I:.J. 46 (1967) 1055. [8] II.H. Tseng and C.Y. Wu, J. Appl. Phys, 61 (198712e:L [t~l M.A. Green and J. Shewchun. Solid State Ele~,~roil. 16 (1973) 114l,